[people/ms/u-boot.git] / arch / arm / cpu / tegra20-common / pmu.c

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <tps6586x.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <asm/arch-tegra/sys_proto.h>

#define VDD_CORE_NOMINAL_T25	0x17	/* 1.3v */
#define VDD_CPU_NOMINAL_T25	0x10	/* 1.125v */

#define VDD_CORE_NOMINAL_T20	0x16	/* 1.275v */
#define VDD_CPU_NOMINAL_T20	0x0f	/* 1.1v */

#define VDD_RELATION		0x02	/*  50mv */
#define VDD_TRANSITION_STEP	0x06	/* 150mv */
#define VDD_TRANSITION_RATE	0x06	/* 3.52mv/us */

int pmu_set_nominal(void)
{
	int core, cpu, bus;

	/* by default, the table has been filled with T25 settings */
	switch (tegra_get_chip_sku()) {
	case TEGRA_SOC_T20:
		core = VDD_CORE_NOMINAL_T20;
		cpu = VDD_CPU_NOMINAL_T20;
		break;
	case TEGRA_SOC_T25:
		core = VDD_CORE_NOMINAL_T25;
		cpu = VDD_CPU_NOMINAL_T25;
		break;
	default:
		debug("%s: Unknown SKU id\n", __func__);
		return -1;
	}

	bus = tegra_i2c_get_dvc_bus_num();
	if (bus == -1) {
		debug("%s: Cannot find DVC I2C bus\n", __func__);
		return -1;
	}
	tps6586x_init(bus);
	tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
	return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
				VDD_TRANSITION_RATE, VDD_RELATION);
}
Commit	Line	Data
6860b4a1 JZ	1	/*
	2	* Copyright (c) 2011 The Chromium OS Authors.
	3	* (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
6860b4a1 JZ	6	*/
	7
	8	#include <common.h>
	9	#include <tps6586x.h>
	10	#include <asm/io.h>
150c2493 TW	11	#include <asm/arch/tegra.h>
	12	#include <asm/arch-tegra/ap.h>
	13	#include <asm/arch-tegra/tegra_i2c.h>
	14	#include <asm/arch-tegra/sys_proto.h>
6860b4a1 JZ	15
	16	#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
	17	#define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
	18
	19	#define VDD_CORE_NOMINAL_T20 0x16 /* 1.275v */
	20	#define VDD_CPU_NOMINAL_T20 0x0f /* 1.1v */
	21
	22	#define VDD_RELATION 0x02 /* 50mv */
	23	#define VDD_TRANSITION_STEP 0x06 /* 150mv */
	24	#define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
	25
	26	int pmu_set_nominal(void)
	27	{
	28	int core, cpu, bus;
	29
	30	/* by default, the table has been filled with T25 settings */
49493cb7	31	switch (tegra_get_chip_sku()) {
6860b4a1 JZ	32	case TEGRA_SOC_T20:
	33	core = VDD_CORE_NOMINAL_T20;
	34	cpu = VDD_CPU_NOMINAL_T20;
	35	break;
	36	case TEGRA_SOC_T25:
	37	core = VDD_CORE_NOMINAL_T25;
	38	cpu = VDD_CPU_NOMINAL_T25;
	39	break;
	40	default:
49493cb7	41	debug("%s: Unknown SKU id\n", __func__);
6860b4a1 JZ	42	return -1;
	43	}
	44
	45	bus = tegra_i2c_get_dvc_bus_num();
	46	if (bus == -1) {
	47	debug("%s: Cannot find DVC I2C bus\n", __func__);
	48	return -1;
	49	}
	50	tps6586x_init(bus);
	51	tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
	52	return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
	53	VDD_TRANSITION_RATE, VDD_RELATION);
	54	}