[people/ms/u-boot.git] / arch / arm / dts / armada-385-turris-omnia.dts

/*
 * Device Tree file for the Turris Omnia
 *
 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is licensed under the terms of the GNU General Public
 *     License version 2.  This program is licensed "as is" without
 *     any warranty of any kind, whether express or implied.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385.dtsi"

/ {
	model = "Turris Omnia";
	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";

	chosen {
		stdout-path = &uart0;
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1024 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;

		internal-regs {

			/* USB part of the PCIe2/USB 2.0 port */
			usb@58000 {
				status = "okay";
			};

			sata@a8000 {
				status = "okay";
			};

			sdhci@d8000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sdhci_pins>;
				status = "okay";

				bus-width = <8>;
				no-1-8-v;
				non-removable;
			};

			usb3@f0000 {
				status = "okay";
			};

			usb3@f8000 {
				status = "okay";
			};
		};

		pcie-controller {
			status = "okay";

			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};

			pcie@3,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
		};
	};
};

/* Connected to 88E6176 switch, port 6 */
&eth0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ge0_rgmii_pins>;
	status = "okay";
	phy-mode = "rgmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

/* Connected to 88E6176 switch, port 5 */
&eth1 {
	pinctrl-names = "default";
	pinctrl-0 = <&ge1_rgmii_pins>;
	status = "okay";
	phy-mode = "rgmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

/* WAN port */
&eth2 {
	status = "okay";
	phy-mode = "sgmii";
	phy = <&phy1>;
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	i2cmux@70 {
		compatible = "nxp,pca9547";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
		status = "okay";

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			/* STM32F0 command interface at address 0x2a */
			/* leds device (in STM32F0) at address 0x2b */

			eeprom@54 {
				compatible = "at,24c64";
				reg = <0x54>;

				/* The EEPROM contains data for bootloader.
				 * Contents:
				 * 	struct omnia_eeprom {
				 * 		u32 magic; (=0x0341a034 in LE)
				 *		u32 ramsize; (in GiB)
				 * 		char regdomain[4];
				 * 		u32 crc32;
				 * 	};
				 */
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			/* routed to PCIe0/mSATA connector (CN7A) */
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			/* routed to PCIe1/USB2 connector (CN61A) */
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			/* routed to PCIe2 connector (CN62A) */
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;

			/* routed to SFP+ */
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;

			/* ATSHA204A at address 0x64 */
		};

		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;

			/* exposed on pin header */
		};

		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;

			pcawan: gpio@71 {
				/*
				 * GPIO expander for SFP+ signals and
				 * and phy irq
				 */
				compatible = "nxp,pca9538";
				reg = <0x71>;

				pinctrl-names = "default";
				pinctrl-0 = <&pcawan_pins>;

				interrupt-parent = <&gpio1>;
				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;

				gpio-controller;
				#gpio-cells = <2>;
			};
		};
	};
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	phy1: phy@1 {
		status = "okay";
		compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
		reg = <1>;

		/* irq is connected to &pcawan pin 7 */
	};

	/* Switch MV88E6176 at address 0x10 */
	switch@10 {
		compatible = "marvell,mv88e6085";
		#address-cells = <1>;
		#size-cells = <0>;
		dsa,member = <0 0>;

		reg = <0x10>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			ports@0 {
				reg = <0>;
				label = "lan0";
			};

			ports@1 {
				reg = <1>;
				label = "lan1";
			};

			ports@2 {
				reg = <2>;
				label = "lan2";
			};

			ports@3 {
				reg = <3>;
				label = "lan3";
			};

			ports@4 {
				reg = <4>;
				label = "lan4";
			};

			ports@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&eth1>;
				phy-mode = "rgmii-id";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			/* port 6 is connected to eth0 */
		};
	};
};

&pinctrl {
	pcawan_pins: pcawan-pins {
		marvell,pins = "mpp46";
		marvell,function = "gpio";
	};

	spi0cs0_pins: spi0cs0-pins {
		marvell,pins = "mpp25";
		marvell,function = "spi0";
	};

	spi0cs1_pins: spi0cs1-pins {
		marvell,pins = "mpp26";
		marvell,function = "spi0";
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
	status = "okay";

	spi-nor@0 {
		compatible = "spansion,s25fl164k", "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-max-frequency = <40000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				reg = <0x0 0x00100000>;
				label = "U-Boot";
			};

			partition@100000 {
				reg = <0x00100000 0x00700000>;
				label = "Rescue system";
			};
		};
	};

	/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
};

&uart0 {
	/* Pin header CN10 */
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart1 {
	/* Pin header CN11 */
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};
Commit	Line	Data
c2502e7b MB	1	/*
	2	* Device Tree file for the Turris Omnia
	3	*
	4	* Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
	5	* Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
	6	*
	7	* This file is dual-licensed: you can use it either under the terms
	8	* of the GPL or the X11 license, at your option. Note that this dual
	9	* licensing only applies to this file, and not this project as a
	10	* whole.
	11	*
	12	* a) This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without
	14	* any warranty of any kind, whether express or implied.
	15	*
	16	* Or, alternatively,
	17	*
	18	* b) Permission is hereby granted, free of charge, to any person
	19	* obtaining a copy of this software and associated documentation
	20	* files (the "Software"), to deal in the Software without
	21	* restriction, including without limitation the rights to use,
	22	* copy, modify, merge, publish, distribute, sublicense, and/or
	23	* sell copies of the Software, and to permit persons to whom the
	24	* Software is furnished to do so, subject to the following
	25	* conditions:
	26	*
	27	* The above copyright notice and this permission notice shall be
	28	* included in all copies or substantial portions of the Software.
	29	*
	30	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	31	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	32	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	33	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	34	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	35	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	36	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	37	* OTHER DEALINGS IN THE SOFTWARE.
	38	*/
	39
	40	/*
	41	* Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
	42	*/
	43
	44	/dts-v1/;
	45
	46	#include <dt-bindings/gpio/gpio.h>
	47	#include <dt-bindings/input/input.h>
	48	#include "armada-385.dtsi"
	49
	50	/ {
	51	model = "Turris Omnia";
	52	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
	53
	54	chosen {
	55	stdout-path = &uart0;
	56	};
	57
	58	memory {
	59	device_type = "memory";
	60	reg = <0x00000000 0x40000000>; /* 1024 MB */
	61	};
	62
	63	soc {
	64	ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
65	MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
66	MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
67	MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
68
69	internal-regs {
70
71	/* USB part of the PCIe2/USB 2.0 port */
72	usb@58000 {
73	status = "okay";
74	};
75
76	sata@a8000 {
77	status = "okay";
78	};
79
80	sdhci@d8000 {
81	pinctrl-names = "default";
82	pinctrl-0 = <&sdhci_pins>;
83	status = "okay";
84
85	bus-width = <8>;
86	no-1-8-v;
87	non-removable;
88	};
89
90	usb3@f0000 {
91	status = "okay";
92	};
93
94	usb3@f8000 {
95	status = "okay";
96	};
97	};
98
99	pcie-controller {
100	status = "okay";
101
102	pcie@1,0 {
103	/* Port 0, Lane 0 */
104	status = "okay";
105	};
106
107	pcie@2,0 {
108	/* Port 1, Lane 0 */
109	status = "okay";
110	};
111
112	pcie@3,0 {
113	/* Port 2, Lane 0 */
114	status = "okay";
115	};
116	};
117	};
118	};
119
120	/* Connected to 88E6176 switch, port 6 */
121	&eth0 {
122	pinctrl-names = "default";
123	pinctrl-0 = <&ge0_rgmii_pins>;
124	status = "okay";
125	phy-mode = "rgmii";
126
127	fixed-link {
128	speed = <1000>;
129	full-duplex;
130	};
131	};
132
133	/* Connected to 88E6176 switch, port 5 */
134	&eth1 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&ge1_rgmii_pins>;
137	status = "okay";
138	phy-mode = "rgmii";
139
140	fixed-link {
141	speed = <1000>;
142	full-duplex;
143	};
144	};
145
146	/* WAN port */
147	&eth2 {
148	status = "okay";
149	phy-mode = "sgmii";
150	phy = <&phy1>;
151	};
152
153	&i2c0 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&i2c0_pins>;
156	status = "okay";
157
158	i2cmux@70 {
159	compatible = "nxp,pca9547";
160	#address-cells = <1>;
161	#size-cells = <0>;
162	reg = <0x70>;
163	status = "okay";
164
165	i2c@0 {
166	#address-cells = <1>;
167	#size-cells = <0>;
168	reg = <0>;
169
170	/* STM32F0 command interface at address 0x2a */
171	/* leds device (in STM32F0) at address 0x2b */
172
173	eeprom@54 {
174	compatible = "at,24c64";
175	reg = <0x54>;
176
177	/* The EEPROM contains data for bootloader.
178	* Contents:
179	* struct omnia_eeprom {
180	* u32 magic; (=0x0341a034 in LE)
181	* u32 ramsize; (in GiB)
182	* char regdomain[4];
183	* u32 crc32;
184	* };
185	*/
186	};
187	};
188
189	i2c@1 {
190	#address-cells = <1>;
191	#size-cells = <0>;
192	reg = <1>;
193
194	/* routed to PCIe0/mSATA connector (CN7A) */
195	};
196
197	i2c@2 {
198	#address-cells = <1>;
199	#size-cells = <0>;
200	reg = <2>;
201
202	/* routed to PCIe1/USB2 connector (CN61A) */
203	};
204
205	i2c@3 {
206	#address-cells = <1>;
207	#size-cells = <0>;
208	reg = <3>;
209
210	/* routed to PCIe2 connector (CN62A) */
211	};
212
213	i2c@4 {
214	#address-cells = <1>;
215	#size-cells = <0>;
216	reg = <4>;
217
218	/* routed to SFP+ */
219	};
220
221	i2c@5 {
222	#address-cells = <1>;
223	#size-cells = <0>;
224	reg = <5>;
225
226	/* ATSHA204A at address 0x64 */
227	};
228
229	i2c@6 {
230	#address-cells = <1>;
231	#size-cells = <0>;
232	reg = <6>;
233
234	/* exposed on pin header */
235	};
236
237	i2c@7 {
238	#address-cells = <1>;
239	#size-cells = <0>;
240	reg = <7>;
241
242	pcawan: gpio@71 {
243	/*
244	* GPIO expander for SFP+ signals and
245	* and phy irq
246	*/
247	compatible = "nxp,pca9538";
248	reg = <0x71>;
249
250	pinctrl-names = "default";
251	pinctrl-0 = <&pcawan_pins>;
252
253	interrupt-parent = <&gpio1>;
254	interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
255
256	gpio-controller;
257	#gpio-cells = <2>;
258	};
259	};
260	};
261	};
262
263	&mdio {
264	pinctrl-names = "default";
265	pinctrl-0 = <&mdio_pins>;
266	status = "okay";
267
268	phy1: phy@1 {
269	status = "okay";
270	compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
271	reg = <1>;
272
273	/* irq is connected to &pcawan pin 7 */
274	};
275
276	/* Switch MV88E6176 at address 0x10 */
277	switch@10 {
278	compatible = "marvell,mv88e6085";
279	#address-cells = <1>;
280	#size-cells = <0>;
281	dsa,member = <0 0>;
282
283	reg = <0x10>;
284
285	ports {
286	#address-cells = <1>;
287	#size-cells = <0>;
288
289	ports@0 {
290	reg = <0>;
291	label = "lan0";
292	};
293
294	ports@1 {
295	reg = <1>;
296	label = "lan1";
297	};
298
299	ports@2 {
300	reg = <2>;
301	label = "lan2";
302	};
303
304	ports@3 {
305	reg = <3>;
306	label = "lan3";
307	};
308
309	ports@4 {
310	reg = <4>;
311	label = "lan4";
312	};
313
314	ports@5 {
315	reg = <5>;
316	label = "cpu";
317	ethernet = <&eth1>;
318	phy-mode = "rgmii-id";
319
320	fixed-link {
321	speed = <1000>;
322	full-duplex;
323	};
324	};
325
326	/* port 6 is connected to eth0 */
327	};
328	};
329	};
330
331	&pinctrl {
332	pcawan_pins: pcawan-pins {
333	marvell,pins = "mpp46";
334	marvell,function = "gpio";
335	};
336
337	spi0cs0_pins: spi0cs0-pins {
338	marvell,pins = "mpp25";
339	marvell,function = "spi0";
340	};
341
342	spi0cs1_pins: spi0cs1-pins {
343	marvell,pins = "mpp26";
344	marvell,function = "spi0";
345	};
346	};
347
348	&spi0 {
349	pinctrl-names = "default";
350	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
351	status = "okay";
352
353	spi-nor@0 {
354	compatible = "spansion,s25fl164k", "jedec,spi-nor";
355	#address-cells = <1>;
356	#size-cells = <1>;
357	reg = <0>;
358	spi-max-frequency = <40000000>;
359
360	partitions {
361	compatible = "fixed-partitions";
362	#address-cells = <1>;
363	#size-cells = <1>;
364
365	partition@0 {
366	reg = <0x0 0x00100000>;
367	label = "U-Boot";
368	};
369
370	partition@100000 {
371	reg = <0x00100000 0x00700000>;
372	label = "Rescue system";
373	};
374	};
375	};
376
377	/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
378	};
379
380	&uart0 {
381	/* Pin header CN10 */
382	pinctrl-names = "default";
383	pinctrl-0 = <&uart0_pins>;
384	status = "okay";
385	};
386
387	&uart1 {
388	/* Pin header CN11 */
389	pinctrl-names = "default";
390	pinctrl-0 = <&uart1_pins>;
391	status = "okay";
392	};