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39a230aa SR |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 38x family of SoCs. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is dual-licensed: you can use it either under the terms | |
11 | * of the GPL or the X11 license, at your option. Note that this dual | |
12 | * licensing only applies to this file, and not this project as a | |
13 | * whole. | |
14 | * | |
15 | * a) This file is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of the | |
18 | * License, or (at your option) any later version. | |
19 | * | |
20 | * This file is distributed in the hope that it will be useful | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * Or, alternatively | |
26 | * | |
27 | * b) Permission is hereby granted, free of charge, to any person | |
28 | * obtaining a copy of this software and associated documentation | |
29 | * files (the "Software"), to deal in the Software without | |
30 | * restriction, including without limitation the rights to use | |
31 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
32 | * sell copies of the Software, and to permit persons to whom the | |
33 | * Software is furnished to do so, subject to the following | |
34 | * conditions: | |
35 | * | |
36 | * The above copyright notice and this permission notice shall be | |
37 | * included in all copies or substantial portions of the Software. | |
38 | * | |
39 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
40 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
41 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
42 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
43 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
44 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
45 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
46 | * OTHER DEALINGS IN THE SOFTWARE. | |
47 | */ | |
48 | ||
49 | #include "skeleton.dtsi" | |
50 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
51 | #include <dt-bindings/interrupt-controller/irq.h> | |
52 | ||
53 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | |
54 | ||
55 | / { | |
56 | model = "Marvell Armada 38x family SoC"; | |
57 | compatible = "marvell,armada380"; | |
58 | ||
59 | aliases { | |
60 | gpio0 = &gpio0; | |
61 | gpio1 = &gpio1; | |
62 | serial0 = &uart0; | |
63 | serial1 = &uart1; | |
64 | }; | |
65 | ||
66 | pmu { | |
67 | compatible = "arm,cortex-a9-pmu"; | |
68 | interrupts-extended = <&mpic 3>; | |
69 | }; | |
70 | ||
71 | soc { | |
72 | compatible = "marvell,armada380-mbus", "simple-bus"; | |
09a54c00 | 73 | u-boot,dm-pre-reloc; |
39a230aa SR |
74 | #address-cells = <2>; |
75 | #size-cells = <1>; | |
76 | controller = <&mbusc>; | |
77 | interrupt-parent = <&gic>; | |
78 | pcie-mem-aperture = <0xe0000000 0x8000000>; | |
79 | pcie-io-aperture = <0xe8000000 0x100000>; | |
80 | ||
81 | bootrom { | |
82 | compatible = "marvell,bootrom"; | |
83 | reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; | |
84 | }; | |
85 | ||
86 | devbus-bootcs { | |
87 | compatible = "marvell,mvebu-devbus"; | |
88 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | |
89 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | |
90 | #address-cells = <1>; | |
91 | #size-cells = <1>; | |
92 | clocks = <&coreclk 0>; | |
93 | status = "disabled"; | |
94 | }; | |
95 | ||
96 | devbus-cs0 { | |
97 | compatible = "marvell,mvebu-devbus"; | |
98 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | |
99 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | |
100 | #address-cells = <1>; | |
101 | #size-cells = <1>; | |
102 | clocks = <&coreclk 0>; | |
103 | status = "disabled"; | |
104 | }; | |
105 | ||
106 | devbus-cs1 { | |
107 | compatible = "marvell,mvebu-devbus"; | |
108 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | |
109 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | |
110 | #address-cells = <1>; | |
111 | #size-cells = <1>; | |
112 | clocks = <&coreclk 0>; | |
113 | status = "disabled"; | |
114 | }; | |
115 | ||
116 | devbus-cs2 { | |
117 | compatible = "marvell,mvebu-devbus"; | |
118 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | |
119 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | |
120 | #address-cells = <1>; | |
121 | #size-cells = <1>; | |
122 | clocks = <&coreclk 0>; | |
123 | status = "disabled"; | |
124 | }; | |
125 | ||
126 | devbus-cs3 { | |
127 | compatible = "marvell,mvebu-devbus"; | |
128 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | |
129 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | |
130 | #address-cells = <1>; | |
131 | #size-cells = <1>; | |
132 | clocks = <&coreclk 0>; | |
133 | status = "disabled"; | |
134 | }; | |
135 | ||
136 | internal-regs { | |
137 | compatible = "simple-bus"; | |
09a54c00 | 138 | u-boot,dm-pre-reloc; |
39a230aa SR |
139 | #address-cells = <1>; |
140 | #size-cells = <1>; | |
141 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | |
142 | ||
143 | L2: cache-controller@8000 { | |
144 | compatible = "arm,pl310-cache"; | |
145 | reg = <0x8000 0x1000>; | |
146 | cache-unified; | |
147 | cache-level = <2>; | |
148 | }; | |
149 | ||
150 | scu@c000 { | |
151 | compatible = "arm,cortex-a9-scu"; | |
152 | reg = <0xc000 0x58>; | |
153 | }; | |
154 | ||
155 | timer@c600 { | |
156 | compatible = "arm,cortex-a9-twd-timer"; | |
157 | reg = <0xc600 0x20>; | |
158 | interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; | |
159 | clocks = <&coreclk 2>; | |
160 | }; | |
161 | ||
162 | gic: interrupt-controller@d000 { | |
163 | compatible = "arm,cortex-a9-gic"; | |
164 | #interrupt-cells = <3>; | |
165 | #size-cells = <0>; | |
166 | interrupt-controller; | |
167 | reg = <0xd000 0x1000>, | |
168 | <0xc100 0x100>; | |
169 | }; | |
170 | ||
171 | spi0: spi@10600 { | |
172 | compatible = "marvell,armada-380-spi", | |
173 | "marvell,orion-spi"; | |
174 | reg = <0x10600 0x50>; | |
175 | #address-cells = <1>; | |
176 | #size-cells = <0>; | |
177 | cell-index = <0>; | |
178 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
179 | clocks = <&coreclk 0>; | |
180 | status = "disabled"; | |
181 | }; | |
182 | ||
183 | spi1: spi@10680 { | |
184 | compatible = "marvell,armada-380-spi", | |
185 | "marvell,orion-spi"; | |
186 | reg = <0x10680 0x50>; | |
187 | #address-cells = <1>; | |
188 | #size-cells = <0>; | |
189 | cell-index = <1>; | |
190 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
191 | clocks = <&coreclk 0>; | |
192 | status = "disabled"; | |
193 | }; | |
194 | ||
195 | i2c0: i2c@11000 { | |
196 | compatible = "marvell,mv64xxx-i2c"; | |
197 | reg = <0x11000 0x20>; | |
198 | #address-cells = <1>; | |
199 | #size-cells = <0>; | |
200 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
201 | timeout-ms = <1000>; | |
202 | clocks = <&coreclk 0>; | |
203 | status = "disabled"; | |
204 | }; | |
205 | ||
206 | i2c1: i2c@11100 { | |
207 | compatible = "marvell,mv64xxx-i2c"; | |
208 | reg = <0x11100 0x20>; | |
209 | #address-cells = <1>; | |
210 | #size-cells = <0>; | |
211 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
212 | timeout-ms = <1000>; | |
213 | clocks = <&coreclk 0>; | |
214 | status = "disabled"; | |
215 | }; | |
216 | ||
217 | uart0: serial@12000 { | |
218 | compatible = "snps,dw-apb-uart"; | |
219 | reg = <0x12000 0x100>; | |
220 | reg-shift = <2>; | |
221 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
222 | reg-io-width = <1>; | |
223 | clocks = <&coreclk 0>; | |
224 | status = "disabled"; | |
225 | }; | |
226 | ||
227 | uart1: serial@12100 { | |
228 | compatible = "snps,dw-apb-uart"; | |
229 | reg = <0x12100 0x100>; | |
230 | reg-shift = <2>; | |
231 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
232 | reg-io-width = <1>; | |
233 | clocks = <&coreclk 0>; | |
234 | status = "disabled"; | |
235 | }; | |
236 | ||
237 | pinctrl: pinctrl@18000 { | |
238 | reg = <0x18000 0x20>; | |
239 | ||
240 | ge0_rgmii_pins: ge-rgmii-pins-0 { | |
241 | marvell,pins = "mpp6", "mpp7", "mpp8", | |
242 | "mpp9", "mpp10", "mpp11", | |
243 | "mpp12", "mpp13", "mpp14", | |
244 | "mpp15", "mpp16", "mpp17"; | |
245 | marvell,function = "ge0"; | |
246 | }; | |
247 | ||
248 | ge1_rgmii_pins: ge-rgmii-pins-1 { | |
249 | marvell,pins = "mpp21", "mpp27", "mpp28", | |
250 | "mpp29", "mpp30", "mpp31", | |
251 | "mpp32", "mpp37", "mpp38", | |
252 | "mpp39", "mpp40", "mpp41"; | |
253 | marvell,function = "ge1"; | |
254 | }; | |
255 | ||
256 | i2c0_pins: i2c-pins-0 { | |
257 | marvell,pins = "mpp2", "mpp3"; | |
258 | marvell,function = "i2c0"; | |
259 | }; | |
260 | ||
261 | mdio_pins: mdio-pins { | |
262 | marvell,pins = "mpp4", "mpp5"; | |
263 | marvell,function = "ge"; | |
264 | }; | |
265 | ||
266 | ref_clk0_pins: ref-clk-pins-0 { | |
267 | marvell,pins = "mpp45"; | |
268 | marvell,function = "ref"; | |
269 | }; | |
270 | ||
271 | ref_clk1_pins: ref-clk-pins-1 { | |
272 | marvell,pins = "mpp46"; | |
273 | marvell,function = "ref"; | |
274 | }; | |
275 | ||
276 | spi0_pins: spi-pins-0 { | |
277 | marvell,pins = "mpp22", "mpp23", "mpp24", | |
278 | "mpp25"; | |
279 | marvell,function = "spi0"; | |
280 | }; | |
281 | ||
282 | spi1_pins: spi-pins-1 { | |
283 | marvell,pins = "mpp56", "mpp57", "mpp58", | |
284 | "mpp59"; | |
285 | marvell,function = "spi1"; | |
286 | }; | |
287 | ||
288 | uart0_pins: uart-pins-0 { | |
289 | marvell,pins = "mpp0", "mpp1"; | |
290 | marvell,function = "ua0"; | |
291 | }; | |
292 | ||
293 | uart1_pins: uart-pins-1 { | |
294 | marvell,pins = "mpp19", "mpp20"; | |
295 | marvell,function = "ua1"; | |
296 | }; | |
297 | ||
298 | sdhci_pins: sdhci-pins { | |
299 | marvell,pins = "mpp48", "mpp49", "mpp50", | |
300 | "mpp52", "mpp53", "mpp54", | |
301 | "mpp55", "mpp57", "mpp58", | |
302 | "mpp59"; | |
303 | marvell,function = "sd0"; | |
304 | }; | |
305 | ||
306 | sata0_pins: sata-pins-0 { | |
307 | marvell,pins = "mpp20"; | |
308 | marvell,function = "sata0"; | |
309 | }; | |
310 | ||
311 | sata1_pins: sata-pins-1 { | |
312 | marvell,pins = "mpp19"; | |
313 | marvell,function = "sata1"; | |
314 | }; | |
315 | ||
316 | sata2_pins: sata-pins-2 { | |
317 | marvell,pins = "mpp47"; | |
318 | marvell,function = "sata2"; | |
319 | }; | |
320 | ||
321 | sata3_pins: sata-pins-3 { | |
322 | marvell,pins = "mpp44"; | |
323 | marvell,function = "sata3"; | |
324 | }; | |
325 | }; | |
326 | ||
327 | gpio0: gpio@18100 { | |
328 | compatible = "marvell,orion-gpio"; | |
329 | reg = <0x18100 0x40>; | |
330 | ngpios = <32>; | |
331 | gpio-controller; | |
332 | #gpio-cells = <2>; | |
333 | interrupt-controller; | |
334 | #interrupt-cells = <2>; | |
335 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
336 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
337 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
338 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
339 | }; | |
340 | ||
341 | gpio1: gpio@18140 { | |
342 | compatible = "marvell,orion-gpio"; | |
343 | reg = <0x18140 0x40>; | |
344 | ngpios = <28>; | |
345 | gpio-controller; | |
346 | #gpio-cells = <2>; | |
347 | interrupt-controller; | |
348 | #interrupt-cells = <2>; | |
349 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
350 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
351 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
352 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
353 | }; | |
354 | ||
355 | system-controller@18200 { | |
356 | compatible = "marvell,armada-380-system-controller", | |
357 | "marvell,armada-370-xp-system-controller"; | |
358 | reg = <0x18200 0x100>; | |
359 | }; | |
360 | ||
361 | gateclk: clock-gating-control@18220 { | |
362 | compatible = "marvell,armada-380-gating-clock"; | |
363 | reg = <0x18220 0x4>; | |
364 | clocks = <&coreclk 0>; | |
365 | #clock-cells = <1>; | |
366 | }; | |
367 | ||
368 | coreclk: mvebu-sar@18600 { | |
369 | compatible = "marvell,armada-380-core-clock"; | |
370 | reg = <0x18600 0x04>; | |
371 | #clock-cells = <1>; | |
372 | }; | |
373 | ||
374 | mbusc: mbus-controller@20000 { | |
375 | compatible = "marvell,mbus-controller"; | |
376 | reg = <0x20000 0x100>, <0x20180 0x20>; | |
377 | }; | |
378 | ||
379 | mpic: interrupt-controller@20a00 { | |
380 | compatible = "marvell,mpic"; | |
381 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
382 | #interrupt-cells = <1>; | |
383 | #size-cells = <1>; | |
384 | interrupt-controller; | |
385 | msi-controller; | |
386 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
387 | }; | |
388 | ||
389 | timer@20300 { | |
390 | compatible = "marvell,armada-380-timer", | |
391 | "marvell,armada-xp-timer"; | |
392 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
393 | interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
394 | <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
395 | <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | |
396 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
397 | <&mpic 5>, | |
398 | <&mpic 6>; | |
399 | clocks = <&coreclk 2>, <&refclk>; | |
400 | clock-names = "nbclk", "fixed"; | |
401 | }; | |
402 | ||
403 | watchdog@20300 { | |
404 | compatible = "marvell,armada-380-wdt"; | |
405 | reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; | |
406 | clocks = <&coreclk 2>, <&refclk>; | |
407 | clock-names = "nbclk", "fixed"; | |
408 | }; | |
409 | ||
410 | cpurst@20800 { | |
411 | compatible = "marvell,armada-370-cpu-reset"; | |
412 | reg = <0x20800 0x10>; | |
413 | }; | |
414 | ||
415 | mpcore-soc-ctrl@20d20 { | |
416 | compatible = "marvell,armada-380-mpcore-soc-ctrl"; | |
417 | reg = <0x20d20 0x6c>; | |
418 | }; | |
419 | ||
420 | coherency-fabric@21010 { | |
421 | compatible = "marvell,armada-380-coherency-fabric"; | |
422 | reg = <0x21010 0x1c>; | |
423 | }; | |
424 | ||
425 | pmsu@22000 { | |
426 | compatible = "marvell,armada-380-pmsu"; | |
427 | reg = <0x22000 0x1000>; | |
428 | }; | |
429 | ||
430 | eth1: ethernet@30000 { | |
431 | compatible = "marvell,armada-370-neta"; | |
432 | reg = <0x30000 0x4000>; | |
433 | interrupts-extended = <&mpic 10>; | |
434 | clocks = <&gateclk 3>; | |
435 | status = "disabled"; | |
436 | }; | |
437 | ||
438 | eth2: ethernet@34000 { | |
439 | compatible = "marvell,armada-370-neta"; | |
440 | reg = <0x34000 0x4000>; | |
441 | interrupts-extended = <&mpic 12>; | |
442 | clocks = <&gateclk 2>; | |
443 | status = "disabled"; | |
444 | }; | |
445 | ||
446 | usb@58000 { | |
447 | compatible = "marvell,orion-ehci"; | |
448 | reg = <0x58000 0x500>; | |
449 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
450 | clocks = <&gateclk 18>; | |
451 | status = "disabled"; | |
452 | }; | |
453 | ||
454 | xor@60800 { | |
455 | compatible = "marvell,orion-xor"; | |
456 | reg = <0x60800 0x100 | |
457 | 0x60a00 0x100>; | |
458 | clocks = <&gateclk 22>; | |
459 | status = "okay"; | |
460 | ||
461 | xor00 { | |
462 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
463 | dmacap,memcpy; | |
464 | dmacap,xor; | |
465 | }; | |
466 | xor01 { | |
467 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
468 | dmacap,memcpy; | |
469 | dmacap,xor; | |
470 | dmacap,memset; | |
471 | }; | |
472 | }; | |
473 | ||
474 | xor@60900 { | |
475 | compatible = "marvell,orion-xor"; | |
476 | reg = <0x60900 0x100 | |
477 | 0x60b00 0x100>; | |
478 | clocks = <&gateclk 28>; | |
479 | status = "okay"; | |
480 | ||
481 | xor10 { | |
482 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
483 | dmacap,memcpy; | |
484 | dmacap,xor; | |
485 | }; | |
486 | xor11 { | |
487 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
488 | dmacap,memcpy; | |
489 | dmacap,xor; | |
490 | dmacap,memset; | |
491 | }; | |
492 | }; | |
493 | ||
494 | eth0: ethernet@70000 { | |
495 | compatible = "marvell,armada-370-neta"; | |
496 | reg = <0x70000 0x4000>; | |
497 | interrupts-extended = <&mpic 8>; | |
498 | clocks = <&gateclk 4>; | |
499 | status = "disabled"; | |
500 | }; | |
501 | ||
502 | mdio: mdio@72004 { | |
503 | #address-cells = <1>; | |
504 | #size-cells = <0>; | |
505 | compatible = "marvell,orion-mdio"; | |
506 | reg = <0x72004 0x4>; | |
507 | clocks = <&gateclk 4>; | |
508 | }; | |
509 | ||
510 | rtc@a3800 { | |
511 | compatible = "marvell,armada-380-rtc"; | |
512 | reg = <0xa3800 0x20>, <0x184a0 0x0c>; | |
513 | reg-names = "rtc", "rtc-soc"; | |
514 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
515 | }; | |
516 | ||
517 | sata@a8000 { | |
518 | compatible = "marvell,armada-380-ahci"; | |
519 | reg = <0xa8000 0x2000>; | |
520 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
521 | clocks = <&gateclk 15>; | |
522 | status = "disabled"; | |
523 | }; | |
524 | ||
525 | sata@e0000 { | |
526 | compatible = "marvell,armada-380-ahci"; | |
527 | reg = <0xe0000 0x2000>; | |
528 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
529 | clocks = <&gateclk 30>; | |
530 | status = "disabled"; | |
531 | }; | |
532 | ||
533 | coredivclk: clock@e4250 { | |
534 | compatible = "marvell,armada-380-corediv-clock"; | |
535 | reg = <0xe4250 0xc>; | |
536 | #clock-cells = <1>; | |
537 | clocks = <&mainpll>; | |
538 | clock-output-names = "nand"; | |
539 | }; | |
540 | ||
541 | thermal@e8078 { | |
542 | compatible = "marvell,armada380-thermal"; | |
543 | reg = <0xe4078 0x4>, <0xe4074 0x4>; | |
544 | status = "okay"; | |
545 | }; | |
546 | ||
547 | flash@d0000 { | |
548 | compatible = "marvell,armada370-nand"; | |
549 | reg = <0xd0000 0x54>; | |
550 | #address-cells = <1>; | |
551 | #size-cells = <1>; | |
552 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
553 | clocks = <&coredivclk 0>; | |
554 | status = "disabled"; | |
555 | }; | |
556 | ||
557 | sdhci@d8000 { | |
558 | compatible = "marvell,armada-380-sdhci"; | |
559 | reg-names = "sdhci", "mbus", "conf-sdio3"; | |
560 | reg = <0xd8000 0x1000>, | |
561 | <0xdc000 0x100>, | |
562 | <0x18454 0x4>; | |
563 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
564 | clocks = <&gateclk 17>; | |
565 | mrvl,clk-delay-cycles = <0x1F>; | |
566 | status = "disabled"; | |
567 | }; | |
568 | ||
569 | usb3@f0000 { | |
570 | compatible = "marvell,armada-380-xhci"; | |
571 | reg = <0xf0000 0x4000>,<0xf4000 0x4000>; | |
572 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
573 | clocks = <&gateclk 9>; | |
574 | status = "disabled"; | |
575 | }; | |
576 | ||
577 | usb3@f8000 { | |
578 | compatible = "marvell,armada-380-xhci"; | |
579 | reg = <0xf8000 0x4000>,<0xfc000 0x4000>; | |
580 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
581 | clocks = <&gateclk 10>; | |
582 | status = "disabled"; | |
583 | }; | |
584 | }; | |
585 | }; | |
586 | ||
587 | clocks { | |
588 | /* 2 GHz fixed main PLL */ | |
589 | mainpll: mainpll { | |
590 | compatible = "fixed-clock"; | |
591 | #clock-cells = <0>; | |
592 | clock-frequency = <1000000000>; | |
593 | }; | |
594 | ||
595 | /* 25 MHz reference crystal */ | |
596 | refclk: oscillator { | |
597 | compatible = "fixed-clock"; | |
598 | #clock-cells = <0>; | |
599 | clock-frequency = <25000000>; | |
600 | }; | |
601 | }; | |
602 | }; |