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57cd681b TR |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
11 | #include <dt-bindings/pinctrl/dra.h> | |
12 | ||
57cd681b TR |
13 | #define MAX_SOURCES 400 |
14 | ||
15 | / { | |
7aa1a408 LV |
16 | #address-cells = <2>; |
17 | #size-cells = <2>; | |
57cd681b TR |
18 | |
19 | compatible = "ti,dra7xx"; | |
20 | interrupt-parent = <&crossbar_mpu>; | |
4ddaa6ce | 21 | chosen { }; |
57cd681b TR |
22 | |
23 | aliases { | |
24 | i2c0 = &i2c1; | |
25 | i2c1 = &i2c2; | |
26 | i2c2 = &i2c3; | |
27 | i2c3 = &i2c4; | |
28 | i2c4 = &i2c5; | |
29 | serial0 = &uart1; | |
30 | serial1 = &uart2; | |
31 | serial2 = &uart3; | |
32 | serial3 = &uart4; | |
33 | serial4 = &uart5; | |
34 | serial5 = &uart6; | |
35 | serial6 = &uart7; | |
36 | serial7 = &uart8; | |
37 | serial8 = &uart9; | |
38 | serial9 = &uart10; | |
39 | ethernet0 = &cpsw_emac0; | |
40 | ethernet1 = &cpsw_emac1; | |
41 | d_can0 = &dcan1; | |
42 | d_can1 = &dcan2; | |
6145ef74 | 43 | spi0 = &qspi; |
57cd681b TR |
44 | }; |
45 | ||
46 | timer { | |
47 | compatible = "arm,armv7-timer"; | |
48 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
49 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
50 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
51 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
52 | interrupt-parent = <&gic>; | |
53 | }; | |
54 | ||
55 | gic: interrupt-controller@48211000 { | |
56 | compatible = "arm,cortex-a15-gic"; | |
57 | interrupt-controller; | |
58 | #interrupt-cells = <3>; | |
7aa1a408 | 59 | reg = <0x0 0x48211000 0x0 0x1000>, |
4ddaa6ce | 60 | <0x0 0x48212000 0x0 0x2000>, |
7aa1a408 LV |
61 | <0x0 0x48214000 0x0 0x2000>, |
62 | <0x0 0x48216000 0x0 0x2000>; | |
57cd681b TR |
63 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
64 | interrupt-parent = <&gic>; | |
65 | }; | |
66 | ||
67 | wakeupgen: interrupt-controller@48281000 { | |
68 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; | |
69 | interrupt-controller; | |
70 | #interrupt-cells = <3>; | |
7aa1a408 | 71 | reg = <0x0 0x48281000 0x0 0x1000>; |
57cd681b TR |
72 | interrupt-parent = <&gic>; |
73 | }; | |
74 | ||
7aa1a408 LV |
75 | cpus { |
76 | #address-cells = <1>; | |
77 | #size-cells = <0>; | |
78 | ||
79 | cpu0: cpu@0 { | |
80 | device_type = "cpu"; | |
81 | compatible = "arm,cortex-a15"; | |
82 | reg = <0>; | |
83 | ||
4ddaa6ce | 84 | operating-points-v2 = <&cpu0_opp_table>; |
7aa1a408 LV |
85 | |
86 | clocks = <&dpll_mpu_ck>; | |
87 | clock-names = "cpu"; | |
88 | ||
89 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
90 | ||
91 | /* cooling options */ | |
92 | cooling-min-level = <0>; | |
93 | cooling-max-level = <2>; | |
94 | #cooling-cells = <2>; /* min followed by max */ | |
95 | }; | |
96 | }; | |
97 | ||
4ddaa6ce LV |
98 | cpu0_opp_table: opp-table { |
99 | compatible = "operating-points-v2-ti-cpu"; | |
100 | syscon = <&scm_wkup>; | |
101 | ||
102 | opp_nom-1000000000 { | |
103 | opp-hz = /bits/ 64 <1000000000>; | |
104 | opp-microvolt = <1060000 850000 1150000>; | |
105 | opp-supported-hw = <0xFF 0x01>; | |
106 | opp-suspend; | |
107 | }; | |
108 | ||
109 | opp_od-1176000000 { | |
110 | opp-hz = /bits/ 64 <1176000000>; | |
111 | opp-microvolt = <1160000 885000 1160000>; | |
112 | opp-supported-hw = <0xFF 0x02>; | |
113 | }; | |
114 | }; | |
115 | ||
57cd681b TR |
116 | /* |
117 | * The soc node represents the soc top level view. It is used for IPs | |
118 | * that are not memory mapped in the MPU view or for the MPU itself. | |
119 | */ | |
120 | soc { | |
121 | compatible = "ti,omap-infra"; | |
122 | mpu { | |
123 | compatible = "ti,omap5-mpu"; | |
124 | ti,hwmods = "mpu"; | |
125 | }; | |
126 | }; | |
127 | ||
128 | /* | |
129 | * XXX: Use a flat representation of the SOC interconnect. | |
130 | * The real OMAP interconnect network is quite complex. | |
131 | * Since it will not bring real advantage to represent that in DT for | |
132 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
133 | * hierarchy. | |
134 | */ | |
135 | ocp { | |
136 | compatible = "ti,dra7-l3-noc", "simple-bus"; | |
137 | #address-cells = <1>; | |
138 | #size-cells = <1>; | |
7aa1a408 | 139 | ranges = <0x0 0x0 0x0 0xc0000000>; |
57cd681b | 140 | ti,hwmods = "l3_main_1", "l3_main_2"; |
7aa1a408 LV |
141 | reg = <0x0 0x44000000 0x0 0x1000000>, |
142 | <0x0 0x45000000 0x0 0x1000>; | |
57cd681b TR |
143 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
144 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
145 | ||
146 | l4_cfg: l4@4a000000 { | |
147 | compatible = "ti,dra7-l4-cfg", "simple-bus"; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <1>; | |
150 | ranges = <0 0x4a000000 0x22c000>; | |
151 | ||
152 | scm: scm@2000 { | |
153 | compatible = "ti,dra7-scm-core", "simple-bus"; | |
154 | reg = <0x2000 0x2000>; | |
155 | #address-cells = <1>; | |
156 | #size-cells = <1>; | |
157 | ranges = <0 0x2000 0x2000>; | |
158 | ||
159 | scm_conf: scm_conf@0 { | |
7aa1a408 | 160 | compatible = "syscon", "simple-bus"; |
57cd681b TR |
161 | reg = <0x0 0x1400>; |
162 | #address-cells = <1>; | |
163 | #size-cells = <1>; | |
7aa1a408 | 164 | ranges = <0 0x0 0x1400>; |
57cd681b | 165 | |
7aa1a408 LV |
166 | pbias_regulator: pbias_regulator@e00 { |
167 | compatible = "ti,pbias-dra7", "ti,pbias-omap"; | |
57cd681b TR |
168 | reg = <0xe00 0x4>; |
169 | syscon = <&scm_conf>; | |
170 | pbias_mmc_reg: pbias_mmc_omap5 { | |
171 | regulator-name = "pbias_mmc_omap5"; | |
172 | regulator-min-microvolt = <1800000>; | |
173 | regulator-max-microvolt = <3000000>; | |
174 | }; | |
175 | }; | |
176 | ||
177 | scm_conf_clocks: clocks { | |
178 | #address-cells = <1>; | |
179 | #size-cells = <0>; | |
180 | }; | |
181 | }; | |
182 | ||
183 | dra7_pmx_core: pinmux@1400 { | |
184 | compatible = "ti,dra7-padconf", | |
185 | "pinctrl-single"; | |
7aa1a408 | 186 | reg = <0x1400 0x0468>; |
57cd681b TR |
187 | #address-cells = <1>; |
188 | #size-cells = <0>; | |
4ddaa6ce | 189 | #pinctrl-cells = <1>; |
57cd681b TR |
190 | #interrupt-cells = <1>; |
191 | interrupt-controller; | |
192 | pinctrl-single,register-width = <32>; | |
193 | pinctrl-single,function-mask = <0x3fffffff>; | |
194 | }; | |
7aa1a408 LV |
195 | |
196 | scm_conf1: scm_conf@1c04 { | |
197 | compatible = "syscon"; | |
198 | reg = <0x1c04 0x0020>; | |
4ddaa6ce | 199 | #syscon-cells = <2>; |
7aa1a408 LV |
200 | }; |
201 | ||
202 | scm_conf_pcie: scm_conf@1c24 { | |
203 | compatible = "syscon"; | |
204 | reg = <0x1c24 0x0024>; | |
205 | }; | |
206 | ||
207 | sdma_xbar: dma-router@b78 { | |
208 | compatible = "ti,dra7-dma-crossbar"; | |
209 | reg = <0xb78 0xfc>; | |
210 | #dma-cells = <1>; | |
211 | dma-requests = <205>; | |
212 | ti,dma-safe-map = <0>; | |
213 | dma-masters = <&sdma>; | |
214 | }; | |
215 | ||
216 | edma_xbar: dma-router@c78 { | |
217 | compatible = "ti,dra7-dma-crossbar"; | |
218 | reg = <0xc78 0x7c>; | |
219 | #dma-cells = <2>; | |
220 | dma-requests = <204>; | |
221 | ti,dma-safe-map = <0>; | |
222 | dma-masters = <&edma>; | |
223 | }; | |
57cd681b TR |
224 | }; |
225 | ||
226 | cm_core_aon: cm_core_aon@5000 { | |
227 | compatible = "ti,dra7-cm-core-aon"; | |
228 | reg = <0x5000 0x2000>; | |
229 | ||
230 | cm_core_aon_clocks: clocks { | |
231 | #address-cells = <1>; | |
232 | #size-cells = <0>; | |
233 | }; | |
234 | ||
235 | cm_core_aon_clockdomains: clockdomains { | |
236 | }; | |
237 | }; | |
238 | ||
239 | cm_core: cm_core@8000 { | |
240 | compatible = "ti,dra7-cm-core"; | |
241 | reg = <0x8000 0x3000>; | |
242 | ||
243 | cm_core_clocks: clocks { | |
244 | #address-cells = <1>; | |
245 | #size-cells = <0>; | |
246 | }; | |
247 | ||
248 | cm_core_clockdomains: clockdomains { | |
249 | }; | |
250 | }; | |
251 | }; | |
252 | ||
253 | l4_wkup: l4@4ae00000 { | |
254 | compatible = "ti,dra7-l4-wkup", "simple-bus"; | |
255 | #address-cells = <1>; | |
256 | #size-cells = <1>; | |
257 | ranges = <0 0x4ae00000 0x3f000>; | |
258 | ||
259 | counter32k: counter@4000 { | |
260 | compatible = "ti,omap-counter32k"; | |
261 | reg = <0x4000 0x40>; | |
262 | ti,hwmods = "counter_32k"; | |
263 | }; | |
264 | ||
265 | prm: prm@6000 { | |
266 | compatible = "ti,dra7-prm"; | |
267 | reg = <0x6000 0x3000>; | |
268 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
269 | ||
270 | prm_clocks: clocks { | |
271 | #address-cells = <1>; | |
272 | #size-cells = <0>; | |
273 | }; | |
274 | ||
275 | prm_clockdomains: clockdomains { | |
276 | }; | |
277 | }; | |
7aa1a408 LV |
278 | |
279 | scm_wkup: scm_conf@c000 { | |
280 | compatible = "syscon"; | |
281 | reg = <0xc000 0x1000>; | |
282 | }; | |
57cd681b TR |
283 | }; |
284 | ||
285 | axi@0 { | |
286 | compatible = "simple-bus"; | |
287 | #size-cells = <1>; | |
288 | #address-cells = <1>; | |
289 | ranges = <0x51000000 0x51000000 0x3000 | |
290 | 0x0 0x20000000 0x10000000>; | |
4ddaa6ce LV |
291 | /** |
292 | * To enable PCI endpoint mode, disable the pcie1_rc | |
293 | * node and enable pcie1_ep mode. | |
294 | */ | |
295 | pcie1_rc: pcie@51000000 { | |
57cd681b TR |
296 | compatible = "ti,dra7-pcie"; |
297 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; | |
298 | reg-names = "rc_dbics", "ti_conf", "config"; | |
299 | interrupts = <0 232 0x4>, <0 233 0x4>; | |
300 | #address-cells = <3>; | |
301 | #size-cells = <2>; | |
302 | device_type = "pci"; | |
303 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
304 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; | |
4ddaa6ce | 305 | bus-range = <0x00 0xff>; |
57cd681b TR |
306 | #interrupt-cells = <1>; |
307 | num-lanes = <1>; | |
7aa1a408 | 308 | linux,pci-domain = <0>; |
57cd681b TR |
309 | ti,hwmods = "pcie1"; |
310 | phys = <&pcie1_phy>; | |
311 | phy-names = "pcie-phy0"; | |
312 | interrupt-map-mask = <0 0 0 7>; | |
313 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, | |
314 | <0 0 0 2 &pcie1_intc 2>, | |
315 | <0 0 0 3 &pcie1_intc 3>, | |
316 | <0 0 0 4 &pcie1_intc 4>; | |
4ddaa6ce | 317 | status = "disabled"; |
57cd681b TR |
318 | pcie1_intc: interrupt-controller { |
319 | interrupt-controller; | |
320 | #address-cells = <0>; | |
321 | #interrupt-cells = <1>; | |
322 | }; | |
323 | }; | |
4ddaa6ce LV |
324 | |
325 | pcie1_ep: pcie_ep@51000000 { | |
326 | compatible = "ti,dra7-pcie-ep"; | |
327 | reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; | |
328 | reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; | |
329 | interrupts = <0 232 0x4>; | |
330 | num-lanes = <1>; | |
331 | num-ib-windows = <4>; | |
332 | num-ob-windows = <16>; | |
333 | ti,hwmods = "pcie1"; | |
334 | phys = <&pcie1_phy>; | |
335 | phy-names = "pcie-phy0"; | |
336 | ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; | |
337 | status = "disabled"; | |
338 | }; | |
57cd681b TR |
339 | }; |
340 | ||
341 | axi@1 { | |
342 | compatible = "simple-bus"; | |
343 | #size-cells = <1>; | |
344 | #address-cells = <1>; | |
345 | ranges = <0x51800000 0x51800000 0x3000 | |
346 | 0x0 0x30000000 0x10000000>; | |
347 | status = "disabled"; | |
7aa1a408 | 348 | pcie@51800000 { |
57cd681b TR |
349 | compatible = "ti,dra7-pcie"; |
350 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; | |
351 | reg-names = "rc_dbics", "ti_conf", "config"; | |
352 | interrupts = <0 355 0x4>, <0 356 0x4>; | |
353 | #address-cells = <3>; | |
354 | #size-cells = <2>; | |
355 | device_type = "pci"; | |
356 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
357 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; | |
4ddaa6ce | 358 | bus-range = <0x00 0xff>; |
57cd681b TR |
359 | #interrupt-cells = <1>; |
360 | num-lanes = <1>; | |
7aa1a408 | 361 | linux,pci-domain = <1>; |
57cd681b TR |
362 | ti,hwmods = "pcie2"; |
363 | phys = <&pcie2_phy>; | |
364 | phy-names = "pcie-phy0"; | |
365 | interrupt-map-mask = <0 0 0 7>; | |
366 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, | |
367 | <0 0 0 2 &pcie2_intc 2>, | |
368 | <0 0 0 3 &pcie2_intc 3>, | |
369 | <0 0 0 4 &pcie2_intc 4>; | |
370 | pcie2_intc: interrupt-controller { | |
371 | interrupt-controller; | |
372 | #address-cells = <0>; | |
373 | #interrupt-cells = <1>; | |
374 | }; | |
375 | }; | |
376 | }; | |
377 | ||
7aa1a408 LV |
378 | ocmcram1: ocmcram@40300000 { |
379 | compatible = "mmio-sram"; | |
380 | reg = <0x40300000 0x80000>; | |
381 | ranges = <0x0 0x40300000 0x80000>; | |
382 | #address-cells = <1>; | |
383 | #size-cells = <1>; | |
384 | /* | |
385 | * This is a placeholder for an optional reserved | |
386 | * region for use by secure software. The size | |
387 | * of this region is not known until runtime so it | |
388 | * is set as zero to either be updated to reserve | |
389 | * space or left unchanged to leave all SRAM for use. | |
390 | * On HS parts that that require the reserved region | |
391 | * either the bootloader can update the size to | |
392 | * the required amount or the node can be overridden | |
393 | * from the board dts file for the secure platform. | |
394 | */ | |
395 | sram-hs@0 { | |
396 | compatible = "ti,secure-ram"; | |
397 | reg = <0x0 0x0>; | |
398 | }; | |
399 | }; | |
400 | ||
401 | /* | |
402 | * NOTE: ocmcram2 and ocmcram3 are not available on all | |
403 | * DRA7xx and AM57xx variants. Confirm availability in | |
404 | * the data manual for the exact part number in use | |
405 | * before enabling these nodes in the board dts file. | |
406 | */ | |
407 | ocmcram2: ocmcram@40400000 { | |
408 | status = "disabled"; | |
409 | compatible = "mmio-sram"; | |
410 | reg = <0x40400000 0x100000>; | |
411 | ranges = <0x0 0x40400000 0x100000>; | |
412 | #address-cells = <1>; | |
413 | #size-cells = <1>; | |
414 | }; | |
415 | ||
416 | ocmcram3: ocmcram@40500000 { | |
417 | status = "disabled"; | |
418 | compatible = "mmio-sram"; | |
419 | reg = <0x40500000 0x100000>; | |
420 | ranges = <0x0 0x40500000 0x100000>; | |
421 | #address-cells = <1>; | |
422 | #size-cells = <1>; | |
423 | }; | |
424 | ||
57cd681b TR |
425 | bandgap: bandgap@4a0021e0 { |
426 | reg = <0x4a0021e0 0xc | |
427 | 0x4a00232c 0xc | |
428 | 0x4a002380 0x2c | |
429 | 0x4a0023C0 0x3c | |
430 | 0x4a002564 0x8 | |
431 | 0x4a002574 0x50>; | |
432 | compatible = "ti,dra752-bandgap"; | |
433 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
434 | #thermal-sensor-cells = <1>; | |
435 | }; | |
436 | ||
7aa1a408 | 437 | dsp1_system: dsp_system@40d00000 { |
57cd681b | 438 | compatible = "syscon"; |
7aa1a408 | 439 | reg = <0x40d00000 0x100>; |
57cd681b TR |
440 | }; |
441 | ||
4ddaa6ce LV |
442 | dra7_iodelay_core: padconf@4844a000 { |
443 | compatible = "ti,dra7-iodelay"; | |
444 | reg = <0x4844a000 0x0d1c>; | |
445 | #address-cells = <1>; | |
446 | #size-cells = <0>; | |
447 | #pinctrl-cells = <2>; | |
448 | }; | |
449 | ||
57cd681b TR |
450 | sdma: dma-controller@4a056000 { |
451 | compatible = "ti,omap4430-sdma"; | |
452 | reg = <0x4a056000 0x1000>; | |
453 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
454 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
455 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
456 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
457 | #dma-cells = <1>; | |
458 | dma-channels = <32>; | |
459 | dma-requests = <127>; | |
460 | }; | |
461 | ||
7aa1a408 LV |
462 | edma: edma@43300000 { |
463 | compatible = "ti,edma3-tpcc"; | |
464 | ti,hwmods = "tpcc"; | |
465 | reg = <0x43300000 0x100000>; | |
466 | reg-names = "edma3_cc"; | |
467 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, | |
468 | <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, | |
469 | <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
470 | interrupt-names = "edma3_ccint", "edma3_mperr", | |
471 | "edma3_ccerrint"; | |
472 | dma-requests = <64>; | |
473 | #dma-cells = <2>; | |
474 | ||
475 | ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; | |
476 | ||
477 | /* | |
478 | * memcpy is disabled, can be enabled with: | |
479 | * ti,edma-memcpy-channels = <20 21>; | |
480 | * for example. Note that these channels need to be | |
481 | * masked in the xbar as well. | |
482 | */ | |
483 | }; | |
484 | ||
485 | edma_tptc0: tptc@43400000 { | |
486 | compatible = "ti,edma3-tptc"; | |
487 | ti,hwmods = "tptc0"; | |
488 | reg = <0x43400000 0x100000>; | |
489 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
490 | interrupt-names = "edma3_tcerrint"; | |
491 | }; | |
492 | ||
493 | edma_tptc1: tptc@43500000 { | |
494 | compatible = "ti,edma3-tptc"; | |
495 | ti,hwmods = "tptc1"; | |
496 | reg = <0x43500000 0x100000>; | |
497 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
498 | interrupt-names = "edma3_tcerrint"; | |
499 | }; | |
500 | ||
57cd681b TR |
501 | gpio1: gpio@4ae10000 { |
502 | compatible = "ti,omap4-gpio"; | |
503 | reg = <0x4ae10000 0x200>; | |
504 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
505 | ti,hwmods = "gpio1"; | |
506 | gpio-controller; | |
507 | #gpio-cells = <2>; | |
508 | interrupt-controller; | |
509 | #interrupt-cells = <2>; | |
510 | }; | |
511 | ||
512 | gpio2: gpio@48055000 { | |
513 | compatible = "ti,omap4-gpio"; | |
514 | reg = <0x48055000 0x200>; | |
515 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
516 | ti,hwmods = "gpio2"; | |
517 | gpio-controller; | |
518 | #gpio-cells = <2>; | |
519 | interrupt-controller; | |
520 | #interrupt-cells = <2>; | |
521 | }; | |
522 | ||
523 | gpio3: gpio@48057000 { | |
524 | compatible = "ti,omap4-gpio"; | |
525 | reg = <0x48057000 0x200>; | |
526 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
527 | ti,hwmods = "gpio3"; | |
528 | gpio-controller; | |
529 | #gpio-cells = <2>; | |
530 | interrupt-controller; | |
531 | #interrupt-cells = <2>; | |
532 | }; | |
533 | ||
534 | gpio4: gpio@48059000 { | |
535 | compatible = "ti,omap4-gpio"; | |
536 | reg = <0x48059000 0x200>; | |
537 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
538 | ti,hwmods = "gpio4"; | |
539 | gpio-controller; | |
540 | #gpio-cells = <2>; | |
541 | interrupt-controller; | |
542 | #interrupt-cells = <2>; | |
543 | }; | |
544 | ||
545 | gpio5: gpio@4805b000 { | |
546 | compatible = "ti,omap4-gpio"; | |
547 | reg = <0x4805b000 0x200>; | |
548 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
549 | ti,hwmods = "gpio5"; | |
550 | gpio-controller; | |
551 | #gpio-cells = <2>; | |
552 | interrupt-controller; | |
553 | #interrupt-cells = <2>; | |
554 | }; | |
555 | ||
556 | gpio6: gpio@4805d000 { | |
557 | compatible = "ti,omap4-gpio"; | |
558 | reg = <0x4805d000 0x200>; | |
559 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
560 | ti,hwmods = "gpio6"; | |
561 | gpio-controller; | |
562 | #gpio-cells = <2>; | |
563 | interrupt-controller; | |
564 | #interrupt-cells = <2>; | |
565 | }; | |
566 | ||
567 | gpio7: gpio@48051000 { | |
568 | compatible = "ti,omap4-gpio"; | |
569 | reg = <0x48051000 0x200>; | |
570 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
571 | ti,hwmods = "gpio7"; | |
572 | gpio-controller; | |
573 | #gpio-cells = <2>; | |
574 | interrupt-controller; | |
575 | #interrupt-cells = <2>; | |
576 | }; | |
577 | ||
578 | gpio8: gpio@48053000 { | |
579 | compatible = "ti,omap4-gpio"; | |
580 | reg = <0x48053000 0x200>; | |
581 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
582 | ti,hwmods = "gpio8"; | |
583 | gpio-controller; | |
584 | #gpio-cells = <2>; | |
585 | interrupt-controller; | |
586 | #interrupt-cells = <2>; | |
587 | }; | |
588 | ||
589 | uart1: serial@4806a000 { | |
7aa1a408 | 590 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
591 | reg = <0x4806a000 0x100>; |
592 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
593 | ti,hwmods = "uart1"; | |
594 | clock-frequency = <48000000>; | |
595 | status = "disabled"; | |
7aa1a408 | 596 | dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; |
57cd681b TR |
597 | dma-names = "tx", "rx"; |
598 | }; | |
599 | ||
600 | uart2: serial@4806c000 { | |
7aa1a408 | 601 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
602 | reg = <0x4806c000 0x100>; |
603 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
604 | ti,hwmods = "uart2"; | |
605 | clock-frequency = <48000000>; | |
606 | status = "disabled"; | |
7aa1a408 | 607 | dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; |
57cd681b TR |
608 | dma-names = "tx", "rx"; |
609 | }; | |
610 | ||
611 | uart3: serial@48020000 { | |
7aa1a408 | 612 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
613 | reg = <0x48020000 0x100>; |
614 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
615 | ti,hwmods = "uart3"; | |
616 | clock-frequency = <48000000>; | |
617 | status = "disabled"; | |
7aa1a408 | 618 | dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; |
57cd681b TR |
619 | dma-names = "tx", "rx"; |
620 | }; | |
621 | ||
622 | uart4: serial@4806e000 { | |
7aa1a408 | 623 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
624 | reg = <0x4806e000 0x100>; |
625 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
626 | ti,hwmods = "uart4"; | |
627 | clock-frequency = <48000000>; | |
628 | status = "disabled"; | |
7aa1a408 | 629 | dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; |
57cd681b TR |
630 | dma-names = "tx", "rx"; |
631 | }; | |
632 | ||
633 | uart5: serial@48066000 { | |
7aa1a408 | 634 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
635 | reg = <0x48066000 0x100>; |
636 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
637 | ti,hwmods = "uart5"; | |
638 | clock-frequency = <48000000>; | |
639 | status = "disabled"; | |
7aa1a408 | 640 | dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; |
57cd681b TR |
641 | dma-names = "tx", "rx"; |
642 | }; | |
643 | ||
644 | uart6: serial@48068000 { | |
7aa1a408 | 645 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
646 | reg = <0x48068000 0x100>; |
647 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
648 | ti,hwmods = "uart6"; | |
649 | clock-frequency = <48000000>; | |
650 | status = "disabled"; | |
7aa1a408 | 651 | dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; |
57cd681b TR |
652 | dma-names = "tx", "rx"; |
653 | }; | |
654 | ||
655 | uart7: serial@48420000 { | |
7aa1a408 | 656 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
657 | reg = <0x48420000 0x100>; |
658 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; | |
659 | ti,hwmods = "uart7"; | |
660 | clock-frequency = <48000000>; | |
661 | status = "disabled"; | |
662 | }; | |
663 | ||
664 | uart8: serial@48422000 { | |
7aa1a408 | 665 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
666 | reg = <0x48422000 0x100>; |
667 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; | |
668 | ti,hwmods = "uart8"; | |
669 | clock-frequency = <48000000>; | |
670 | status = "disabled"; | |
671 | }; | |
672 | ||
673 | uart9: serial@48424000 { | |
7aa1a408 | 674 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
675 | reg = <0x48424000 0x100>; |
676 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; | |
677 | ti,hwmods = "uart9"; | |
678 | clock-frequency = <48000000>; | |
679 | status = "disabled"; | |
680 | }; | |
681 | ||
682 | uart10: serial@4ae2b000 { | |
7aa1a408 | 683 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
57cd681b TR |
684 | reg = <0x4ae2b000 0x100>; |
685 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
686 | ti,hwmods = "uart10"; | |
687 | clock-frequency = <48000000>; | |
688 | status = "disabled"; | |
689 | }; | |
690 | ||
691 | mailbox1: mailbox@4a0f4000 { | |
692 | compatible = "ti,omap4-mailbox"; | |
693 | reg = <0x4a0f4000 0x200>; | |
694 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, | |
695 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
696 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
697 | ti,hwmods = "mailbox1"; | |
698 | #mbox-cells = <1>; | |
699 | ti,mbox-num-users = <3>; | |
700 | ti,mbox-num-fifos = <8>; | |
701 | status = "disabled"; | |
702 | }; | |
703 | ||
704 | mailbox2: mailbox@4883a000 { | |
705 | compatible = "ti,omap4-mailbox"; | |
706 | reg = <0x4883a000 0x200>; | |
707 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, | |
708 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
709 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
710 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
711 | ti,hwmods = "mailbox2"; | |
712 | #mbox-cells = <1>; | |
713 | ti,mbox-num-users = <4>; | |
714 | ti,mbox-num-fifos = <12>; | |
715 | status = "disabled"; | |
716 | }; | |
717 | ||
718 | mailbox3: mailbox@4883c000 { | |
719 | compatible = "ti,omap4-mailbox"; | |
720 | reg = <0x4883c000 0x200>; | |
721 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, | |
722 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
723 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
724 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; | |
725 | ti,hwmods = "mailbox3"; | |
726 | #mbox-cells = <1>; | |
727 | ti,mbox-num-users = <4>; | |
728 | ti,mbox-num-fifos = <12>; | |
729 | status = "disabled"; | |
730 | }; | |
731 | ||
732 | mailbox4: mailbox@4883e000 { | |
733 | compatible = "ti,omap4-mailbox"; | |
734 | reg = <0x4883e000 0x200>; | |
735 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
736 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
737 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
738 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | |
739 | ti,hwmods = "mailbox4"; | |
740 | #mbox-cells = <1>; | |
741 | ti,mbox-num-users = <4>; | |
742 | ti,mbox-num-fifos = <12>; | |
743 | status = "disabled"; | |
744 | }; | |
745 | ||
746 | mailbox5: mailbox@48840000 { | |
747 | compatible = "ti,omap4-mailbox"; | |
748 | reg = <0x48840000 0x200>; | |
749 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | |
750 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
751 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
752 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
753 | ti,hwmods = "mailbox5"; | |
754 | #mbox-cells = <1>; | |
755 | ti,mbox-num-users = <4>; | |
756 | ti,mbox-num-fifos = <12>; | |
757 | status = "disabled"; | |
758 | }; | |
759 | ||
760 | mailbox6: mailbox@48842000 { | |
761 | compatible = "ti,omap4-mailbox"; | |
762 | reg = <0x48842000 0x200>; | |
763 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | |
764 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
765 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
766 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
767 | ti,hwmods = "mailbox6"; | |
768 | #mbox-cells = <1>; | |
769 | ti,mbox-num-users = <4>; | |
770 | ti,mbox-num-fifos = <12>; | |
771 | status = "disabled"; | |
772 | }; | |
773 | ||
774 | mailbox7: mailbox@48844000 { | |
775 | compatible = "ti,omap4-mailbox"; | |
776 | reg = <0x48844000 0x200>; | |
777 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, | |
778 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
779 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
780 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; | |
781 | ti,hwmods = "mailbox7"; | |
782 | #mbox-cells = <1>; | |
783 | ti,mbox-num-users = <4>; | |
784 | ti,mbox-num-fifos = <12>; | |
785 | status = "disabled"; | |
786 | }; | |
787 | ||
788 | mailbox8: mailbox@48846000 { | |
789 | compatible = "ti,omap4-mailbox"; | |
790 | reg = <0x48846000 0x200>; | |
791 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, | |
792 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, | |
793 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, | |
794 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; | |
795 | ti,hwmods = "mailbox8"; | |
796 | #mbox-cells = <1>; | |
797 | ti,mbox-num-users = <4>; | |
798 | ti,mbox-num-fifos = <12>; | |
799 | status = "disabled"; | |
800 | }; | |
801 | ||
802 | mailbox9: mailbox@4885e000 { | |
803 | compatible = "ti,omap4-mailbox"; | |
804 | reg = <0x4885e000 0x200>; | |
805 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, | |
806 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, | |
807 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, | |
808 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
809 | ti,hwmods = "mailbox9"; | |
810 | #mbox-cells = <1>; | |
811 | ti,mbox-num-users = <4>; | |
812 | ti,mbox-num-fifos = <12>; | |
813 | status = "disabled"; | |
814 | }; | |
815 | ||
816 | mailbox10: mailbox@48860000 { | |
817 | compatible = "ti,omap4-mailbox"; | |
818 | reg = <0x48860000 0x200>; | |
819 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, | |
820 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, | |
821 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, | |
822 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
823 | ti,hwmods = "mailbox10"; | |
824 | #mbox-cells = <1>; | |
825 | ti,mbox-num-users = <4>; | |
826 | ti,mbox-num-fifos = <12>; | |
827 | status = "disabled"; | |
828 | }; | |
829 | ||
830 | mailbox11: mailbox@48862000 { | |
831 | compatible = "ti,omap4-mailbox"; | |
832 | reg = <0x48862000 0x200>; | |
833 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, | |
834 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, | |
835 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, | |
836 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; | |
837 | ti,hwmods = "mailbox11"; | |
838 | #mbox-cells = <1>; | |
839 | ti,mbox-num-users = <4>; | |
840 | ti,mbox-num-fifos = <12>; | |
841 | status = "disabled"; | |
842 | }; | |
843 | ||
844 | mailbox12: mailbox@48864000 { | |
845 | compatible = "ti,omap4-mailbox"; | |
846 | reg = <0x48864000 0x200>; | |
847 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, | |
848 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, | |
849 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
850 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; | |
851 | ti,hwmods = "mailbox12"; | |
852 | #mbox-cells = <1>; | |
853 | ti,mbox-num-users = <4>; | |
854 | ti,mbox-num-fifos = <12>; | |
855 | status = "disabled"; | |
856 | }; | |
857 | ||
858 | mailbox13: mailbox@48802000 { | |
859 | compatible = "ti,omap4-mailbox"; | |
860 | reg = <0x48802000 0x200>; | |
861 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, | |
862 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, | |
863 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, | |
864 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; | |
865 | ti,hwmods = "mailbox13"; | |
866 | #mbox-cells = <1>; | |
867 | ti,mbox-num-users = <4>; | |
868 | ti,mbox-num-fifos = <12>; | |
869 | status = "disabled"; | |
870 | }; | |
871 | ||
872 | timer1: timer@4ae18000 { | |
873 | compatible = "ti,omap5430-timer"; | |
874 | reg = <0x4ae18000 0x80>; | |
875 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
876 | ti,hwmods = "timer1"; | |
877 | ti,timer-alwon; | |
878 | }; | |
879 | ||
880 | timer2: timer@48032000 { | |
881 | compatible = "ti,omap5430-timer"; | |
882 | reg = <0x48032000 0x80>; | |
883 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
884 | ti,hwmods = "timer2"; | |
885 | }; | |
886 | ||
887 | timer3: timer@48034000 { | |
888 | compatible = "ti,omap5430-timer"; | |
889 | reg = <0x48034000 0x80>; | |
890 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
891 | ti,hwmods = "timer3"; | |
892 | }; | |
893 | ||
894 | timer4: timer@48036000 { | |
895 | compatible = "ti,omap5430-timer"; | |
896 | reg = <0x48036000 0x80>; | |
897 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
898 | ti,hwmods = "timer4"; | |
899 | }; | |
900 | ||
901 | timer5: timer@48820000 { | |
902 | compatible = "ti,omap5430-timer"; | |
903 | reg = <0x48820000 0x80>; | |
904 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
905 | ti,hwmods = "timer5"; | |
906 | }; | |
907 | ||
908 | timer6: timer@48822000 { | |
909 | compatible = "ti,omap5430-timer"; | |
910 | reg = <0x48822000 0x80>; | |
911 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
912 | ti,hwmods = "timer6"; | |
913 | }; | |
914 | ||
915 | timer7: timer@48824000 { | |
916 | compatible = "ti,omap5430-timer"; | |
917 | reg = <0x48824000 0x80>; | |
918 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
919 | ti,hwmods = "timer7"; | |
920 | }; | |
921 | ||
922 | timer8: timer@48826000 { | |
923 | compatible = "ti,omap5430-timer"; | |
924 | reg = <0x48826000 0x80>; | |
925 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
926 | ti,hwmods = "timer8"; | |
927 | }; | |
928 | ||
929 | timer9: timer@4803e000 { | |
930 | compatible = "ti,omap5430-timer"; | |
931 | reg = <0x4803e000 0x80>; | |
932 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
933 | ti,hwmods = "timer9"; | |
934 | }; | |
935 | ||
936 | timer10: timer@48086000 { | |
937 | compatible = "ti,omap5430-timer"; | |
938 | reg = <0x48086000 0x80>; | |
939 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
940 | ti,hwmods = "timer10"; | |
941 | }; | |
942 | ||
943 | timer11: timer@48088000 { | |
944 | compatible = "ti,omap5430-timer"; | |
945 | reg = <0x48088000 0x80>; | |
946 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
947 | ti,hwmods = "timer11"; | |
948 | }; | |
949 | ||
7aa1a408 LV |
950 | timer12: timer@4ae20000 { |
951 | compatible = "ti,omap5430-timer"; | |
952 | reg = <0x4ae20000 0x80>; | |
953 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
954 | ti,hwmods = "timer12"; | |
955 | ti,timer-alwon; | |
956 | ti,timer-secure; | |
957 | }; | |
958 | ||
57cd681b TR |
959 | timer13: timer@48828000 { |
960 | compatible = "ti,omap5430-timer"; | |
961 | reg = <0x48828000 0x80>; | |
962 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; | |
963 | ti,hwmods = "timer13"; | |
57cd681b TR |
964 | }; |
965 | ||
966 | timer14: timer@4882a000 { | |
967 | compatible = "ti,omap5430-timer"; | |
968 | reg = <0x4882a000 0x80>; | |
969 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; | |
970 | ti,hwmods = "timer14"; | |
57cd681b TR |
971 | }; |
972 | ||
973 | timer15: timer@4882c000 { | |
974 | compatible = "ti,omap5430-timer"; | |
975 | reg = <0x4882c000 0x80>; | |
976 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; | |
977 | ti,hwmods = "timer15"; | |
57cd681b TR |
978 | }; |
979 | ||
980 | timer16: timer@4882e000 { | |
981 | compatible = "ti,omap5430-timer"; | |
982 | reg = <0x4882e000 0x80>; | |
983 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; | |
984 | ti,hwmods = "timer16"; | |
57cd681b TR |
985 | }; |
986 | ||
987 | wdt2: wdt@4ae14000 { | |
988 | compatible = "ti,omap3-wdt"; | |
989 | reg = <0x4ae14000 0x80>; | |
990 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
991 | ti,hwmods = "wd_timer2"; | |
992 | }; | |
993 | ||
994 | hwspinlock: spinlock@4a0f6000 { | |
995 | compatible = "ti,omap4-hwspinlock"; | |
996 | reg = <0x4a0f6000 0x1000>; | |
997 | ti,hwmods = "spinlock"; | |
998 | #hwlock-cells = <1>; | |
999 | }; | |
1000 | ||
1001 | dmm@4e000000 { | |
1002 | compatible = "ti,omap5-dmm"; | |
1003 | reg = <0x4e000000 0x800>; | |
1004 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
1005 | ti,hwmods = "dmm"; | |
1006 | }; | |
1007 | ||
1008 | i2c1: i2c@48070000 { | |
1009 | compatible = "ti,omap4-i2c"; | |
1010 | reg = <0x48070000 0x100>; | |
1011 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
1012 | #address-cells = <1>; | |
1013 | #size-cells = <0>; | |
1014 | ti,hwmods = "i2c1"; | |
1015 | status = "disabled"; | |
1016 | }; | |
1017 | ||
1018 | i2c2: i2c@48072000 { | |
1019 | compatible = "ti,omap4-i2c"; | |
1020 | reg = <0x48072000 0x100>; | |
1021 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
1022 | #address-cells = <1>; | |
1023 | #size-cells = <0>; | |
1024 | ti,hwmods = "i2c2"; | |
1025 | status = "disabled"; | |
1026 | }; | |
1027 | ||
1028 | i2c3: i2c@48060000 { | |
1029 | compatible = "ti,omap4-i2c"; | |
1030 | reg = <0x48060000 0x100>; | |
1031 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
1032 | #address-cells = <1>; | |
1033 | #size-cells = <0>; | |
1034 | ti,hwmods = "i2c3"; | |
1035 | status = "disabled"; | |
1036 | }; | |
1037 | ||
1038 | i2c4: i2c@4807a000 { | |
1039 | compatible = "ti,omap4-i2c"; | |
1040 | reg = <0x4807a000 0x100>; | |
1041 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
1042 | #address-cells = <1>; | |
1043 | #size-cells = <0>; | |
1044 | ti,hwmods = "i2c4"; | |
1045 | status = "disabled"; | |
1046 | }; | |
1047 | ||
1048 | i2c5: i2c@4807c000 { | |
1049 | compatible = "ti,omap4-i2c"; | |
1050 | reg = <0x4807c000 0x100>; | |
1051 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
1052 | #address-cells = <1>; | |
1053 | #size-cells = <0>; | |
1054 | ti,hwmods = "i2c5"; | |
1055 | status = "disabled"; | |
1056 | }; | |
1057 | ||
1058 | mmc1: mmc@4809c000 { | |
6ba41e5d | 1059 | compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; |
57cd681b TR |
1060 | reg = <0x4809c000 0x400>; |
1061 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
1062 | ti,hwmods = "mmc1"; | |
1063 | ti,dual-volt; | |
1064 | ti,needs-special-reset; | |
7aa1a408 | 1065 | dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; |
57cd681b TR |
1066 | dma-names = "tx", "rx"; |
1067 | status = "disabled"; | |
1068 | pbias-supply = <&pbias_mmc_reg>; | |
4ddaa6ce | 1069 | max-frequency = <192000000>; |
2adee41d JJH |
1070 | sd-uhs-sdr104; |
1071 | sd-uhs-sdr50; | |
1072 | sd-uhs-ddr50; | |
1073 | sd-uhs-sdr25; | |
1074 | sd-uhs-sdr12; | |
57cd681b TR |
1075 | }; |
1076 | ||
1077 | mmc2: mmc@480b4000 { | |
6ba41e5d | 1078 | compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; |
57cd681b TR |
1079 | reg = <0x480b4000 0x400>; |
1080 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
1081 | ti,hwmods = "mmc2"; | |
1082 | ti,needs-special-reset; | |
7aa1a408 | 1083 | dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; |
57cd681b TR |
1084 | dma-names = "tx", "rx"; |
1085 | status = "disabled"; | |
4ddaa6ce | 1086 | max-frequency = <192000000>; |
2adee41d JJH |
1087 | sd-uhs-sdr25; |
1088 | sd-uhs-sdr12; | |
1089 | mmc-hs200-1_8v; | |
1090 | mmc-ddr-1_8v; | |
57cd681b TR |
1091 | }; |
1092 | ||
1093 | mmc3: mmc@480ad000 { | |
6ba41e5d | 1094 | compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; |
57cd681b TR |
1095 | reg = <0x480ad000 0x400>; |
1096 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
1097 | ti,hwmods = "mmc3"; | |
1098 | ti,needs-special-reset; | |
7aa1a408 | 1099 | dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; |
57cd681b TR |
1100 | dma-names = "tx", "rx"; |
1101 | status = "disabled"; | |
4ddaa6ce LV |
1102 | /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ |
1103 | max-frequency = <64000000>; | |
2adee41d JJH |
1104 | sd-uhs-sdr12; |
1105 | sd-uhs-sdr25; | |
1106 | sd-uhs-sdr50; | |
57cd681b TR |
1107 | }; |
1108 | ||
1109 | mmc4: mmc@480d1000 { | |
6ba41e5d | 1110 | compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; |
57cd681b TR |
1111 | reg = <0x480d1000 0x400>; |
1112 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
1113 | ti,hwmods = "mmc4"; | |
1114 | ti,needs-special-reset; | |
7aa1a408 | 1115 | dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; |
57cd681b TR |
1116 | dma-names = "tx", "rx"; |
1117 | status = "disabled"; | |
4ddaa6ce | 1118 | max-frequency = <192000000>; |
2adee41d JJH |
1119 | sd-uhs-sdr12; |
1120 | sd-uhs-sdr25; | |
57cd681b TR |
1121 | }; |
1122 | ||
7aa1a408 LV |
1123 | mmu0_dsp1: mmu@40d01000 { |
1124 | compatible = "ti,dra7-dsp-iommu"; | |
1125 | reg = <0x40d01000 0x100>; | |
1126 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
1127 | ti,hwmods = "mmu0_dsp1"; | |
1128 | #iommu-cells = <0>; | |
1129 | ti,syscon-mmuconfig = <&dsp1_system 0x0>; | |
1130 | status = "disabled"; | |
1131 | }; | |
1132 | ||
1133 | mmu1_dsp1: mmu@40d02000 { | |
1134 | compatible = "ti,dra7-dsp-iommu"; | |
1135 | reg = <0x40d02000 0x100>; | |
1136 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
1137 | ti,hwmods = "mmu1_dsp1"; | |
1138 | #iommu-cells = <0>; | |
1139 | ti,syscon-mmuconfig = <&dsp1_system 0x1>; | |
1140 | status = "disabled"; | |
1141 | }; | |
1142 | ||
1143 | mmu_ipu1: mmu@58882000 { | |
1144 | compatible = "ti,dra7-iommu"; | |
1145 | reg = <0x58882000 0x100>; | |
1146 | interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; | |
1147 | ti,hwmods = "mmu_ipu1"; | |
1148 | #iommu-cells = <0>; | |
1149 | ti,iommu-bus-err-back; | |
1150 | status = "disabled"; | |
1151 | }; | |
1152 | ||
1153 | mmu_ipu2: mmu@55082000 { | |
1154 | compatible = "ti,dra7-iommu"; | |
1155 | reg = <0x55082000 0x100>; | |
1156 | interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; | |
1157 | ti,hwmods = "mmu_ipu2"; | |
1158 | #iommu-cells = <0>; | |
1159 | ti,iommu-bus-err-back; | |
1160 | status = "disabled"; | |
1161 | }; | |
1162 | ||
57cd681b TR |
1163 | abb_mpu: regulator-abb-mpu { |
1164 | compatible = "ti,abb-v3"; | |
1165 | regulator-name = "abb_mpu"; | |
1166 | #address-cells = <0>; | |
1167 | #size-cells = <0>; | |
1168 | clocks = <&sys_clkin1>; | |
1169 | ti,settling-time = <50>; | |
1170 | ti,clock-cycles = <16>; | |
1171 | ||
1172 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, | |
1173 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, | |
1174 | <0x4ae0c158 0x4>; | |
1175 | reg-names = "setup-address", "control-address", | |
1176 | "int-address", "efuse-address", | |
1177 | "ldo-address"; | |
1178 | ti,tranxdone-status-mask = <0x80>; | |
1179 | /* LDOVBBMPU_FBB_MUX_CTRL */ | |
1180 | ti,ldovbb-override-mask = <0x400>; | |
1181 | /* LDOVBBMPU_FBB_VSET_OUT */ | |
1182 | ti,ldovbb-vset-mask = <0x1F>; | |
1183 | ||
1184 | /* | |
1185 | * NOTE: only FBB mode used but actual vset will | |
1186 | * determine final biasing | |
1187 | */ | |
1188 | ti,abb_info = < | |
1189 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1190 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
1191 | 1160000 0 0x4 0 0x02000000 0x01F00000 | |
1192 | 1210000 0 0x8 0 0x02000000 0x01F00000 | |
1193 | >; | |
1194 | }; | |
1195 | ||
1196 | abb_ivahd: regulator-abb-ivahd { | |
1197 | compatible = "ti,abb-v3"; | |
1198 | regulator-name = "abb_ivahd"; | |
1199 | #address-cells = <0>; | |
1200 | #size-cells = <0>; | |
1201 | clocks = <&sys_clkin1>; | |
1202 | ti,settling-time = <50>; | |
1203 | ti,clock-cycles = <16>; | |
1204 | ||
1205 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, | |
1206 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, | |
1207 | <0x4a002470 0x4>; | |
1208 | reg-names = "setup-address", "control-address", | |
1209 | "int-address", "efuse-address", | |
1210 | "ldo-address"; | |
1211 | ti,tranxdone-status-mask = <0x40000000>; | |
1212 | /* LDOVBBIVA_FBB_MUX_CTRL */ | |
1213 | ti,ldovbb-override-mask = <0x400>; | |
1214 | /* LDOVBBIVA_FBB_VSET_OUT */ | |
1215 | ti,ldovbb-vset-mask = <0x1F>; | |
1216 | ||
1217 | /* | |
1218 | * NOTE: only FBB mode used but actual vset will | |
1219 | * determine final biasing | |
1220 | */ | |
1221 | ti,abb_info = < | |
1222 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1223 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
1224 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
1225 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
1226 | >; | |
1227 | }; | |
1228 | ||
1229 | abb_dspeve: regulator-abb-dspeve { | |
1230 | compatible = "ti,abb-v3"; | |
1231 | regulator-name = "abb_dspeve"; | |
1232 | #address-cells = <0>; | |
1233 | #size-cells = <0>; | |
1234 | clocks = <&sys_clkin1>; | |
1235 | ti,settling-time = <50>; | |
1236 | ti,clock-cycles = <16>; | |
1237 | ||
1238 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, | |
1239 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, | |
1240 | <0x4a00246c 0x4>; | |
1241 | reg-names = "setup-address", "control-address", | |
1242 | "int-address", "efuse-address", | |
1243 | "ldo-address"; | |
1244 | ti,tranxdone-status-mask = <0x20000000>; | |
1245 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ | |
1246 | ti,ldovbb-override-mask = <0x400>; | |
1247 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ | |
1248 | ti,ldovbb-vset-mask = <0x1F>; | |
1249 | ||
1250 | /* | |
1251 | * NOTE: only FBB mode used but actual vset will | |
1252 | * determine final biasing | |
1253 | */ | |
1254 | ti,abb_info = < | |
1255 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1256 | 1055000 0 0x0 0 0x02000000 0x01F00000 | |
1257 | 1150000 0 0x4 0 0x02000000 0x01F00000 | |
1258 | 1250000 0 0x8 0 0x02000000 0x01F00000 | |
1259 | >; | |
1260 | }; | |
1261 | ||
1262 | abb_gpu: regulator-abb-gpu { | |
1263 | compatible = "ti,abb-v3"; | |
1264 | regulator-name = "abb_gpu"; | |
1265 | #address-cells = <0>; | |
1266 | #size-cells = <0>; | |
1267 | clocks = <&sys_clkin1>; | |
1268 | ti,settling-time = <50>; | |
1269 | ti,clock-cycles = <16>; | |
1270 | ||
1271 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, | |
1272 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, | |
1273 | <0x4ae0c154 0x4>; | |
1274 | reg-names = "setup-address", "control-address", | |
1275 | "int-address", "efuse-address", | |
1276 | "ldo-address"; | |
1277 | ti,tranxdone-status-mask = <0x10000000>; | |
1278 | /* LDOVBBGPU_FBB_MUX_CTRL */ | |
1279 | ti,ldovbb-override-mask = <0x400>; | |
1280 | /* LDOVBBGPU_FBB_VSET_OUT */ | |
1281 | ti,ldovbb-vset-mask = <0x1F>; | |
1282 | ||
1283 | /* | |
1284 | * NOTE: only FBB mode used but actual vset will | |
1285 | * determine final biasing | |
1286 | */ | |
1287 | ti,abb_info = < | |
1288 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1289 | 1090000 0 0x0 0 0x02000000 0x01F00000 | |
1290 | 1210000 0 0x4 0 0x02000000 0x01F00000 | |
1291 | 1280000 0 0x8 0 0x02000000 0x01F00000 | |
1292 | >; | |
1293 | }; | |
1294 | ||
1295 | mcspi1: spi@48098000 { | |
1296 | compatible = "ti,omap4-mcspi"; | |
1297 | reg = <0x48098000 0x200>; | |
1298 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
1299 | #address-cells = <1>; | |
1300 | #size-cells = <0>; | |
1301 | ti,hwmods = "mcspi1"; | |
1302 | ti,spi-num-cs = <4>; | |
7aa1a408 LV |
1303 | dmas = <&sdma_xbar 35>, |
1304 | <&sdma_xbar 36>, | |
1305 | <&sdma_xbar 37>, | |
1306 | <&sdma_xbar 38>, | |
1307 | <&sdma_xbar 39>, | |
1308 | <&sdma_xbar 40>, | |
1309 | <&sdma_xbar 41>, | |
1310 | <&sdma_xbar 42>; | |
57cd681b TR |
1311 | dma-names = "tx0", "rx0", "tx1", "rx1", |
1312 | "tx2", "rx2", "tx3", "rx3"; | |
1313 | status = "disabled"; | |
1314 | }; | |
1315 | ||
1316 | mcspi2: spi@4809a000 { | |
1317 | compatible = "ti,omap4-mcspi"; | |
1318 | reg = <0x4809a000 0x200>; | |
1319 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
1320 | #address-cells = <1>; | |
1321 | #size-cells = <0>; | |
1322 | ti,hwmods = "mcspi2"; | |
1323 | ti,spi-num-cs = <2>; | |
7aa1a408 LV |
1324 | dmas = <&sdma_xbar 43>, |
1325 | <&sdma_xbar 44>, | |
1326 | <&sdma_xbar 45>, | |
1327 | <&sdma_xbar 46>; | |
57cd681b TR |
1328 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
1329 | status = "disabled"; | |
1330 | }; | |
1331 | ||
1332 | mcspi3: spi@480b8000 { | |
1333 | compatible = "ti,omap4-mcspi"; | |
1334 | reg = <0x480b8000 0x200>; | |
1335 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
1336 | #address-cells = <1>; | |
1337 | #size-cells = <0>; | |
1338 | ti,hwmods = "mcspi3"; | |
1339 | ti,spi-num-cs = <2>; | |
7aa1a408 | 1340 | dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; |
57cd681b TR |
1341 | dma-names = "tx0", "rx0"; |
1342 | status = "disabled"; | |
1343 | }; | |
1344 | ||
1345 | mcspi4: spi@480ba000 { | |
1346 | compatible = "ti,omap4-mcspi"; | |
1347 | reg = <0x480ba000 0x200>; | |
1348 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
1349 | #address-cells = <1>; | |
1350 | #size-cells = <0>; | |
1351 | ti,hwmods = "mcspi4"; | |
1352 | ti,spi-num-cs = <1>; | |
7aa1a408 | 1353 | dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; |
57cd681b TR |
1354 | dma-names = "tx0", "rx0"; |
1355 | status = "disabled"; | |
1356 | }; | |
1357 | ||
1358 | qspi: qspi@4b300000 { | |
1359 | compatible = "ti,dra7xxx-qspi"; | |
830aba2c | 1360 | reg = <0x4b300000 0x100>, |
7aa1a408 LV |
1361 | <0x5c000000 0x4000000>; |
1362 | reg-names = "qspi_base", "qspi_mmap"; | |
1363 | syscon-chipselects = <&scm_conf 0x558>; | |
57cd681b TR |
1364 | #address-cells = <1>; |
1365 | #size-cells = <0>; | |
1366 | ti,hwmods = "qspi"; | |
1367 | clocks = <&qspi_gfclk_div>; | |
1368 | clock-names = "fck"; | |
1369 | num-cs = <4>; | |
1370 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; | |
1371 | status = "disabled"; | |
1372 | }; | |
1373 | ||
57cd681b TR |
1374 | /* OCP2SCP3 */ |
1375 | ocp2scp@4a090000 { | |
1376 | compatible = "ti,omap-ocp2scp"; | |
1377 | #address-cells = <1>; | |
1378 | #size-cells = <1>; | |
1379 | ranges; | |
1380 | reg = <0x4a090000 0x20>; | |
1381 | ti,hwmods = "ocp2scp3"; | |
1382 | sata_phy: phy@4A096000 { | |
1383 | compatible = "ti,phy-pipe3-sata"; | |
1384 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
1385 | <0x4A096400 0x64>, /* phy_tx */ | |
1386 | <0x4A096800 0x40>; /* pll_ctrl */ | |
1387 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
7aa1a408 | 1388 | syscon-phy-power = <&scm_conf 0x374>; |
57cd681b TR |
1389 | clocks = <&sys_clkin1>, <&sata_ref_clk>; |
1390 | clock-names = "sysclk", "refclk"; | |
7aa1a408 | 1391 | syscon-pllreset = <&scm_conf 0x3fc>; |
57cd681b TR |
1392 | #phy-cells = <0>; |
1393 | }; | |
1394 | ||
1395 | pcie1_phy: pciephy@4a094000 { | |
1396 | compatible = "ti,phy-pipe3-pcie"; | |
1397 | reg = <0x4a094000 0x80>, /* phy_rx */ | |
1398 | <0x4a094400 0x64>; /* phy_tx */ | |
1399 | reg-names = "phy_rx", "phy_tx"; | |
7aa1a408 LV |
1400 | syscon-phy-power = <&scm_conf_pcie 0x1c>; |
1401 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
57cd681b TR |
1402 | clocks = <&dpll_pcie_ref_ck>, |
1403 | <&dpll_pcie_ref_m2ldo_ck>, | |
1404 | <&optfclk_pciephy1_32khz>, | |
1405 | <&optfclk_pciephy1_clk>, | |
1406 | <&optfclk_pciephy1_div_clk>, | |
7aa1a408 LV |
1407 | <&optfclk_pciephy_div>, |
1408 | <&sys_clkin1>; | |
57cd681b TR |
1409 | clock-names = "dpll_ref", "dpll_ref_m2", |
1410 | "wkupclk", "refclk", | |
7aa1a408 | 1411 | "div-clk", "phy-div", "sysclk"; |
57cd681b TR |
1412 | #phy-cells = <0>; |
1413 | }; | |
1414 | ||
1415 | pcie2_phy: pciephy@4a095000 { | |
1416 | compatible = "ti,phy-pipe3-pcie"; | |
1417 | reg = <0x4a095000 0x80>, /* phy_rx */ | |
1418 | <0x4a095400 0x64>; /* phy_tx */ | |
1419 | reg-names = "phy_rx", "phy_tx"; | |
7aa1a408 LV |
1420 | syscon-phy-power = <&scm_conf_pcie 0x20>; |
1421 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
57cd681b TR |
1422 | clocks = <&dpll_pcie_ref_ck>, |
1423 | <&dpll_pcie_ref_m2ldo_ck>, | |
1424 | <&optfclk_pciephy2_32khz>, | |
1425 | <&optfclk_pciephy2_clk>, | |
1426 | <&optfclk_pciephy2_div_clk>, | |
7aa1a408 LV |
1427 | <&optfclk_pciephy_div>, |
1428 | <&sys_clkin1>; | |
57cd681b TR |
1429 | clock-names = "dpll_ref", "dpll_ref_m2", |
1430 | "wkupclk", "refclk", | |
7aa1a408 | 1431 | "div-clk", "phy-div", "sysclk"; |
57cd681b TR |
1432 | #phy-cells = <0>; |
1433 | status = "disabled"; | |
1434 | }; | |
1435 | }; | |
1436 | ||
1437 | sata: sata@4a141100 { | |
1438 | compatible = "snps,dwc-ahci"; | |
1439 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
1440 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
1441 | phys = <&sata_phy>; | |
1442 | phy-names = "sata-phy"; | |
1443 | clocks = <&sata_ref_clk>; | |
1444 | ti,hwmods = "sata"; | |
4ddaa6ce | 1445 | ports-implemented = <0x1>; |
57cd681b TR |
1446 | }; |
1447 | ||
57cd681b TR |
1448 | rtc: rtc@48838000 { |
1449 | compatible = "ti,am3352-rtc"; | |
1450 | reg = <0x48838000 0x100>; | |
1451 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | |
1452 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; | |
1453 | ti,hwmods = "rtcss"; | |
1454 | clocks = <&sys_32k_ck>; | |
1455 | }; | |
1456 | ||
57cd681b TR |
1457 | /* OCP2SCP1 */ |
1458 | ocp2scp@4a080000 { | |
1459 | compatible = "ti,omap-ocp2scp"; | |
1460 | #address-cells = <1>; | |
1461 | #size-cells = <1>; | |
1462 | ranges; | |
1463 | reg = <0x4a080000 0x20>; | |
1464 | ti,hwmods = "ocp2scp1"; | |
1465 | ||
1466 | usb2_phy1: phy@4a084000 { | |
7aa1a408 | 1467 | compatible = "ti,dra7x-usb2", "ti,omap-usb2"; |
57cd681b | 1468 | reg = <0x4a084000 0x400>; |
7aa1a408 | 1469 | syscon-phy-power = <&scm_conf 0x300>; |
57cd681b TR |
1470 | clocks = <&usb_phy1_always_on_clk32k>, |
1471 | <&usb_otg_ss1_refclk960m>; | |
1472 | clock-names = "wkupclk", | |
1473 | "refclk"; | |
1474 | #phy-cells = <0>; | |
1475 | }; | |
1476 | ||
1477 | usb2_phy2: phy@4a085000 { | |
7aa1a408 LV |
1478 | compatible = "ti,dra7x-usb2-phy2", |
1479 | "ti,omap-usb2"; | |
57cd681b | 1480 | reg = <0x4a085000 0x400>; |
7aa1a408 | 1481 | syscon-phy-power = <&scm_conf 0xe74>; |
57cd681b TR |
1482 | clocks = <&usb_phy2_always_on_clk32k>, |
1483 | <&usb_otg_ss2_refclk960m>; | |
1484 | clock-names = "wkupclk", | |
1485 | "refclk"; | |
1486 | #phy-cells = <0>; | |
1487 | }; | |
1488 | ||
1489 | usb3_phy1: phy@4a084400 { | |
1490 | compatible = "ti,omap-usb3"; | |
1491 | reg = <0x4a084400 0x80>, | |
1492 | <0x4a084800 0x64>, | |
1493 | <0x4a084c00 0x40>; | |
1494 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
7aa1a408 | 1495 | syscon-phy-power = <&scm_conf 0x370>; |
57cd681b TR |
1496 | clocks = <&usb_phy3_always_on_clk32k>, |
1497 | <&sys_clkin1>, | |
1498 | <&usb_otg_ss1_refclk960m>; | |
1499 | clock-names = "wkupclk", | |
1500 | "sysclk", | |
1501 | "refclk"; | |
1502 | #phy-cells = <0>; | |
1503 | }; | |
1504 | }; | |
1505 | ||
1506 | omap_dwc3_1: omap_dwc3_1@48880000 { | |
1507 | compatible = "ti,dwc3"; | |
1508 | ti,hwmods = "usb_otg_ss1"; | |
1509 | reg = <0x48880000 0x10000>; | |
1510 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
1511 | #address-cells = <1>; | |
1512 | #size-cells = <1>; | |
1513 | utmi-mode = <2>; | |
1514 | ranges; | |
1515 | usb1: usb@48890000 { | |
1516 | compatible = "snps,dwc3"; | |
1517 | reg = <0x48890000 0x17000>; | |
7aa1a408 LV |
1518 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
1519 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, | |
1520 | <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
1521 | interrupt-names = "peripheral", | |
1522 | "host", | |
1523 | "otg"; | |
57cd681b TR |
1524 | phys = <&usb2_phy1>, <&usb3_phy1>; |
1525 | phy-names = "usb2-phy", "usb3-phy"; | |
57cd681b TR |
1526 | maximum-speed = "super-speed"; |
1527 | dr_mode = "otg"; | |
1528 | snps,dis_u3_susphy_quirk; | |
1529 | snps,dis_u2_susphy_quirk; | |
1530 | }; | |
1531 | }; | |
1532 | ||
1533 | omap_dwc3_2: omap_dwc3_2@488c0000 { | |
1534 | compatible = "ti,dwc3"; | |
1535 | ti,hwmods = "usb_otg_ss2"; | |
1536 | reg = <0x488c0000 0x10000>; | |
1537 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
1538 | #address-cells = <1>; | |
1539 | #size-cells = <1>; | |
1540 | utmi-mode = <2>; | |
1541 | ranges; | |
1542 | usb2: usb@488d0000 { | |
1543 | compatible = "snps,dwc3"; | |
1544 | reg = <0x488d0000 0x17000>; | |
7aa1a408 LV |
1545 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
1546 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
1547 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
1548 | interrupt-names = "peripheral", | |
1549 | "host", | |
1550 | "otg"; | |
57cd681b TR |
1551 | phys = <&usb2_phy2>; |
1552 | phy-names = "usb2-phy"; | |
57cd681b TR |
1553 | maximum-speed = "high-speed"; |
1554 | dr_mode = "otg"; | |
1555 | snps,dis_u3_susphy_quirk; | |
1556 | snps,dis_u2_susphy_quirk; | |
1557 | }; | |
1558 | }; | |
1559 | ||
1560 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ | |
1561 | omap_dwc3_3: omap_dwc3_3@48900000 { | |
1562 | compatible = "ti,dwc3"; | |
1563 | ti,hwmods = "usb_otg_ss3"; | |
1564 | reg = <0x48900000 0x10000>; | |
1565 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
1566 | #address-cells = <1>; | |
1567 | #size-cells = <1>; | |
1568 | utmi-mode = <2>; | |
1569 | ranges; | |
1570 | status = "disabled"; | |
1571 | usb3: usb@48910000 { | |
1572 | compatible = "snps,dwc3"; | |
1573 | reg = <0x48910000 0x17000>; | |
7aa1a408 LV |
1574 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
1575 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
1576 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
1577 | interrupt-names = "peripheral", | |
1578 | "host", | |
1579 | "otg"; | |
57cd681b TR |
1580 | maximum-speed = "high-speed"; |
1581 | dr_mode = "otg"; | |
1582 | snps,dis_u3_susphy_quirk; | |
1583 | snps,dis_u2_susphy_quirk; | |
1584 | }; | |
1585 | }; | |
1586 | ||
1587 | elm: elm@48078000 { | |
1588 | compatible = "ti,am3352-elm"; | |
1589 | reg = <0x48078000 0xfc0>; /* device IO registers */ | |
1590 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
1591 | ti,hwmods = "elm"; | |
1592 | status = "disabled"; | |
1593 | }; | |
1594 | ||
1595 | gpmc: gpmc@50000000 { | |
1596 | compatible = "ti,am3352-gpmc"; | |
1597 | ti,hwmods = "gpmc"; | |
1598 | reg = <0x50000000 0x37c>; /* device IO registers */ | |
1599 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
7aa1a408 LV |
1600 | dmas = <&edma_xbar 4 0>; |
1601 | dma-names = "rxtx"; | |
57cd681b TR |
1602 | gpmc,num-cs = <8>; |
1603 | gpmc,num-waitpins = <2>; | |
1604 | #address-cells = <2>; | |
1605 | #size-cells = <1>; | |
7aa1a408 LV |
1606 | interrupt-controller; |
1607 | #interrupt-cells = <2>; | |
1608 | gpio-controller; | |
1609 | #gpio-cells = <2>; | |
57cd681b TR |
1610 | status = "disabled"; |
1611 | }; | |
1612 | ||
1613 | atl: atl@4843c000 { | |
1614 | compatible = "ti,dra7-atl"; | |
1615 | reg = <0x4843c000 0x3ff>; | |
1616 | ti,hwmods = "atl"; | |
1617 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, | |
1618 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; | |
1619 | clocks = <&atl_gfclk_mux>; | |
1620 | clock-names = "fck"; | |
1621 | status = "disabled"; | |
1622 | }; | |
1623 | ||
7aa1a408 LV |
1624 | mcasp1: mcasp@48460000 { |
1625 | compatible = "ti,dra7-mcasp-audio"; | |
1626 | ti,hwmods = "mcasp1"; | |
1627 | reg = <0x48460000 0x2000>, | |
1628 | <0x45800000 0x1000>; | |
1629 | reg-names = "mpu","dat"; | |
1630 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
1631 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
1632 | interrupt-names = "tx", "rx"; | |
1633 | dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; | |
1634 | dma-names = "tx", "rx"; | |
1635 | clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, | |
1636 | <&mcasp1_ahclkr_mux>; | |
1637 | clock-names = "fck", "ahclkx", "ahclkr"; | |
1638 | status = "disabled"; | |
1639 | }; | |
1640 | ||
1641 | mcasp2: mcasp@48464000 { | |
1642 | compatible = "ti,dra7-mcasp-audio"; | |
1643 | ti,hwmods = "mcasp2"; | |
1644 | reg = <0x48464000 0x2000>, | |
1645 | <0x45c00000 0x1000>; | |
1646 | reg-names = "mpu","dat"; | |
1647 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
1648 | <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
1649 | interrupt-names = "tx", "rx"; | |
1650 | dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; | |
1651 | dma-names = "tx", "rx"; | |
1652 | clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, | |
1653 | <&mcasp2_ahclkr_mux>; | |
1654 | clock-names = "fck", "ahclkx", "ahclkr"; | |
1655 | status = "disabled"; | |
1656 | }; | |
1657 | ||
1658 | mcasp3: mcasp@48468000 { | |
1659 | compatible = "ti,dra7-mcasp-audio"; | |
1660 | ti,hwmods = "mcasp3"; | |
1661 | reg = <0x48468000 0x2000>, | |
1662 | <0x46000000 0x1000>; | |
1663 | reg-names = "mpu","dat"; | |
1664 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, | |
1665 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
1666 | interrupt-names = "tx", "rx"; | |
1667 | dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; | |
1668 | dma-names = "tx", "rx"; | |
1669 | clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; | |
1670 | clock-names = "fck", "ahclkx"; | |
1671 | status = "disabled"; | |
1672 | }; | |
1673 | ||
1674 | mcasp4: mcasp@4846c000 { | |
1675 | compatible = "ti,dra7-mcasp-audio"; | |
1676 | ti,hwmods = "mcasp4"; | |
1677 | reg = <0x4846c000 0x2000>, | |
1678 | <0x48436000 0x1000>; | |
1679 | reg-names = "mpu","dat"; | |
1680 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
1681 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
1682 | interrupt-names = "tx", "rx"; | |
1683 | dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; | |
1684 | dma-names = "tx", "rx"; | |
1685 | clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; | |
1686 | clock-names = "fck", "ahclkx"; | |
1687 | status = "disabled"; | |
1688 | }; | |
1689 | ||
1690 | mcasp5: mcasp@48470000 { | |
1691 | compatible = "ti,dra7-mcasp-audio"; | |
1692 | ti,hwmods = "mcasp5"; | |
1693 | reg = <0x48470000 0x2000>, | |
1694 | <0x4843a000 0x1000>; | |
1695 | reg-names = "mpu","dat"; | |
1696 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, | |
1697 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
1698 | interrupt-names = "tx", "rx"; | |
1699 | dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; | |
1700 | dma-names = "tx", "rx"; | |
1701 | clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; | |
1702 | clock-names = "fck", "ahclkx"; | |
1703 | status = "disabled"; | |
1704 | }; | |
1705 | ||
1706 | mcasp6: mcasp@48474000 { | |
1707 | compatible = "ti,dra7-mcasp-audio"; | |
1708 | ti,hwmods = "mcasp6"; | |
1709 | reg = <0x48474000 0x2000>, | |
1710 | <0x4844c000 0x1000>; | |
1711 | reg-names = "mpu","dat"; | |
1712 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
1713 | <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
1714 | interrupt-names = "tx", "rx"; | |
1715 | dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; | |
1716 | dma-names = "tx", "rx"; | |
1717 | clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; | |
1718 | clock-names = "fck", "ahclkx"; | |
1719 | status = "disabled"; | |
1720 | }; | |
1721 | ||
1722 | mcasp7: mcasp@48478000 { | |
1723 | compatible = "ti,dra7-mcasp-audio"; | |
1724 | ti,hwmods = "mcasp7"; | |
1725 | reg = <0x48478000 0x2000>, | |
1726 | <0x48450000 0x1000>; | |
1727 | reg-names = "mpu","dat"; | |
1728 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, | |
1729 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
1730 | interrupt-names = "tx", "rx"; | |
1731 | dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; | |
1732 | dma-names = "tx", "rx"; | |
1733 | clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; | |
1734 | clock-names = "fck", "ahclkx"; | |
1735 | status = "disabled"; | |
1736 | }; | |
1737 | ||
1738 | mcasp8: mcasp@4847c000 { | |
1739 | compatible = "ti,dra7-mcasp-audio"; | |
1740 | ti,hwmods = "mcasp8"; | |
1741 | reg = <0x4847c000 0x2000>, | |
1742 | <0x48454000 0x1000>; | |
1743 | reg-names = "mpu","dat"; | |
1744 | interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, | |
1745 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; | |
1746 | interrupt-names = "tx", "rx"; | |
1747 | dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; | |
1748 | dma-names = "tx", "rx"; | |
1749 | clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; | |
1750 | clock-names = "fck", "ahclkx"; | |
1751 | status = "disabled"; | |
1752 | }; | |
1753 | ||
57cd681b TR |
1754 | crossbar_mpu: crossbar@4a002a48 { |
1755 | compatible = "ti,irq-crossbar"; | |
1756 | reg = <0x4a002a48 0x130>; | |
1757 | interrupt-controller; | |
1758 | interrupt-parent = <&wakeupgen>; | |
1759 | #interrupt-cells = <3>; | |
1760 | ti,max-irqs = <160>; | |
1761 | ti,max-crossbar-sources = <MAX_SOURCES>; | |
1762 | ti,reg-size = <2>; | |
1763 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; | |
1764 | ti,irqs-skip = <10 133 139 140>; | |
1765 | ti,irqs-safe-map = <0>; | |
1766 | }; | |
1767 | ||
844f8144 | 1768 | mac: ethernet@48484000 { |
7aa1a408 | 1769 | compatible = "ti,dra7-cpsw","ti,cpsw"; |
57cd681b | 1770 | ti,hwmods = "gmac"; |
7aa1a408 | 1771 | clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; |
57cd681b TR |
1772 | clock-names = "fck", "cpts"; |
1773 | cpdma_channels = <8>; | |
1774 | ale_entries = <1024>; | |
1775 | bd_ram_size = <0x2000>; | |
57cd681b TR |
1776 | mac_control = <0x20>; |
1777 | slaves = <2>; | |
1778 | active_slave = <0>; | |
7aa1a408 | 1779 | cpts_clock_mult = <0x784CFE14>; |
57cd681b TR |
1780 | cpts_clock_shift = <29>; |
1781 | reg = <0x48484000 0x1000 | |
1782 | 0x48485200 0x2E00>; | |
1783 | #address-cells = <1>; | |
1784 | #size-cells = <1>; | |
7aa1a408 LV |
1785 | |
1786 | /* | |
1787 | * Do not allow gating of cpsw clock as workaround | |
1788 | * for errata i877. Keeping internal clock disabled | |
1789 | * causes the device switching characteristics | |
1790 | * to degrade over time and eventually fail to meet | |
1791 | * the data manual delay time/skew specs. | |
1792 | */ | |
1793 | ti,no-idle; | |
1794 | ||
57cd681b TR |
1795 | /* |
1796 | * rx_thresh_pend | |
1797 | * rx_pend | |
1798 | * tx_pend | |
1799 | * misc_pend | |
1800 | */ | |
1801 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
1802 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
1803 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
1804 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; | |
1805 | ranges; | |
4ddaa6ce | 1806 | syscon = <&scm_conf>; |
57cd681b TR |
1807 | status = "disabled"; |
1808 | ||
1809 | davinci_mdio: mdio@48485000 { | |
7aa1a408 | 1810 | compatible = "ti,cpsw-mdio","ti,davinci_mdio"; |
57cd681b TR |
1811 | #address-cells = <1>; |
1812 | #size-cells = <0>; | |
1813 | ti,hwmods = "davinci_mdio"; | |
1814 | bus_freq = <1000000>; | |
1815 | reg = <0x48485000 0x100>; | |
1816 | }; | |
1817 | ||
1818 | cpsw_emac0: slave@48480200 { | |
1819 | /* Filled in by U-Boot */ | |
1820 | mac-address = [ 00 00 00 00 00 00 ]; | |
1821 | }; | |
1822 | ||
1823 | cpsw_emac1: slave@48480300 { | |
1824 | /* Filled in by U-Boot */ | |
1825 | mac-address = [ 00 00 00 00 00 00 ]; | |
1826 | }; | |
1827 | ||
1828 | phy_sel: cpsw-phy-sel@4a002554 { | |
1829 | compatible = "ti,dra7xx-cpsw-phy-sel"; | |
1830 | reg= <0x4a002554 0x4>; | |
1831 | reg-names = "gmii-sel"; | |
1832 | }; | |
1833 | }; | |
1834 | ||
1835 | dcan1: can@481cc000 { | |
1836 | compatible = "ti,dra7-d_can"; | |
1837 | ti,hwmods = "dcan1"; | |
1838 | reg = <0x4ae3c000 0x2000>; | |
1839 | syscon-raminit = <&scm_conf 0x558 0>; | |
1840 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; | |
1841 | clocks = <&dcan1_sys_clk_mux>; | |
1842 | status = "disabled"; | |
1843 | }; | |
1844 | ||
1845 | dcan2: can@481d0000 { | |
1846 | compatible = "ti,dra7-d_can"; | |
1847 | ti,hwmods = "dcan2"; | |
1848 | reg = <0x48480000 0x2000>; | |
1849 | syscon-raminit = <&scm_conf 0x558 1>; | |
1850 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; | |
1851 | clocks = <&sys_clkin1>; | |
1852 | status = "disabled"; | |
1853 | }; | |
1854 | ||
1855 | dss: dss@58000000 { | |
1856 | compatible = "ti,dra7-dss"; | |
1857 | /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ | |
1858 | /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ | |
1859 | status = "disabled"; | |
1860 | ti,hwmods = "dss_core"; | |
1861 | /* CTRL_CORE_DSS_PLL_CONTROL */ | |
1862 | syscon-pll-ctrl = <&scm_conf 0x538>; | |
1863 | #address-cells = <1>; | |
1864 | #size-cells = <1>; | |
1865 | ranges; | |
1866 | ||
1867 | dispc@58001000 { | |
1868 | compatible = "ti,dra7-dispc"; | |
1869 | reg = <0x58001000 0x1000>; | |
1870 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
1871 | ti,hwmods = "dss_dispc"; | |
1872 | clocks = <&dss_dss_clk>; | |
1873 | clock-names = "fck"; | |
1874 | /* CTRL_CORE_SMA_SW_1 */ | |
1875 | syscon-pol = <&scm_conf 0x534>; | |
1876 | }; | |
1877 | ||
1878 | hdmi: encoder@58060000 { | |
1879 | compatible = "ti,dra7-hdmi"; | |
1880 | reg = <0x58040000 0x200>, | |
1881 | <0x58040200 0x80>, | |
1882 | <0x58040300 0x80>, | |
1883 | <0x58060000 0x19000>; | |
1884 | reg-names = "wp", "pll", "phy", "core"; | |
1885 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
1886 | status = "disabled"; | |
1887 | ti,hwmods = "dss_hdmi"; | |
1888 | clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; | |
1889 | clock-names = "fck", "sys_clk"; | |
1890 | }; | |
1891 | }; | |
7aa1a408 LV |
1892 | |
1893 | epwmss0: epwmss@4843e000 { | |
1894 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
1895 | reg = <0x4843e000 0x30>; | |
1896 | ti,hwmods = "epwmss0"; | |
1897 | #address-cells = <1>; | |
1898 | #size-cells = <1>; | |
1899 | status = "disabled"; | |
1900 | ranges; | |
1901 | ||
1902 | ehrpwm0: pwm@4843e200 { | |
1903 | compatible = "ti,dra746-ehrpwm", | |
1904 | "ti,am3352-ehrpwm"; | |
1905 | #pwm-cells = <3>; | |
1906 | reg = <0x4843e200 0x80>; | |
1907 | clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; | |
1908 | clock-names = "tbclk", "fck"; | |
1909 | status = "disabled"; | |
1910 | }; | |
1911 | ||
1912 | ecap0: ecap@4843e100 { | |
1913 | compatible = "ti,dra746-ecap", | |
1914 | "ti,am3352-ecap"; | |
1915 | #pwm-cells = <3>; | |
1916 | reg = <0x4843e100 0x80>; | |
1917 | clocks = <&l4_root_clk_div>; | |
1918 | clock-names = "fck"; | |
1919 | status = "disabled"; | |
1920 | }; | |
1921 | }; | |
1922 | ||
1923 | epwmss1: epwmss@48440000 { | |
1924 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
1925 | reg = <0x48440000 0x30>; | |
1926 | ti,hwmods = "epwmss1"; | |
1927 | #address-cells = <1>; | |
1928 | #size-cells = <1>; | |
1929 | status = "disabled"; | |
1930 | ranges; | |
1931 | ||
1932 | ehrpwm1: pwm@48440200 { | |
1933 | compatible = "ti,dra746-ehrpwm", | |
1934 | "ti,am3352-ehrpwm"; | |
1935 | #pwm-cells = <3>; | |
1936 | reg = <0x48440200 0x80>; | |
1937 | clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; | |
1938 | clock-names = "tbclk", "fck"; | |
1939 | status = "disabled"; | |
1940 | }; | |
1941 | ||
1942 | ecap1: ecap@48440100 { | |
1943 | compatible = "ti,dra746-ecap", | |
1944 | "ti,am3352-ecap"; | |
1945 | #pwm-cells = <3>; | |
1946 | reg = <0x48440100 0x80>; | |
1947 | clocks = <&l4_root_clk_div>; | |
1948 | clock-names = "fck"; | |
1949 | status = "disabled"; | |
1950 | }; | |
1951 | }; | |
1952 | ||
1953 | epwmss2: epwmss@48442000 { | |
1954 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
1955 | reg = <0x48442000 0x30>; | |
1956 | ti,hwmods = "epwmss2"; | |
1957 | #address-cells = <1>; | |
1958 | #size-cells = <1>; | |
1959 | status = "disabled"; | |
1960 | ranges; | |
1961 | ||
1962 | ehrpwm2: pwm@48442200 { | |
1963 | compatible = "ti,dra746-ehrpwm", | |
1964 | "ti,am3352-ehrpwm"; | |
1965 | #pwm-cells = <3>; | |
1966 | reg = <0x48442200 0x80>; | |
1967 | clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; | |
1968 | clock-names = "tbclk", "fck"; | |
1969 | status = "disabled"; | |
1970 | }; | |
1971 | ||
1972 | ecap2: ecap@48442100 { | |
1973 | compatible = "ti,dra746-ecap", | |
1974 | "ti,am3352-ecap"; | |
1975 | #pwm-cells = <3>; | |
1976 | reg = <0x48442100 0x80>; | |
1977 | clocks = <&l4_root_clk_div>; | |
1978 | clock-names = "fck"; | |
1979 | status = "disabled"; | |
1980 | }; | |
1981 | }; | |
1982 | ||
1983 | aes1: aes@4b500000 { | |
1984 | compatible = "ti,omap4-aes"; | |
1985 | ti,hwmods = "aes1"; | |
1986 | reg = <0x4b500000 0xa0>; | |
1987 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
1988 | dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; | |
1989 | dma-names = "tx", "rx"; | |
1990 | clocks = <&l3_iclk_div>; | |
1991 | clock-names = "fck"; | |
1992 | }; | |
1993 | ||
1994 | aes2: aes@4b700000 { | |
1995 | compatible = "ti,omap4-aes"; | |
1996 | ti,hwmods = "aes2"; | |
1997 | reg = <0x4b700000 0xa0>; | |
1998 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
1999 | dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; | |
2000 | dma-names = "tx", "rx"; | |
2001 | clocks = <&l3_iclk_div>; | |
2002 | clock-names = "fck"; | |
2003 | }; | |
2004 | ||
2005 | des: des@480a5000 { | |
2006 | compatible = "ti,omap4-des"; | |
2007 | ti,hwmods = "des"; | |
2008 | reg = <0x480a5000 0xa0>; | |
2009 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
2010 | dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; | |
2011 | dma-names = "tx", "rx"; | |
2012 | clocks = <&l3_iclk_div>; | |
2013 | clock-names = "fck"; | |
2014 | }; | |
2015 | ||
2016 | sham: sham@53100000 { | |
2017 | compatible = "ti,omap5-sham"; | |
2018 | ti,hwmods = "sham"; | |
2019 | reg = <0x4b101000 0x300>; | |
2020 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
2021 | dmas = <&edma_xbar 119 0>; | |
2022 | dma-names = "rx"; | |
2023 | clocks = <&l3_iclk_div>; | |
2024 | clock-names = "fck"; | |
2025 | }; | |
2026 | ||
2027 | rng: rng@48090000 { | |
2028 | compatible = "ti,omap4-rng"; | |
2029 | ti,hwmods = "rng"; | |
2030 | reg = <0x48090000 0x2000>; | |
2031 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
2032 | clocks = <&l3_iclk_div>; | |
2033 | clock-names = "fck"; | |
2034 | }; | |
57cd681b TR |
2035 | }; |
2036 | ||
2037 | thermal_zones: thermal-zones { | |
2038 | #include "omap4-cpu-thermal.dtsi" | |
2039 | #include "omap5-gpu-thermal.dtsi" | |
2040 | #include "omap5-core-thermal.dtsi" | |
7aa1a408 LV |
2041 | #include "dra7-dspeve-thermal.dtsi" |
2042 | #include "dra7-iva-thermal.dtsi" | |
57cd681b TR |
2043 | }; |
2044 | ||
2045 | }; | |
2046 | ||
2047 | &cpu_thermal { | |
2048 | polling-delay = <500>; /* milliseconds */ | |
4ddaa6ce LV |
2049 | coefficients = <0 2000>; |
2050 | }; | |
2051 | ||
2052 | &gpu_thermal { | |
2053 | coefficients = <0 2000>; | |
2054 | }; | |
2055 | ||
2056 | &core_thermal { | |
2057 | coefficients = <0 2000>; | |
2058 | }; | |
2059 | ||
2060 | &dspeve_thermal { | |
2061 | coefficients = <0 2000>; | |
2062 | }; | |
2063 | ||
2064 | &iva_thermal { | |
2065 | coefficients = <0 2000>; | |
2066 | }; | |
2067 | ||
2068 | &cpu_crit { | |
2069 | temperature = <120000>; /* milli Celsius */ | |
57cd681b TR |
2070 | }; |
2071 | ||
2072 | /include/ "dra7xx-clocks.dtsi" |