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dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl
[people/ms/u-boot.git] / arch / arm / dts / dra7.dtsi
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57cd681b
TR		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15#define MAX_SOURCES 400
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 compatible = "ti,dra7xx";
22 interrupt-parent = <&crossbar_mpu>;
23
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
53 };
54
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 reg = <0x48211000 0x1000>,
60 <0x48212000 0x1000>,
61 <0x48214000 0x2000>,
62 <0x48216000 0x2000>;
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
65 };
66
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
69 interrupt-controller;
70 #interrupt-cells = <3>;
71 reg = <0x48281000 0x1000>;
72 interrupt-parent = <&gic>;
73 };
74
75 /*
76 * The soc node represents the soc top level view. It is used for IPs
77 * that are not memory mapped in the MPU view or for the MPU itself.
78 */
79 soc {
80 compatible = "ti,omap-infra";
81 mpu {
82 compatible = "ti,omap5-mpu";
83 ti,hwmods = "mpu";
84 };
85 };
86
87 /*
88 * XXX: Use a flat representation of the SOC interconnect.
89 * The real OMAP interconnect network is quite complex.
90 * Since it will not bring real advantage to represent that in DT for
91 * the moment, just use a fake OCP bus entry to represent the whole bus
92 * hierarchy.
93 */
94 ocp {
95 compatible = "ti,dra7-l3-noc", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 ti,hwmods = "l3_main_1", "l3_main_2";
100 reg = <0x44000000 0x1000000>,
101 <0x45000000 0x1000>;
102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
104
105 l4_cfg: l4@4a000000 {
106 compatible = "ti,dra7-l4-cfg", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges = <0 0x4a000000 0x22c000>;
110
111 scm: scm@2000 {
112 compatible = "ti,dra7-scm-core", "simple-bus";
113 reg = <0x2000 0x2000>;
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0 0x2000 0x2000>;
117
118 scm_conf: scm_conf@0 {
119 compatible = "syscon";
120 reg = <0x0 0x1400>;
121 #address-cells = <1>;
122 #size-cells = <1>;
123
124 pbias_regulator: pbias_regulator {
125 compatible = "ti,pbias-omap";
126 reg = <0xe00 0x4>;
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap5 {
129 regulator-name = "pbias_mmc_omap5";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
132 };
133 };
134
135 scm_conf_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139 };
140
141 dra7_pmx_core: pinmux@1400 {
142 compatible = "ti,dra7-padconf",
143 "pinctrl-single";
144 reg = <0x1400 0x0464>;
145 #address-cells = <1>;
146 #size-cells = <0>;
147 #interrupt-cells = <1>;
148 interrupt-controller;
149 pinctrl-single,register-width = <32>;
150 pinctrl-single,function-mask = <0x3fffffff>;
151 };
152 };
153
154 cm_core_aon: cm_core_aon@5000 {
155 compatible = "ti,dra7-cm-core-aon";
156 reg = <0x5000 0x2000>;
157
158 cm_core_aon_clocks: clocks {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 cm_core_aon_clockdomains: clockdomains {
164 };
165 };
166
167 cm_core: cm_core@8000 {
168 compatible = "ti,dra7-cm-core";
169 reg = <0x8000 0x3000>;
170
171 cm_core_clocks: clocks {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 };
175
176 cm_core_clockdomains: clockdomains {
177 };
178 };
179 };
180
181 l4_wkup: l4@4ae00000 {
182 compatible = "ti,dra7-l4-wkup", "simple-bus";
183 #address-cells = <1>;
184 #size-cells = <1>;
185 ranges = <0 0x4ae00000 0x3f000>;
186
187 counter32k: counter@4000 {
188 compatible = "ti,omap-counter32k";
189 reg = <0x4000 0x40>;
190 ti,hwmods = "counter_32k";
191 };
192
193 prm: prm@6000 {
194 compatible = "ti,dra7-prm";
195 reg = <0x6000 0x3000>;
196 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
197
198 prm_clocks: clocks {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 };
202
203 prm_clockdomains: clockdomains {
204 };
205 };
206 };
207
208 axi@0 {
209 compatible = "simple-bus";
210 #size-cells = <1>;
211 #address-cells = <1>;
212 ranges = <0x51000000 0x51000000 0x3000
213 0x0 0x20000000 0x10000000>;
214 pcie@51000000 {
215 compatible = "ti,dra7-pcie";
216 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
217 reg-names = "rc_dbics", "ti_conf", "config";
218 interrupts = <0 232 0x4>, <0 233 0x4>;
219 #address-cells = <3>;
220 #size-cells = <2>;
221 device_type = "pci";
222 ranges = <0x81000000 0 0 0x03000 0 0x00010000
223 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
224 #interrupt-cells = <1>;
225 num-lanes = <1>;
226 ti,hwmods = "pcie1";
227 phys = <&pcie1_phy>;
228 phy-names = "pcie-phy0";
229 interrupt-map-mask = <0 0 0 7>;
230 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
231 <0 0 0 2 &pcie1_intc 2>,
232 <0 0 0 3 &pcie1_intc 3>,
233 <0 0 0 4 &pcie1_intc 4>;
234 pcie1_intc: interrupt-controller {
235 interrupt-controller;
236 #address-cells = <0>;
237 #interrupt-cells = <1>;
238 };
239 };
240 };
241
242 axi@1 {
243 compatible = "simple-bus";
244 #size-cells = <1>;
245 #address-cells = <1>;
246 ranges = <0x51800000 0x51800000 0x3000
247 0x0 0x30000000 0x10000000>;
248 status = "disabled";
249 pcie@51000000 {
250 compatible = "ti,dra7-pcie";
251 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
252 reg-names = "rc_dbics", "ti_conf", "config";
253 interrupts = <0 355 0x4>, <0 356 0x4>;
254 #address-cells = <3>;
255 #size-cells = <2>;
256 device_type = "pci";
257 ranges = <0x81000000 0 0 0x03000 0 0x00010000
258 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
259 #interrupt-cells = <1>;
260 num-lanes = <1>;
261 ti,hwmods = "pcie2";
262 phys = <&pcie2_phy>;
263 phy-names = "pcie-phy0";
264 interrupt-map-mask = <0 0 0 7>;
265 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
266 <0 0 0 2 &pcie2_intc 2>,
267 <0 0 0 3 &pcie2_intc 3>,
268 <0 0 0 4 &pcie2_intc 4>;
269 pcie2_intc: interrupt-controller {
270 interrupt-controller;
271 #address-cells = <0>;
272 #interrupt-cells = <1>;
273 };
274 };
275 };
276
277 bandgap: bandgap@4a0021e0 {
278 reg = <0x4a0021e0 0xc
279 0x4a00232c 0xc
280 0x4a002380 0x2c
281 0x4a0023C0 0x3c
282 0x4a002564 0x8
283 0x4a002574 0x50>;
284 compatible = "ti,dra752-bandgap";
285 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
286 #thermal-sensor-cells = <1>;
287 };
288
289 dra7_ctrl_core: ctrl_core@4a002000 {
290 compatible = "syscon";
291 reg = <0x4a002000 0x6d0>;
292 };
293
294 dra7_ctrl_general: tisyscon@4a002e00 {
295 compatible = "syscon";
296 reg = <0x4a002e00 0x7c>;
297 };
298
299 sdma: dma-controller@4a056000 {
300 compatible = "ti,omap4430-sdma";
301 reg = <0x4a056000 0x1000>;
302 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
306 #dma-cells = <1>;
307 dma-channels = <32>;
308 dma-requests = <127>;
309 };
310
311 gpio1: gpio@4ae10000 {
312 compatible = "ti,omap4-gpio";
313 reg = <0x4ae10000 0x200>;
314 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
315 ti,hwmods = "gpio1";
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 };
321
322 gpio2: gpio@48055000 {
323 compatible = "ti,omap4-gpio";
324 reg = <0x48055000 0x200>;
325 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
326 ti,hwmods = "gpio2";
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 gpio3: gpio@48057000 {
334 compatible = "ti,omap4-gpio";
335 reg = <0x48057000 0x200>;
336 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
337 ti,hwmods = "gpio3";
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343
344 gpio4: gpio@48059000 {
345 compatible = "ti,omap4-gpio";
346 reg = <0x48059000 0x200>;
347 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
348 ti,hwmods = "gpio4";
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 gpio5: gpio@4805b000 {
356 compatible = "ti,omap4-gpio";
357 reg = <0x4805b000 0x200>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "gpio5";
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
365
366 gpio6: gpio@4805d000 {
367 compatible = "ti,omap4-gpio";
368 reg = <0x4805d000 0x200>;
369 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
370 ti,hwmods = "gpio6";
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 };
376
377 gpio7: gpio@48051000 {
378 compatible = "ti,omap4-gpio";
379 reg = <0x48051000 0x200>;
380 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "gpio7";
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 };
387
388 gpio8: gpio@48053000 {
389 compatible = "ti,omap4-gpio";
390 reg = <0x48053000 0x200>;
391 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
392 ti,hwmods = "gpio8";
393 gpio-controller;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 };
398
399 uart1: serial@4806a000 {
400 compatible = "ti,omap4-uart";
401 reg = <0x4806a000 0x100>;
85cf0e62 402 reg-shift = <2>;
57cd681b
TR		 403 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
404 ti,hwmods = "uart1";
405 clock-frequency = <48000000>;
406 status = "disabled";
407 dmas = <&sdma 49>, <&sdma 50>;
408 dma-names = "tx", "rx";
409 };
410
411 uart2: serial@4806c000 {
412 compatible = "ti,omap4-uart";
413 reg = <0x4806c000 0x100>;
85cf0e62 414 reg-shift = <2>;
57cd681b
TR		 415 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "uart2";
417 clock-frequency = <48000000>;
418 status = "disabled";
419 dmas = <&sdma 51>, <&sdma 52>;
420 dma-names = "tx", "rx";
421 };
422
423 uart3: serial@48020000 {
424 compatible = "ti,omap4-uart";
425 reg = <0x48020000 0x100>;
85cf0e62 426 reg-shift = <2>;
57cd681b
TR		 427 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
428 ti,hwmods = "uart3";
429 clock-frequency = <48000000>;
430 status = "disabled";
431 dmas = <&sdma 53>, <&sdma 54>;
432 dma-names = "tx", "rx";
433 };
434
435 uart4: serial@4806e000 {
436 compatible = "ti,omap4-uart";
437 reg = <0x4806e000 0x100>;
85cf0e62 438 reg-shift = <2>;
57cd681b
TR		 439 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
440 ti,hwmods = "uart4";
441 clock-frequency = <48000000>;
442 status = "disabled";
443 dmas = <&sdma 55>, <&sdma 56>;
444 dma-names = "tx", "rx";
445 };
446
447 uart5: serial@48066000 {
448 compatible = "ti,omap4-uart";
449 reg = <0x48066000 0x100>;
85cf0e62 450 reg-shift = <2>;
57cd681b
TR		 451 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
452 ti,hwmods = "uart5";
453 clock-frequency = <48000000>;
454 status = "disabled";
455 dmas = <&sdma 63>, <&sdma 64>;
456 dma-names = "tx", "rx";
457 };
458
459 uart6: serial@48068000 {
460 compatible = "ti,omap4-uart";
461 reg = <0x48068000 0x100>;
85cf0e62 462 reg-shift = <2>;
57cd681b
TR		 463 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
464 ti,hwmods = "uart6";
465 clock-frequency = <48000000>;
466 status = "disabled";
467 dmas = <&sdma 79>, <&sdma 80>;
468 dma-names = "tx", "rx";
469 };
470
471 uart7: serial@48420000 {
472 compatible = "ti,omap4-uart";
473 reg = <0x48420000 0x100>;
85cf0e62 474 reg-shift = <2>;
57cd681b
TR		 475 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
476 ti,hwmods = "uart7";
477 clock-frequency = <48000000>;
478 status = "disabled";
479 };
480
481 uart8: serial@48422000 {
482 compatible = "ti,omap4-uart";
483 reg = <0x48422000 0x100>;
85cf0e62 484 reg-shift = <2>;
57cd681b
TR		 485 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
486 ti,hwmods = "uart8";
487 clock-frequency = <48000000>;
488 status = "disabled";
489 };
490
491 uart9: serial@48424000 {
492 compatible = "ti,omap4-uart";
493 reg = <0x48424000 0x100>;
85cf0e62 494 reg-shift = <2>;
57cd681b
TR		 495 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
496 ti,hwmods = "uart9";
497 clock-frequency = <48000000>;
498 status = "disabled";
499 };
500
501 uart10: serial@4ae2b000 {
502 compatible = "ti,omap4-uart";
503 reg = <0x4ae2b000 0x100>;
85cf0e62 504 reg-shift = <2>;
57cd681b
TR		 505 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
506 ti,hwmods = "uart10";
507 clock-frequency = <48000000>;
508 status = "disabled";
509 };
510
511 mailbox1: mailbox@4a0f4000 {
512 compatible = "ti,omap4-mailbox";
513 reg = <0x4a0f4000 0x200>;
514 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
517 ti,hwmods = "mailbox1";
518 #mbox-cells = <1>;
519 ti,mbox-num-users = <3>;
520 ti,mbox-num-fifos = <8>;
521 status = "disabled";
522 };
523
524 mailbox2: mailbox@4883a000 {
525 compatible = "ti,omap4-mailbox";
526 reg = <0x4883a000 0x200>;
527 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "mailbox2";
532 #mbox-cells = <1>;
533 ti,mbox-num-users = <4>;
534 ti,mbox-num-fifos = <12>;
535 status = "disabled";
536 };
537
538 mailbox3: mailbox@4883c000 {
539 compatible = "ti,omap4-mailbox";
540 reg = <0x4883c000 0x200>;
541 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
545 ti,hwmods = "mailbox3";
546 #mbox-cells = <1>;
547 ti,mbox-num-users = <4>;
548 ti,mbox-num-fifos = <12>;
549 status = "disabled";
550 };
551
552 mailbox4: mailbox@4883e000 {
553 compatible = "ti,omap4-mailbox";
554 reg = <0x4883e000 0x200>;
555 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
559 ti,hwmods = "mailbox4";
560 #mbox-cells = <1>;
561 ti,mbox-num-users = <4>;
562 ti,mbox-num-fifos = <12>;
563 status = "disabled";
564 };
565
566 mailbox5: mailbox@48840000 {
567 compatible = "ti,omap4-mailbox";
568 reg = <0x48840000 0x200>;
569 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
573 ti,hwmods = "mailbox5";
574 #mbox-cells = <1>;
575 ti,mbox-num-users = <4>;
576 ti,mbox-num-fifos = <12>;
577 status = "disabled";
578 };
579
580 mailbox6: mailbox@48842000 {
581 compatible = "ti,omap4-mailbox";
582 reg = <0x48842000 0x200>;
583 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
587 ti,hwmods = "mailbox6";
588 #mbox-cells = <1>;
589 ti,mbox-num-users = <4>;
590 ti,mbox-num-fifos = <12>;
591 status = "disabled";
592 };
593
594 mailbox7: mailbox@48844000 {
595 compatible = "ti,omap4-mailbox";
596 reg = <0x48844000 0x200>;
597 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
601 ti,hwmods = "mailbox7";
602 #mbox-cells = <1>;
603 ti,mbox-num-users = <4>;
604 ti,mbox-num-fifos = <12>;
605 status = "disabled";
606 };
607
608 mailbox8: mailbox@48846000 {
609 compatible = "ti,omap4-mailbox";
610 reg = <0x48846000 0x200>;
611 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
615 ti,hwmods = "mailbox8";
616 #mbox-cells = <1>;
617 ti,mbox-num-users = <4>;
618 ti,mbox-num-fifos = <12>;
619 status = "disabled";
620 };
621
622 mailbox9: mailbox@4885e000 {
623 compatible = "ti,omap4-mailbox";
624 reg = <0x4885e000 0x200>;
625 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
629 ti,hwmods = "mailbox9";
630 #mbox-cells = <1>;
631 ti,mbox-num-users = <4>;
632 ti,mbox-num-fifos = <12>;
633 status = "disabled";
634 };
635
636 mailbox10: mailbox@48860000 {
637 compatible = "ti,omap4-mailbox";
638 reg = <0x48860000 0x200>;
639 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
643 ti,hwmods = "mailbox10";
644 #mbox-cells = <1>;
645 ti,mbox-num-users = <4>;
646 ti,mbox-num-fifos = <12>;
647 status = "disabled";
648 };
649
650 mailbox11: mailbox@48862000 {
651 compatible = "ti,omap4-mailbox";
652 reg = <0x48862000 0x200>;
653 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
657 ti,hwmods = "mailbox11";
658 #mbox-cells = <1>;
659 ti,mbox-num-users = <4>;
660 ti,mbox-num-fifos = <12>;
661 status = "disabled";
662 };
663
664 mailbox12: mailbox@48864000 {
665 compatible = "ti,omap4-mailbox";
666 reg = <0x48864000 0x200>;
667 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
671 ti,hwmods = "mailbox12";
672 #mbox-cells = <1>;
673 ti,mbox-num-users = <4>;
674 ti,mbox-num-fifos = <12>;
675 status = "disabled";
676 };
677
678 mailbox13: mailbox@48802000 {
679 compatible = "ti,omap4-mailbox";
680 reg = <0x48802000 0x200>;
681 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
685 ti,hwmods = "mailbox13";
686 #mbox-cells = <1>;
687 ti,mbox-num-users = <4>;
688 ti,mbox-num-fifos = <12>;
689 status = "disabled";
690 };
691
692 timer1: timer@4ae18000 {
693 compatible = "ti,omap5430-timer";
694 reg = <0x4ae18000 0x80>;
695 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
696 ti,hwmods = "timer1";
697 ti,timer-alwon;
698 };
699
700 timer2: timer@48032000 {
701 compatible = "ti,omap5430-timer";
702 reg = <0x48032000 0x80>;
703 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
704 ti,hwmods = "timer2";
705 };
706
707 timer3: timer@48034000 {
708 compatible = "ti,omap5430-timer";
709 reg = <0x48034000 0x80>;
710 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
711 ti,hwmods = "timer3";
712 };
713
714 timer4: timer@48036000 {
715 compatible = "ti,omap5430-timer";
716 reg = <0x48036000 0x80>;
717 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
718 ti,hwmods = "timer4";
719 };
720
721 timer5: timer@48820000 {
722 compatible = "ti,omap5430-timer";
723 reg = <0x48820000 0x80>;
724 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
725 ti,hwmods = "timer5";
726 };
727
728 timer6: timer@48822000 {
729 compatible = "ti,omap5430-timer";
730 reg = <0x48822000 0x80>;
731 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
732 ti,hwmods = "timer6";
733 };
734
735 timer7: timer@48824000 {
736 compatible = "ti,omap5430-timer";
737 reg = <0x48824000 0x80>;
738 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
739 ti,hwmods = "timer7";
740 };
741
742 timer8: timer@48826000 {
743 compatible = "ti,omap5430-timer";
744 reg = <0x48826000 0x80>;
745 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
746 ti,hwmods = "timer8";
747 };
748
749 timer9: timer@4803e000 {
750 compatible = "ti,omap5430-timer";
751 reg = <0x4803e000 0x80>;
752 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
753 ti,hwmods = "timer9";
754 };
755
756 timer10: timer@48086000 {
757 compatible = "ti,omap5430-timer";
758 reg = <0x48086000 0x80>;
759 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
760 ti,hwmods = "timer10";
761 };
762
763 timer11: timer@48088000 {
764 compatible = "ti,omap5430-timer";
765 reg = <0x48088000 0x80>;
766 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
767 ti,hwmods = "timer11";
768 };
769
770 timer13: timer@48828000 {
771 compatible = "ti,omap5430-timer";
772 reg = <0x48828000 0x80>;
773 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
774 ti,hwmods = "timer13";
775 status = "disabled";
776 };
777
778 timer14: timer@4882a000 {
779 compatible = "ti,omap5430-timer";
780 reg = <0x4882a000 0x80>;
781 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
782 ti,hwmods = "timer14";
783 status = "disabled";
784 };
785
786 timer15: timer@4882c000 {
787 compatible = "ti,omap5430-timer";
788 reg = <0x4882c000 0x80>;
789 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
790 ti,hwmods = "timer15";
791 status = "disabled";
792 };
793
794 timer16: timer@4882e000 {
795 compatible = "ti,omap5430-timer";
796 reg = <0x4882e000 0x80>;
797 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
798 ti,hwmods = "timer16";
799 status = "disabled";
800 };
801
802 wdt2: wdt@4ae14000 {
803 compatible = "ti,omap3-wdt";
804 reg = <0x4ae14000 0x80>;
805 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
806 ti,hwmods = "wd_timer2";
807 };
808
809 hwspinlock: spinlock@4a0f6000 {
810 compatible = "ti,omap4-hwspinlock";
811 reg = <0x4a0f6000 0x1000>;
812 ti,hwmods = "spinlock";
813 #hwlock-cells = <1>;
814 };
815
816 dmm@4e000000 {
817 compatible = "ti,omap5-dmm";
818 reg = <0x4e000000 0x800>;
819 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
820 ti,hwmods = "dmm";
821 };
822
823 i2c1: i2c@48070000 {
824 compatible = "ti,omap4-i2c";
825 reg = <0x48070000 0x100>;
826 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
827 #address-cells = <1>;
828 #size-cells = <0>;
829 ti,hwmods = "i2c1";
830 status = "disabled";
831 };
832
833 i2c2: i2c@48072000 {
834 compatible = "ti,omap4-i2c";
835 reg = <0x48072000 0x100>;
836 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
837 #address-cells = <1>;
838 #size-cells = <0>;
839 ti,hwmods = "i2c2";
840 status = "disabled";
841 };
842
843 i2c3: i2c@48060000 {
844 compatible = "ti,omap4-i2c";
845 reg = <0x48060000 0x100>;
846 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
847 #address-cells = <1>;
848 #size-cells = <0>;
849 ti,hwmods = "i2c3";
850 status = "disabled";
851 };
852
853 i2c4: i2c@4807a000 {
854 compatible = "ti,omap4-i2c";
855 reg = <0x4807a000 0x100>;
856 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
857 #address-cells = <1>;
858 #size-cells = <0>;
859 ti,hwmods = "i2c4";
860 status = "disabled";
861 };
862
863 i2c5: i2c@4807c000 {
864 compatible = "ti,omap4-i2c";
865 reg = <0x4807c000 0x100>;
866 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
867 #address-cells = <1>;
868 #size-cells = <0>;
869 ti,hwmods = "i2c5";
870 status = "disabled";
871 };
872
873 mmc1: mmc@4809c000 {
874 compatible = "ti,omap4-hsmmc";
875 reg = <0x4809c000 0x400>;
876 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
877 ti,hwmods = "mmc1";
878 ti,dual-volt;
879 ti,needs-special-reset;
880 dmas = <&sdma 61>, <&sdma 62>;
881 dma-names = "tx", "rx";
882 status = "disabled";
883 pbias-supply = <&pbias_mmc_reg>;
884 };
885
886 mmc2: mmc@480b4000 {
887 compatible = "ti,omap4-hsmmc";
888 reg = <0x480b4000 0x400>;
889 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
890 ti,hwmods = "mmc2";
891 ti,needs-special-reset;
892 dmas = <&sdma 47>, <&sdma 48>;
893 dma-names = "tx", "rx";
894 status = "disabled";
895 };
896
897 mmc3: mmc@480ad000 {
898 compatible = "ti,omap4-hsmmc";
899 reg = <0x480ad000 0x400>;
900 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
901 ti,hwmods = "mmc3";
902 ti,needs-special-reset;
903 dmas = <&sdma 77>, <&sdma 78>;
904 dma-names = "tx", "rx";
905 status = "disabled";
906 };
907
908 mmc4: mmc@480d1000 {
909 compatible = "ti,omap4-hsmmc";
910 reg = <0x480d1000 0x400>;
911 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
912 ti,hwmods = "mmc4";
913 ti,needs-special-reset;
914 dmas = <&sdma 57>, <&sdma 58>;
915 dma-names = "tx", "rx";
916 status = "disabled";
917 };
918
919 abb_mpu: regulator-abb-mpu {
920 compatible = "ti,abb-v3";
921 regulator-name = "abb_mpu";
922 #address-cells = <0>;
923 #size-cells = <0>;
924 clocks = <&sys_clkin1>;
925 ti,settling-time = <50>;
926 ti,clock-cycles = <16>;
927
928 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
929 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
930 <0x4ae0c158 0x4>;
931 reg-names = "setup-address", "control-address",
932 "int-address", "efuse-address",
933 "ldo-address";
934 ti,tranxdone-status-mask = <0x80>;
935 /* LDOVBBMPU_FBB_MUX_CTRL */
936 ti,ldovbb-override-mask = <0x400>;
937 /* LDOVBBMPU_FBB_VSET_OUT */
938 ti,ldovbb-vset-mask = <0x1F>;
939
940 /*
941 * NOTE: only FBB mode used but actual vset will
942 * determine final biasing
943 */
944 ti,abb_info = <
945 /*uV ABB efuse rbb_m fbb_m vset_m*/
946 1060000 0 0x0 0 0x02000000 0x01F00000
947 1160000 0 0x4 0 0x02000000 0x01F00000
948 1210000 0 0x8 0 0x02000000 0x01F00000
949 >;
950 };
951
952 abb_ivahd: regulator-abb-ivahd {
953 compatible = "ti,abb-v3";
954 regulator-name = "abb_ivahd";
955 #address-cells = <0>;
956 #size-cells = <0>;
957 clocks = <&sys_clkin1>;
958 ti,settling-time = <50>;
959 ti,clock-cycles = <16>;
960
961 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
962 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
963 <0x4a002470 0x4>;
964 reg-names = "setup-address", "control-address",
965 "int-address", "efuse-address",
966 "ldo-address";
967 ti,tranxdone-status-mask = <0x40000000>;
968 /* LDOVBBIVA_FBB_MUX_CTRL */
969 ti,ldovbb-override-mask = <0x400>;
970 /* LDOVBBIVA_FBB_VSET_OUT */
971 ti,ldovbb-vset-mask = <0x1F>;
972
973 /*
974 * NOTE: only FBB mode used but actual vset will
975 * determine final biasing
976 */
977 ti,abb_info = <
978 /*uV ABB efuse rbb_m fbb_m vset_m*/
979 1055000 0 0x0 0 0x02000000 0x01F00000
980 1150000 0 0x4 0 0x02000000 0x01F00000
981 1250000 0 0x8 0 0x02000000 0x01F00000
982 >;
983 };
984
985 abb_dspeve: regulator-abb-dspeve {
986 compatible = "ti,abb-v3";
987 regulator-name = "abb_dspeve";
988 #address-cells = <0>;
989 #size-cells = <0>;
990 clocks = <&sys_clkin1>;
991 ti,settling-time = <50>;
992 ti,clock-cycles = <16>;
993
994 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
995 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
996 <0x4a00246c 0x4>;
997 reg-names = "setup-address", "control-address",
998 "int-address", "efuse-address",
999 "ldo-address";
1000 ti,tranxdone-status-mask = <0x20000000>;
1001 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1002 ti,ldovbb-override-mask = <0x400>;
1003 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1004 ti,ldovbb-vset-mask = <0x1F>;
1005
1006 /*
1007 * NOTE: only FBB mode used but actual vset will
1008 * determine final biasing
1009 */
1010 ti,abb_info = <
1011 /*uV ABB efuse rbb_m fbb_m vset_m*/
1012 1055000 0 0x0 0 0x02000000 0x01F00000
1013 1150000 0 0x4 0 0x02000000 0x01F00000
1014 1250000 0 0x8 0 0x02000000 0x01F00000
1015 >;
1016 };
1017
1018 abb_gpu: regulator-abb-gpu {
1019 compatible = "ti,abb-v3";
1020 regulator-name = "abb_gpu";
1021 #address-cells = <0>;
1022 #size-cells = <0>;
1023 clocks = <&sys_clkin1>;
1024 ti,settling-time = <50>;
1025 ti,clock-cycles = <16>;
1026
1027 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1028 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1029 <0x4ae0c154 0x4>;
1030 reg-names = "setup-address", "control-address",
1031 "int-address", "efuse-address",
1032 "ldo-address";
1033 ti,tranxdone-status-mask = <0x10000000>;
1034 /* LDOVBBGPU_FBB_MUX_CTRL */
1035 ti,ldovbb-override-mask = <0x400>;
1036 /* LDOVBBGPU_FBB_VSET_OUT */
1037 ti,ldovbb-vset-mask = <0x1F>;
1038
1039 /*
1040 * NOTE: only FBB mode used but actual vset will
1041 * determine final biasing
1042 */
1043 ti,abb_info = <
1044 /*uV ABB efuse rbb_m fbb_m vset_m*/
1045 1090000 0 0x0 0 0x02000000 0x01F00000
1046 1210000 0 0x4 0 0x02000000 0x01F00000
1047 1280000 0 0x8 0 0x02000000 0x01F00000
1048 >;
1049 };
1050
1051 mcspi1: spi@48098000 {
1052 compatible = "ti,omap4-mcspi";
1053 reg = <0x48098000 0x200>;
1054 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 ti,hwmods = "mcspi1";
1058 ti,spi-num-cs = <4>;
1059 dmas = <&sdma 35>,
1060 <&sdma 36>,
1061 <&sdma 37>,
1062 <&sdma 38>,
1063 <&sdma 39>,
1064 <&sdma 40>,
1065 <&sdma 41>,
1066 <&sdma 42>;
1067 dma-names = "tx0", "rx0", "tx1", "rx1",
1068 "tx2", "rx2", "tx3", "rx3";
1069 status = "disabled";
1070 };
1071
1072 mcspi2: spi@4809a000 {
1073 compatible = "ti,omap4-mcspi";
1074 reg = <0x4809a000 0x200>;
1075 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1078 ti,hwmods = "mcspi2";
1079 ti,spi-num-cs = <2>;
1080 dmas = <&sdma 43>,
1081 <&sdma 44>,
1082 <&sdma 45>,
1083 <&sdma 46>;
1084 dma-names = "tx0", "rx0", "tx1", "rx1";
1085 status = "disabled";
1086 };
1087
1088 mcspi3: spi@480b8000 {
1089 compatible = "ti,omap4-mcspi";
1090 reg = <0x480b8000 0x200>;
1091 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1094 ti,hwmods = "mcspi3";
1095 ti,spi-num-cs = <2>;
1096 dmas = <&sdma 15>, <&sdma 16>;
1097 dma-names = "tx0", "rx0";
1098 status = "disabled";
1099 };
1100
1101 mcspi4: spi@480ba000 {
1102 compatible = "ti,omap4-mcspi";
1103 reg = <0x480ba000 0x200>;
1104 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1107 ti,hwmods = "mcspi4";
1108 ti,spi-num-cs = <1>;
1109 dmas = <&sdma 70>, <&sdma 71>;
1110 dma-names = "tx0", "rx0";
1111 status = "disabled";
1112 };
1113
1114 qspi: qspi@4b300000 {
1115 compatible = "ti,dra7xxx-qspi";
1116 reg = <0x4b300000 0x100>;
1117 reg-names = "qspi_base";
1118 #address-cells = <1>;
1119 #size-cells = <0>;
1120 ti,hwmods = "qspi";
1121 clocks = <&qspi_gfclk_div>;
1122 clock-names = "fck";
1123 num-cs = <4>;
1124 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1125 status = "disabled";
1126 };
1127
1128 omap_control_sata: control-phy@4a002374 {
1129 compatible = "ti,control-phy-pipe3";
1130 reg = <0x4a002374 0x4>;
1131 reg-names = "power";
1132 clocks = <&sys_clkin1>;
1133 clock-names = "sysclk";
1134 };
1135
1136 /* OCP2SCP3 */
1137 ocp2scp@4a090000 {
1138 compatible = "ti,omap-ocp2scp";
1139 #address-cells = <1>;
1140 #size-cells = <1>;
1141 ranges;
1142 reg = <0x4a090000 0x20>;
1143 ti,hwmods = "ocp2scp3";
1144 sata_phy: phy@4A096000 {
1145 compatible = "ti,phy-pipe3-sata";
1146 reg = <0x4A096000 0x80>, /* phy_rx */
1147 <0x4A096400 0x64>, /* phy_tx */
1148 <0x4A096800 0x40>; /* pll_ctrl */
1149 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1150 ctrl-module = <&omap_control_sata>;
1151 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1152 clock-names = "sysclk", "refclk";
1153 #phy-cells = <0>;
1154 };
1155
1156 pcie1_phy: pciephy@4a094000 {
1157 compatible = "ti,phy-pipe3-pcie";
1158 reg = <0x4a094000 0x80>, /* phy_rx */
1159 <0x4a094400 0x64>; /* phy_tx */
1160 reg-names = "phy_rx", "phy_tx";
1161 ctrl-module = <&omap_control_pcie1phy>;
1162 clocks = <&dpll_pcie_ref_ck>,
1163 <&dpll_pcie_ref_m2ldo_ck>,
1164 <&optfclk_pciephy1_32khz>,
1165 <&optfclk_pciephy1_clk>,
1166 <&optfclk_pciephy1_div_clk>,
1167 <&optfclk_pciephy_div>;
1168 clock-names = "dpll_ref", "dpll_ref_m2",
1169 "wkupclk", "refclk",
1170 "div-clk", "phy-div";
1171 #phy-cells = <0>;
1172 };
1173
1174 pcie2_phy: pciephy@4a095000 {
1175 compatible = "ti,phy-pipe3-pcie";
1176 reg = <0x4a095000 0x80>, /* phy_rx */
1177 <0x4a095400 0x64>; /* phy_tx */
1178 reg-names = "phy_rx", "phy_tx";
1179 ctrl-module = <&omap_control_pcie2phy>;
1180 clocks = <&dpll_pcie_ref_ck>,
1181 <&dpll_pcie_ref_m2ldo_ck>,
1182 <&optfclk_pciephy2_32khz>,
1183 <&optfclk_pciephy2_clk>,
1184 <&optfclk_pciephy2_div_clk>,
1185 <&optfclk_pciephy_div>;
1186 clock-names = "dpll_ref", "dpll_ref_m2",
1187 "wkupclk", "refclk",
1188 "div-clk", "phy-div";
1189 #phy-cells = <0>;
1190 status = "disabled";
1191 };
1192 };
1193
1194 sata: sata@4a141100 {
1195 compatible = "snps,dwc-ahci";
1196 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1197 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1198 phys = <&sata_phy>;
1199 phy-names = "sata-phy";
1200 clocks = <&sata_ref_clk>;
1201 ti,hwmods = "sata";
1202 };
1203
1204 omap_control_pcie1phy: control-phy@0x4a003c40 {
1205 compatible = "ti,control-phy-pcie";
1206 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1207 reg-names = "power", "control_sma", "pcie_pcs";
1208 clocks = <&sys_clkin1>;
1209 clock-names = "sysclk";
1210 };
1211
1212 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1213 compatible = "ti,control-phy-pcie";
1214 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1215 reg-names = "power", "control_sma", "pcie_pcs";
1216 clocks = <&sys_clkin1>;
1217 clock-names = "sysclk";
1218 status = "disabled";
1219 };
1220
1221 rtc: rtc@48838000 {
1222 compatible = "ti,am3352-rtc";
1223 reg = <0x48838000 0x100>;
1224 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1226 ti,hwmods = "rtcss";
1227 clocks = <&sys_32k_ck>;
1228 };
1229
1230 omap_control_usb2phy1: control-phy@4a002300 {
1231 compatible = "ti,control-phy-usb2";
1232 reg = <0x4a002300 0x4>;
1233 reg-names = "power";
1234 };
1235
1236 omap_control_usb3phy1: control-phy@4a002370 {
1237 compatible = "ti,control-phy-pipe3";
1238 reg = <0x4a002370 0x4>;
1239 reg-names = "power";
1240 };
1241
1242 omap_control_usb2phy2: control-phy@0x4a002e74 {
1243 compatible = "ti,control-phy-usb2-dra7";
1244 reg = <0x4a002e74 0x4>;
1245 reg-names = "power";
1246 };
1247
1248 /* OCP2SCP1 */
1249 ocp2scp@4a080000 {
1250 compatible = "ti,omap-ocp2scp";
1251 #address-cells = <1>;
1252 #size-cells = <1>;
1253 ranges;
1254 reg = <0x4a080000 0x20>;
1255 ti,hwmods = "ocp2scp1";
1256
1257 usb2_phy1: phy@4a084000 {
1258 compatible = "ti,omap-usb2";
1259 reg = <0x4a084000 0x400>;
1260 ctrl-module = <&omap_control_usb2phy1>;
1261 clocks = <&usb_phy1_always_on_clk32k>,
1262 <&usb_otg_ss1_refclk960m>;
1263 clock-names = "wkupclk",
1264 "refclk";
1265 #phy-cells = <0>;
1266 };
1267
1268 usb2_phy2: phy@4a085000 {
1269 compatible = "ti,omap-usb2";
1270 reg = <0x4a085000 0x400>;
1271 ctrl-module = <&omap_control_usb2phy2>;
1272 clocks = <&usb_phy2_always_on_clk32k>,
1273 <&usb_otg_ss2_refclk960m>;
1274 clock-names = "wkupclk",
1275 "refclk";
1276 #phy-cells = <0>;
1277 };
1278
1279 usb3_phy1: phy@4a084400 {
1280 compatible = "ti,omap-usb3";
1281 reg = <0x4a084400 0x80>,
1282 <0x4a084800 0x64>,
1283 <0x4a084c00 0x40>;
1284 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1285 ctrl-module = <&omap_control_usb3phy1>;
1286 clocks = <&usb_phy3_always_on_clk32k>,
1287 <&sys_clkin1>,
1288 <&usb_otg_ss1_refclk960m>;
1289 clock-names = "wkupclk",
1290 "sysclk",
1291 "refclk";
1292 #phy-cells = <0>;
1293 };
1294 };
1295
1296 omap_dwc3_1: omap_dwc3_1@48880000 {
1297 compatible = "ti,dwc3";
1298 ti,hwmods = "usb_otg_ss1";
1299 reg = <0x48880000 0x10000>;
1300 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1301 #address-cells = <1>;
1302 #size-cells = <1>;
1303 utmi-mode = <2>;
1304 ranges;
1305 usb1: usb@48890000 {
1306 compatible = "snps,dwc3";
1307 reg = <0x48890000 0x17000>;
1308 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1309 phys = <&usb2_phy1>, <&usb3_phy1>;
1310 phy-names = "usb2-phy", "usb3-phy";
1311 tx-fifo-resize;
1312 maximum-speed = "super-speed";
1313 dr_mode = "otg";
1314 snps,dis_u3_susphy_quirk;
1315 snps,dis_u2_susphy_quirk;
1316 };
1317 };
1318
1319 omap_dwc3_2: omap_dwc3_2@488c0000 {
1320 compatible = "ti,dwc3";
1321 ti,hwmods = "usb_otg_ss2";
1322 reg = <0x488c0000 0x10000>;
1323 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1324 #address-cells = <1>;
1325 #size-cells = <1>;
1326 utmi-mode = <2>;
1327 ranges;
1328 usb2: usb@488d0000 {
1329 compatible = "snps,dwc3";
1330 reg = <0x488d0000 0x17000>;
1331 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1332 phys = <&usb2_phy2>;
1333 phy-names = "usb2-phy";
1334 tx-fifo-resize;
1335 maximum-speed = "high-speed";
1336 dr_mode = "otg";
1337 snps,dis_u3_susphy_quirk;
1338 snps,dis_u2_susphy_quirk;
1339 };
1340 };
1341
1342 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1343 omap_dwc3_3: omap_dwc3_3@48900000 {
1344 compatible = "ti,dwc3";
1345 ti,hwmods = "usb_otg_ss3";
1346 reg = <0x48900000 0x10000>;
1347 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cells = <1>;
1349 #size-cells = <1>;
1350 utmi-mode = <2>;
1351 ranges;
1352 status = "disabled";
1353 usb3: usb@48910000 {
1354 compatible = "snps,dwc3";
1355 reg = <0x48910000 0x17000>;
1356 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1357 tx-fifo-resize;
1358 maximum-speed = "high-speed";
1359 dr_mode = "otg";
1360 snps,dis_u3_susphy_quirk;
1361 snps,dis_u2_susphy_quirk;
1362 };
1363 };
1364
1365 elm: elm@48078000 {
1366 compatible = "ti,am3352-elm";
1367 reg = <0x48078000 0xfc0>; /* device IO registers */
1368 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1369 ti,hwmods = "elm";
1370 status = "disabled";
1371 };
1372
1373 gpmc: gpmc@50000000 {
1374 compatible = "ti,am3352-gpmc";
1375 ti,hwmods = "gpmc";
1376 reg = <0x50000000 0x37c>; /* device IO registers */
1377 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1378 gpmc,num-cs = <8>;
1379 gpmc,num-waitpins = <2>;
1380 #address-cells = <2>;
1381 #size-cells = <1>;
1382 status = "disabled";
1383 };
1384
1385 atl: atl@4843c000 {
1386 compatible = "ti,dra7-atl";
1387 reg = <0x4843c000 0x3ff>;
1388 ti,hwmods = "atl";
1389 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1390 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1391 clocks = <&atl_gfclk_mux>;
1392 clock-names = "fck";
1393 status = "disabled";
1394 };
1395
1396 crossbar_mpu: crossbar@4a002a48 {
1397 compatible = "ti,irq-crossbar";
1398 reg = <0x4a002a48 0x130>;
1399 interrupt-controller;
1400 interrupt-parent = <&wakeupgen>;
1401 #interrupt-cells = <3>;
1402 ti,max-irqs = <160>;
1403 ti,max-crossbar-sources = <MAX_SOURCES>;
1404 ti,reg-size = <2>;
1405 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1406 ti,irqs-skip = <10 133 139 140>;
1407 ti,irqs-safe-map = <0>;
1408 };
1409
1410 mac: ethernet@4a100000 {
1411 compatible = "ti,cpsw";
1412 ti,hwmods = "gmac";
1413 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1414 clock-names = "fck", "cpts";
1415 cpdma_channels = <8>;
1416 ale_entries = <1024>;
1417 bd_ram_size = <0x2000>;
1418 no_bd_ram = <0>;
1419 rx_descs = <64>;
1420 mac_control = <0x20>;
1421 slaves = <2>;
1422 active_slave = <0>;
1423 cpts_clock_mult = <0x80000000>;
1424 cpts_clock_shift = <29>;
1425 reg = <0x48484000 0x1000
1426 0x48485200 0x2E00>;
1427 #address-cells = <1>;
1428 #size-cells = <1>;
1429 /*
1430 * rx_thresh_pend
1431 * rx_pend
1432 * tx_pend
1433 * misc_pend
1434 */
1435 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1439 ranges;
1440 status = "disabled";
1441
1442 davinci_mdio: mdio@48485000 {
1443 compatible = "ti,davinci_mdio";
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1446 ti,hwmods = "davinci_mdio";
1447 bus_freq = <1000000>;
1448 reg = <0x48485000 0x100>;
1449 };
1450
1451 cpsw_emac0: slave@48480200 {
1452 /* Filled in by U-Boot */
1453 mac-address = [ 00 00 00 00 00 00 ];
1454 };
1455
1456 cpsw_emac1: slave@48480300 {
1457 /* Filled in by U-Boot */
1458 mac-address = [ 00 00 00 00 00 00 ];
1459 };
1460
1461 phy_sel: cpsw-phy-sel@4a002554 {
1462 compatible = "ti,dra7xx-cpsw-phy-sel";
1463 reg= <0x4a002554 0x4>;
1464 reg-names = "gmii-sel";
1465 };
1466 };
1467
1468 dcan1: can@481cc000 {
1469 compatible = "ti,dra7-d_can";
1470 ti,hwmods = "dcan1";
1471 reg = <0x4ae3c000 0x2000>;
1472 syscon-raminit = <&scm_conf 0x558 0>;
1473 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&dcan1_sys_clk_mux>;
1475 status = "disabled";
1476 };
1477
1478 dcan2: can@481d0000 {
1479 compatible = "ti,dra7-d_can";
1480 ti,hwmods = "dcan2";
1481 reg = <0x48480000 0x2000>;
1482 syscon-raminit = <&scm_conf 0x558 1>;
1483 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&sys_clkin1>;
1485 status = "disabled";
1486 };
1487
1488 dss: dss@58000000 {
1489 compatible = "ti,dra7-dss";
1490 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1491 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1492 status = "disabled";
1493 ti,hwmods = "dss_core";
1494 /* CTRL_CORE_DSS_PLL_CONTROL */
1495 syscon-pll-ctrl = <&scm_conf 0x538>;
1496 #address-cells = <1>;
1497 #size-cells = <1>;
1498 ranges;
1499
1500 dispc@58001000 {
1501 compatible = "ti,dra7-dispc";
1502 reg = <0x58001000 0x1000>;
1503 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1504 ti,hwmods = "dss_dispc";
1505 clocks = <&dss_dss_clk>;
1506 clock-names = "fck";
1507 /* CTRL_CORE_SMA_SW_1 */
1508 syscon-pol = <&scm_conf 0x534>;
1509 };
1510
1511 hdmi: encoder@58060000 {
1512 compatible = "ti,dra7-hdmi";
1513 reg = <0x58040000 0x200>,
1514 <0x58040200 0x80>,
1515 <0x58040300 0x80>,
1516 <0x58060000 0x19000>;
1517 reg-names = "wp", "pll", "phy", "core";
1518 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1519 status = "disabled";
1520 ti,hwmods = "dss_hdmi";
1521 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1522 clock-names = "fck", "sys_clk";
1523 };
1524 };
1525 };
1526
1527 thermal_zones: thermal-zones {
1528 #include "omap4-cpu-thermal.dtsi"
1529 #include "omap5-gpu-thermal.dtsi"
1530 #include "omap5-core-thermal.dtsi"
1531 };
1532
1533};
1534
1535&cpu_thermal {
1536 polling-delay = <500>; /* milliseconds */
1537};
1538
1539/include/ "dra7xx-clocks.dtsi"
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