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Merge git://git.denx.de/u-boot-sunxi
[people/ms/u-boot.git] / arch / arm / dts / imx6qdl.dtsi
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39f41da3
JT		 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/clock/imx6qdl-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16#include "skeleton.dtsi"
17
18/ {
19 aliases {
20 ethernet0 = &fec;
21 can0 = &can1;
22 can1 = &can2;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 ipu0 = &ipu1;
34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
36 mmc2 = &usdhc3;
37 mmc3 = &usdhc4;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 spi0 = &ecspi1;
44 spi1 = &ecspi2;
45 spi2 = &ecspi3;
46 spi3 = &ecspi4;
47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
49 };
50
51 clocks {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 ckil {
56 compatible = "fsl,imx-ckil", "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <32768>;
59 };
60
61 ckih1 {
62 compatible = "fsl,imx-ckih1", "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
65 };
66
67 osc {
68 compatible = "fsl,imx-osc", "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <24000000>;
71 };
72 };
73
74 soc {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "simple-bus";
78 interrupt-parent = <&gpc>;
79 ranges;
1f6e9bd2 80 u-boot,dm-spl;
39f41da3
JT		 81
82 dma_apbh: dma-apbh@00110000 {
83 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
84 reg = <0x00110000 0x2000>;
85 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
86 <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 <0 13 IRQ_TYPE_LEVEL_HIGH>,
88 <0 13 IRQ_TYPE_LEVEL_HIGH>;
89 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
90 #dma-cells = <1>;
91 dma-channels = <4>;
92 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
93 };
94
95 gpmi: gpmi-nand@00112000 {
96 compatible = "fsl,imx6q-gpmi-nand";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
100 reg-names = "gpmi-nand", "bch";
101 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "bch";
103 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
104 <&clks IMX6QDL_CLK_GPMI_APB>,
105 <&clks IMX6QDL_CLK_GPMI_BCH>,
106 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
107 <&clks IMX6QDL_CLK_PER1_BCH>;
108 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
109 "gpmi_bch_apb", "per1_bch";
110 dmas = <&dma_apbh 0>;
111 dma-names = "rx-tx";
112 status = "disabled";
113 };
114
115 hdmi: hdmi@0120000 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 reg = <0x00120000 0x9000>;
119 interrupts = <0 115 0x04>;
120 gpr = <&gpr>;
121 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
122 <&clks IMX6QDL_CLK_HDMI_ISFR>;
123 clock-names = "iahb", "isfr";
124 status = "disabled";
125
126 port@0 {
127 reg = <0>;
128
129 hdmi_mux_0: endpoint {
130 remote-endpoint = <&ipu1_di0_hdmi>;
131 };
132 };
133
134 port@1 {
135 reg = <1>;
136
137 hdmi_mux_1: endpoint {
138 remote-endpoint = <&ipu1_di1_hdmi>;
139 };
140 };
141 };
142
143 gpu_3d: gpu@00130000 {
144 compatible = "vivante,gc";
145 reg = <0x00130000 0x4000>;
146 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
148 <&clks IMX6QDL_CLK_GPU3D_CORE>,
149 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
150 clock-names = "bus", "core", "shader";
151 power-domains = <&gpc 1>;
152 };
153
154 gpu_2d: gpu@00134000 {
155 compatible = "vivante,gc";
156 reg = <0x00134000 0x4000>;
157 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
159 <&clks IMX6QDL_CLK_GPU2D_CORE>;
160 clock-names = "bus", "core";
161 power-domains = <&gpc 1>;
162 };
163
164 timer@00a00600 {
165 compatible = "arm,cortex-a9-twd-timer";
166 reg = <0x00a00600 0x20>;
167 interrupts = <1 13 0xf01>;
168 interrupt-parent = <&intc>;
169 clocks = <&clks IMX6QDL_CLK_TWD>;
170 };
171
172 intc: interrupt-controller@00a01000 {
173 compatible = "arm,cortex-a9-gic";
174 #interrupt-cells = <3>;
175 interrupt-controller;
176 reg = <0x00a01000 0x1000>,
177 <0x00a00100 0x100>;
178 interrupt-parent = <&intc>;
179 };
180
181 L2: l2-cache@00a02000 {
182 compatible = "arm,pl310-cache";
183 reg = <0x00a02000 0x1000>;
184 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
185 cache-unified;
186 cache-level = <2>;
187 arm,tag-latency = <4 2 3>;
188 arm,data-latency = <4 2 3>;
189 arm,shared-override;
190 };
191
192 pcie: pcie@0x01000000 {
193 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
194 reg = <0x01ffc000 0x04000>,
195 <0x01f00000 0x80000>;
196 reg-names = "dbi", "config";
197 #address-cells = <3>;
198 #size-cells = <2>;
199 device_type = "pci";
200 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
201 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
202 num-lanes = <1>;
203 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
204 interrupt-names = "msi";
205 #interrupt-cells = <1>;
206 interrupt-map-mask = <0 0 0 0x7>;
207 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
208 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
209 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
210 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
212 <&clks IMX6QDL_CLK_LVDS1_GATE>,
213 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
214 clock-names = "pcie", "pcie_bus", "pcie_phy";
215 status = "disabled";
216 };
217
218 pmu {
219 compatible = "arm,cortex-a9-pmu";
220 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
221 };
222
223 aips-bus@02000000 { /* AIPS1 */
224 compatible = "fsl,aips-bus", "simple-bus";
225 #address-cells = <1>;
226 #size-cells = <1>;
227 reg = <0x02000000 0x100000>;
228 ranges;
1f6e9bd2 229 u-boot,dm-spl;
39f41da3
JT		 230
231 spba-bus@02000000 {
232 compatible = "fsl,spba-bus", "simple-bus";
233 #address-cells = <1>;
234 #size-cells = <1>;
235 reg = <0x02000000 0x40000>;
236 ranges;
237
238 spdif: spdif@02004000 {
239 compatible = "fsl,imx35-spdif";
240 reg = <0x02004000 0x4000>;
241 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
242 dmas = <&sdma 14 18 0>,
243 <&sdma 15 18 0>;
244 dma-names = "rx", "tx";
245 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
246 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
247 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
248 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
249 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
250 clock-names = "core", "rxtx0",
251 "rxtx1", "rxtx2",
252 "rxtx3", "rxtx4",
253 "rxtx5", "rxtx6",
254 "rxtx7", "spba";
255 status = "disabled";
256 };
257
258 ecspi1: ecspi@02008000 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
262 reg = <0x02008000 0x4000>;
263 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
265 <&clks IMX6QDL_CLK_ECSPI1>;
266 clock-names = "ipg", "per";
267 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
268 dma-names = "rx", "tx";
269 status = "disabled";
270 };
271
272 ecspi2: ecspi@0200c000 {
273 #address-cells = <1>;
274 #size-cells = <0>;
275 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
276 reg = <0x0200c000 0x4000>;
277 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
279 <&clks IMX6QDL_CLK_ECSPI2>;
280 clock-names = "ipg", "per";
281 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
282 dma-names = "rx", "tx";
283 status = "disabled";
284 };
285
286 ecspi3: ecspi@02010000 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
290 reg = <0x02010000 0x4000>;
291 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
293 <&clks IMX6QDL_CLK_ECSPI3>;
294 clock-names = "ipg", "per";
295 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
296 dma-names = "rx", "tx";
297 status = "disabled";
298 };
299
300 ecspi4: ecspi@02014000 {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
304 reg = <0x02014000 0x4000>;
305 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
307 <&clks IMX6QDL_CLK_ECSPI4>;
308 clock-names = "ipg", "per";
309 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
310 dma-names = "rx", "tx";
311 status = "disabled";
312 };
313
314 uart1: serial@02020000 {
315 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
316 reg = <0x02020000 0x4000>;
317 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
319 <&clks IMX6QDL_CLK_UART_SERIAL>;
320 clock-names = "ipg", "per";
321 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
322 dma-names = "rx", "tx";
323 status = "disabled";
324 };
325
326 esai: esai@02024000 {
327 #sound-dai-cells = <0>;
328 compatible = "fsl,imx35-esai";
329 reg = <0x02024000 0x4000>;
330 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
332 <&clks IMX6QDL_CLK_ESAI_MEM>,
333 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
334 <&clks IMX6QDL_CLK_ESAI_IPG>,
335 <&clks IMX6QDL_CLK_SPBA>;
336 clock-names = "core", "mem", "extal", "fsys", "spba";
337 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
338 dma-names = "rx", "tx";
339 status = "disabled";
340 };
341
342 ssi1: ssi@02028000 {
343 #sound-dai-cells = <0>;
344 compatible = "fsl,imx6q-ssi",
345 "fsl,imx51-ssi";
346 reg = <0x02028000 0x4000>;
347 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
349 <&clks IMX6QDL_CLK_SSI1>;
350 clock-names = "ipg", "baud";
351 dmas = <&sdma 37 1 0>,
352 <&sdma 38 1 0>;
353 dma-names = "rx", "tx";
354 fsl,fifo-depth = <15>;
355 status = "disabled";
356 };
357
358 ssi2: ssi@0202c000 {
359 #sound-dai-cells = <0>;
360 compatible = "fsl,imx6q-ssi",
361 "fsl,imx51-ssi";
362 reg = <0x0202c000 0x4000>;
363 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
365 <&clks IMX6QDL_CLK_SSI2>;
366 clock-names = "ipg", "baud";
367 dmas = <&sdma 41 1 0>,
368 <&sdma 42 1 0>;
369 dma-names = "rx", "tx";
370 fsl,fifo-depth = <15>;
371 status = "disabled";
372 };
373
374 ssi3: ssi@02030000 {
375 #sound-dai-cells = <0>;
376 compatible = "fsl,imx6q-ssi",
377 "fsl,imx51-ssi";
378 reg = <0x02030000 0x4000>;
379 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
381 <&clks IMX6QDL_CLK_SSI3>;
382 clock-names = "ipg", "baud";
383 dmas = <&sdma 45 1 0>,
384 <&sdma 46 1 0>;
385 dma-names = "rx", "tx";
386 fsl,fifo-depth = <15>;
387 status = "disabled";
388 };
389
390 asrc: asrc@02034000 {
391 compatible = "fsl,imx53-asrc";
392 reg = <0x02034000 0x4000>;
393 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
395 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
396 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
397 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
398 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
399 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
400 <&clks IMX6QDL_CLK_SPBA>;
401 clock-names = "mem", "ipg", "asrck_0",
402 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
403 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
404 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
405 "asrck_d", "asrck_e", "asrck_f", "spba";
406 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
407 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
408 dma-names = "rxa", "rxb", "rxc",
409 "txa", "txb", "txc";
410 fsl,asrc-rate = <48000>;
411 fsl,asrc-width = <16>;
412 status = "okay";
413 };
414
415 spba@0203c000 {
416 reg = <0x0203c000 0x4000>;
417 };
418 };
419
420 vpu: vpu@02040000 {
421 compatible = "cnm,coda960";
422 reg = <0x02040000 0x3c000>;
423 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
424 <0 3 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "bit", "jpeg";
426 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
427 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
428 clock-names = "per", "ahb";
429 power-domains = <&gpc 1>;
430 resets = <&src 1>;
431 iram = <&ocram>;
432 };
433
434 aipstz@0207c000 { /* AIPSTZ1 */
435 reg = <0x0207c000 0x4000>;
436 };
437
438 pwm1: pwm@02080000 {
439 #pwm-cells = <2>;
440 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
441 reg = <0x02080000 0x4000>;
442 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX6QDL_CLK_IPG>,
444 <&clks IMX6QDL_CLK_PWM1>;
445 clock-names = "ipg", "per";
446 status = "disabled";
447 };
448
449 pwm2: pwm@02084000 {
450 #pwm-cells = <2>;
451 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
452 reg = <0x02084000 0x4000>;
453 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&clks IMX6QDL_CLK_IPG>,
455 <&clks IMX6QDL_CLK_PWM2>;
456 clock-names = "ipg", "per";
457 status = "disabled";
458 };
459
460 pwm3: pwm@02088000 {
461 #pwm-cells = <2>;
462 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
463 reg = <0x02088000 0x4000>;
464 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clks IMX6QDL_CLK_IPG>,
466 <&clks IMX6QDL_CLK_PWM3>;
467 clock-names = "ipg", "per";
468 status = "disabled";
469 };
470
471 pwm4: pwm@0208c000 {
472 #pwm-cells = <2>;
473 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
474 reg = <0x0208c000 0x4000>;
475 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clks IMX6QDL_CLK_IPG>,
477 <&clks IMX6QDL_CLK_PWM4>;
478 clock-names = "ipg", "per";
479 status = "disabled";
480 };
481
482 can1: flexcan@02090000 {
483 compatible = "fsl,imx6q-flexcan";
484 reg = <0x02090000 0x4000>;
485 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
487 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
488 clock-names = "ipg", "per";
489 status = "disabled";
490 };
491
492 can2: flexcan@02094000 {
493 compatible = "fsl,imx6q-flexcan";
494 reg = <0x02094000 0x4000>;
495 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
497 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
498 clock-names = "ipg", "per";
499 status = "disabled";
500 };
501
502 gpt: gpt@02098000 {
503 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
504 reg = <0x02098000 0x4000>;
505 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
507 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
508 <&clks IMX6QDL_CLK_GPT_3M>;
509 clock-names = "ipg", "per", "osc_per";
510 };
511
512 gpio1: gpio@0209c000 {
513 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
514 reg = <0x0209c000 0x4000>;
515 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
516 <0 67 IRQ_TYPE_LEVEL_HIGH>;
517 gpio-controller;
518 #gpio-cells = <2>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
1f6e9bd2 521 u-boot,dm-spl;
39f41da3
JT		 522 };
523
524 gpio2: gpio@020a0000 {
525 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
526 reg = <0x020a0000 0x4000>;
527 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
528 <0 69 IRQ_TYPE_LEVEL_HIGH>;
529 gpio-controller;
530 #gpio-cells = <2>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 };
534
535 gpio3: gpio@020a4000 {
536 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
537 reg = <0x020a4000 0x4000>;
538 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
539 <0 71 IRQ_TYPE_LEVEL_HIGH>;
540 gpio-controller;
541 #gpio-cells = <2>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
544 };
545
546 gpio4: gpio@020a8000 {
547 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
548 reg = <0x020a8000 0x4000>;
549 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
550 <0 73 IRQ_TYPE_LEVEL_HIGH>;
551 gpio-controller;
552 #gpio-cells = <2>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 };
556
557 gpio5: gpio@020ac000 {
558 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
559 reg = <0x020ac000 0x4000>;
560 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
561 <0 75 IRQ_TYPE_LEVEL_HIGH>;
562 gpio-controller;
563 #gpio-cells = <2>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 };
567
568 gpio6: gpio@020b0000 {
569 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
570 reg = <0x020b0000 0x4000>;
571 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
572 <0 77 IRQ_TYPE_LEVEL_HIGH>;
573 gpio-controller;
574 #gpio-cells = <2>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 };
578
579 gpio7: gpio@020b4000 {
580 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
581 reg = <0x020b4000 0x4000>;
582 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
583 <0 79 IRQ_TYPE_LEVEL_HIGH>;
584 gpio-controller;
585 #gpio-cells = <2>;
586 interrupt-controller;
587 #interrupt-cells = <2>;
588 };
589
590 kpp: kpp@020b8000 {
591 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
592 reg = <0x020b8000 0x4000>;
593 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clks IMX6QDL_CLK_IPG>;
595 status = "disabled";
596 };
597
598 wdog1: wdog@020bc000 {
599 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
600 reg = <0x020bc000 0x4000>;
601 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clks IMX6QDL_CLK_DUMMY>;
603 };
604
605 wdog2: wdog@020c0000 {
606 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
607 reg = <0x020c0000 0x4000>;
608 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&clks IMX6QDL_CLK_DUMMY>;
610 status = "disabled";
611 };
612
613 clks: ccm@020c4000 {
614 compatible = "fsl,imx6q-ccm";
615 reg = <0x020c4000 0x4000>;
616 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
617 <0 88 IRQ_TYPE_LEVEL_HIGH>;
618 #clock-cells = <1>;
619 };
620
621 anatop: anatop@020c8000 {
622 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
623 reg = <0x020c8000 0x1000>;
624 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
625 <0 54 IRQ_TYPE_LEVEL_HIGH>,
626 <0 127 IRQ_TYPE_LEVEL_HIGH>;
627
628 regulator-1p1 {
629 compatible = "fsl,anatop-regulator";
630 regulator-name = "vdd1p1";
631 regulator-min-microvolt = <800000>;
632 regulator-max-microvolt = <1375000>;
633 regulator-always-on;
634 anatop-reg-offset = <0x110>;
635 anatop-vol-bit-shift = <8>;
636 anatop-vol-bit-width = <5>;
637 anatop-min-bit-val = <4>;
638 anatop-min-voltage = <800000>;
639 anatop-max-voltage = <1375000>;
640 };
641
642 regulator-3p0 {
643 compatible = "fsl,anatop-regulator";
644 regulator-name = "vdd3p0";
645 regulator-min-microvolt = <2800000>;
646 regulator-max-microvolt = <3150000>;
647 regulator-always-on;
648 anatop-reg-offset = <0x120>;
649 anatop-vol-bit-shift = <8>;
650 anatop-vol-bit-width = <5>;
651 anatop-min-bit-val = <0>;
652 anatop-min-voltage = <2625000>;
653 anatop-max-voltage = <3400000>;
654 };
655
656 regulator-2p5 {
657 compatible = "fsl,anatop-regulator";
658 regulator-name = "vdd2p5";
659 regulator-min-microvolt = <2000000>;
660 regulator-max-microvolt = <2750000>;
661 regulator-always-on;
662 anatop-reg-offset = <0x130>;
663 anatop-vol-bit-shift = <8>;
664 anatop-vol-bit-width = <5>;
665 anatop-min-bit-val = <0>;
666 anatop-min-voltage = <2000000>;
667 anatop-max-voltage = <2750000>;
668 };
669
670 reg_arm: regulator-vddcore {
671 compatible = "fsl,anatop-regulator";
672 regulator-name = "vddarm";
673 regulator-min-microvolt = <725000>;
674 regulator-max-microvolt = <1450000>;
675 regulator-always-on;
676 anatop-reg-offset = <0x140>;
677 anatop-vol-bit-shift = <0>;
678 anatop-vol-bit-width = <5>;
679 anatop-delay-reg-offset = <0x170>;
680 anatop-delay-bit-shift = <24>;
681 anatop-delay-bit-width = <2>;
682 anatop-min-bit-val = <1>;
683 anatop-min-voltage = <725000>;
684 anatop-max-voltage = <1450000>;
685 };
686
687 reg_pu: regulator-vddpu {
688 compatible = "fsl,anatop-regulator";
689 regulator-name = "vddpu";
690 regulator-min-microvolt = <725000>;
691 regulator-max-microvolt = <1450000>;
692 regulator-enable-ramp-delay = <150>;
693 anatop-reg-offset = <0x140>;
694 anatop-vol-bit-shift = <9>;
695 anatop-vol-bit-width = <5>;
696 anatop-delay-reg-offset = <0x170>;
697 anatop-delay-bit-shift = <26>;
698 anatop-delay-bit-width = <2>;
699 anatop-min-bit-val = <1>;
700 anatop-min-voltage = <725000>;
701 anatop-max-voltage = <1450000>;
702 };
703
704 reg_soc: regulator-vddsoc {
705 compatible = "fsl,anatop-regulator";
706 regulator-name = "vddsoc";
707 regulator-min-microvolt = <725000>;
708 regulator-max-microvolt = <1450000>;
709 regulator-always-on;
710 anatop-reg-offset = <0x140>;
711 anatop-vol-bit-shift = <18>;
712 anatop-vol-bit-width = <5>;
713 anatop-delay-reg-offset = <0x170>;
714 anatop-delay-bit-shift = <28>;
715 anatop-delay-bit-width = <2>;
716 anatop-min-bit-val = <1>;
717 anatop-min-voltage = <725000>;
718 anatop-max-voltage = <1450000>;
719 };
720 };
721
722 tempmon: tempmon {
723 compatible = "fsl,imx6q-tempmon";
724 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
725 fsl,tempmon = <&anatop>;
726 fsl,tempmon-data = <&ocotp>;
727 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
728 };
729
730 usbphy1: usbphy@020c9000 {
731 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
732 reg = <0x020c9000 0x1000>;
733 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
735 fsl,anatop = <&anatop>;
736 };
737
738 usbphy2: usbphy@020ca000 {
739 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
740 reg = <0x020ca000 0x1000>;
741 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
743 fsl,anatop = <&anatop>;
744 };
745
746 snvs: snvs@020cc000 {
747 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
748 reg = <0x020cc000 0x4000>;
749
750 snvs_rtc: snvs-rtc-lp {
751 compatible = "fsl,sec-v4.0-mon-rtc-lp";
752 regmap = <&snvs>;
753 offset = <0x34>;
754 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
755 <0 20 IRQ_TYPE_LEVEL_HIGH>;
756 };
757
758 snvs_poweroff: snvs-poweroff {
759 compatible = "syscon-poweroff";
760 regmap = <&snvs>;
761 offset = <0x38>;
762 mask = <0x60>;
763 status = "disabled";
764 };
765 };
766
767 epit1: epit@020d0000 { /* EPIT1 */
768 reg = <0x020d0000 0x4000>;
769 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
770 };
771
772 epit2: epit@020d4000 { /* EPIT2 */
773 reg = <0x020d4000 0x4000>;
774 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
775 };
776
777 src: src@020d8000 {
778 compatible = "fsl,imx6q-src", "fsl,imx51-src";
779 reg = <0x020d8000 0x4000>;
780 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
781 <0 96 IRQ_TYPE_LEVEL_HIGH>;
782 #reset-cells = <1>;
783 };
784
785 gpc: gpc@020dc000 {
786 compatible = "fsl,imx6q-gpc";
787 reg = <0x020dc000 0x4000>;
788 interrupt-controller;
789 #interrupt-cells = <3>;
790 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
791 <0 90 IRQ_TYPE_LEVEL_HIGH>;
792 interrupt-parent = <&intc>;
793 pu-supply = <&reg_pu>;
794 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
795 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
796 <&clks IMX6QDL_CLK_GPU2D_CORE>,
797 <&clks IMX6QDL_CLK_GPU2D_AXI>,
798 <&clks IMX6QDL_CLK_OPENVG_AXI>,
799 <&clks IMX6QDL_CLK_VPU_AXI>;
800 #power-domain-cells = <1>;
801 };
802
803 gpr: iomuxc-gpr@020e0000 {
804 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
805 reg = <0x020e0000 0x38>;
806 };
807
808 iomuxc: iomuxc@020e0000 {
809 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
810 reg = <0x020e0000 0x4000>;
1f6e9bd2 811 u-boot,dm-spl;
39f41da3
JT		 812 };
813
814 ldb: ldb@020e0008 {
815 #address-cells = <1>;
816 #size-cells = <0>;
817 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
818 gpr = <&gpr>;
819 status = "disabled";
820
821 lvds-channel@0 {
822 #address-cells = <1>;
823 #size-cells = <0>;
824 reg = <0>;
825 status = "disabled";
826
827 port@0 {
828 reg = <0>;
829
830 lvds0_mux_0: endpoint {
831 remote-endpoint = <&ipu1_di0_lvds0>;
832 };
833 };
834
835 port@1 {
836 reg = <1>;
837
838 lvds0_mux_1: endpoint {
839 remote-endpoint = <&ipu1_di1_lvds0>;
840 };
841 };
842 };
843
844 lvds-channel@1 {
845 #address-cells = <1>;
846 #size-cells = <0>;
847 reg = <1>;
848 status = "disabled";
849
850 port@0 {
851 reg = <0>;
852
853 lvds1_mux_0: endpoint {
854 remote-endpoint = <&ipu1_di0_lvds1>;
855 };
856 };
857
858 port@1 {
859 reg = <1>;
860
861 lvds1_mux_1: endpoint {
862 remote-endpoint = <&ipu1_di1_lvds1>;
863 };
864 };
865 };
866 };
867
868 dcic1: dcic@020e4000 {
869 reg = <0x020e4000 0x4000>;
870 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
871 };
872
873 dcic2: dcic@020e8000 {
874 reg = <0x020e8000 0x4000>;
875 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
876 };
877
878 sdma: sdma@020ec000 {
879 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
880 reg = <0x020ec000 0x4000>;
881 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clks IMX6QDL_CLK_SDMA>,
883 <&clks IMX6QDL_CLK_SDMA>;
884 clock-names = "ipg", "ahb";
885 #dma-cells = <3>;
886 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
887 };
888 };
889
890 aips-bus@02100000 { /* AIPS2 */
891 compatible = "fsl,aips-bus", "simple-bus";
892 #address-cells = <1>;
893 #size-cells = <1>;
894 reg = <0x02100000 0x100000>;
895 ranges;
1f6e9bd2 896 u-boot,dm-spl;
39f41da3
JT		 897
898 crypto: caam@2100000 {
899 compatible = "fsl,sec-v4.0";
900 fsl,sec-era = <4>;
901 #address-cells = <1>;
902 #size-cells = <1>;
903 reg = <0x2100000 0x10000>;
904 ranges = <0 0x2100000 0x10000>;
905 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
906 <&clks IMX6QDL_CLK_CAAM_ACLK>,
907 <&clks IMX6QDL_CLK_CAAM_IPG>,
908 <&clks IMX6QDL_CLK_EIM_SLOW>;
909 clock-names = "mem", "aclk", "ipg", "emi_slow";
910
911 sec_jr0: jr0@1000 {
912 compatible = "fsl,sec-v4.0-job-ring";
913 reg = <0x1000 0x1000>;
914 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
915 };
916
917 sec_jr1: jr1@2000 {
918 compatible = "fsl,sec-v4.0-job-ring";
919 reg = <0x2000 0x1000>;
920 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
921 };
922 };
923
924 aipstz@0217c000 { /* AIPSTZ2 */
925 reg = <0x0217c000 0x4000>;
926 };
927
928 usbotg: usb@02184000 {
929 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
930 reg = <0x02184000 0x200>;
931 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&clks IMX6QDL_CLK_USBOH3>;
933 fsl,usbphy = <&usbphy1>;
934 fsl,usbmisc = <&usbmisc 0>;
935 ahb-burst-config = <0x0>;
936 tx-burst-size-dword = <0x10>;
937 rx-burst-size-dword = <0x10>;
938 status = "disabled";
939 };
940
941 usbh1: usb@02184200 {
942 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
943 reg = <0x02184200 0x200>;
944 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&clks IMX6QDL_CLK_USBOH3>;
946 fsl,usbphy = <&usbphy2>;
947 fsl,usbmisc = <&usbmisc 1>;
948 dr_mode = "host";
949 ahb-burst-config = <0x0>;
950 tx-burst-size-dword = <0x10>;
951 rx-burst-size-dword = <0x10>;
952 status = "disabled";
953 };
954
955 usbh2: usb@02184400 {
956 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
957 reg = <0x02184400 0x200>;
958 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&clks IMX6QDL_CLK_USBOH3>;
960 fsl,usbmisc = <&usbmisc 2>;
961 dr_mode = "host";
962 ahb-burst-config = <0x0>;
963 tx-burst-size-dword = <0x10>;
964 rx-burst-size-dword = <0x10>;
965 status = "disabled";
966 };
967
968 usbh3: usb@02184600 {
969 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
970 reg = <0x02184600 0x200>;
971 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&clks IMX6QDL_CLK_USBOH3>;
973 fsl,usbmisc = <&usbmisc 3>;
974 dr_mode = "host";
975 ahb-burst-config = <0x0>;
976 tx-burst-size-dword = <0x10>;
977 rx-burst-size-dword = <0x10>;
978 status = "disabled";
979 };
980
981 usbmisc: usbmisc@02184800 {
982 #index-cells = <1>;
983 compatible = "fsl,imx6q-usbmisc";
984 reg = <0x02184800 0x200>;
985 clocks = <&clks IMX6QDL_CLK_USBOH3>;
986 };
987
988 fec: ethernet@02188000 {
989 compatible = "fsl,imx6q-fec";
990 reg = <0x02188000 0x4000>;
991 interrupts-extended =
992 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
993 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clks IMX6QDL_CLK_ENET>,
995 <&clks IMX6QDL_CLK_ENET>,
996 <&clks IMX6QDL_CLK_ENET_REF>;
997 clock-names = "ipg", "ahb", "ptp";
998 status = "disabled";
999 };
1000
1001 mlb@0218c000 {
1002 reg = <0x0218c000 0x4000>;
1003 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1004 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1005 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1006 };
1007
1008 usdhc1: usdhc@02190000 {
1009 compatible = "fsl,imx6q-usdhc";
1010 reg = <0x02190000 0x4000>;
1011 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1013 <&clks IMX6QDL_CLK_USDHC1>,
1014 <&clks IMX6QDL_CLK_USDHC1>;
1015 clock-names = "ipg", "ahb", "per";
1016 bus-width = <4>;
1017 status = "disabled";
1018 };
1019
1020 usdhc2: usdhc@02194000 {
1021 compatible = "fsl,imx6q-usdhc";
1022 reg = <0x02194000 0x4000>;
1023 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1025 <&clks IMX6QDL_CLK_USDHC2>,
1026 <&clks IMX6QDL_CLK_USDHC2>;
1027 clock-names = "ipg", "ahb", "per";
1028 bus-width = <4>;
1029 status = "disabled";
1030 };
1031
1032 usdhc3: usdhc@02198000 {
1033 compatible = "fsl,imx6q-usdhc";
1034 reg = <0x02198000 0x4000>;
1035 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1037 <&clks IMX6QDL_CLK_USDHC3>,
1038 <&clks IMX6QDL_CLK_USDHC3>;
1039 clock-names = "ipg", "ahb", "per";
1040 bus-width = <4>;
1041 status = "disabled";
1042 };
1043
1044 usdhc4: usdhc@0219c000 {
1045 compatible = "fsl,imx6q-usdhc";
1046 reg = <0x0219c000 0x4000>;
1047 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1049 <&clks IMX6QDL_CLK_USDHC4>,
1050 <&clks IMX6QDL_CLK_USDHC4>;
1051 clock-names = "ipg", "ahb", "per";
1052 bus-width = <4>;
1053 status = "disabled";
1054 };
1055
1056 i2c1: i2c@021a0000 {
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1060 reg = <0x021a0000 0x4000>;
1061 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&clks IMX6QDL_CLK_I2C1>;
1063 status = "disabled";
1064 };
1065
1066 i2c2: i2c@021a4000 {
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1070 reg = <0x021a4000 0x4000>;
1071 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&clks IMX6QDL_CLK_I2C2>;
1073 status = "disabled";
1074 };
1075
1076 i2c3: i2c@021a8000 {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1080 reg = <0x021a8000 0x4000>;
1081 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&clks IMX6QDL_CLK_I2C3>;
1083 status = "disabled";
1084 };
1085
1086 romcp@021ac000 {
1087 reg = <0x021ac000 0x4000>;
1088 };
1089
1090 mmdc0: mmdc@021b0000 { /* MMDC0 */
1091 compatible = "fsl,imx6q-mmdc";
1092 reg = <0x021b0000 0x4000>;
1093 };
1094
1095 mmdc1: mmdc@021b4000 { /* MMDC1 */
1096 reg = <0x021b4000 0x4000>;
1097 };
1098
1099 weim: weim@021b8000 {
1100 compatible = "fsl,imx6q-weim";
1101 reg = <0x021b8000 0x4000>;
1102 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1104 };
1105
1106 ocotp: ocotp@021bc000 {
1107 compatible = "fsl,imx6q-ocotp", "syscon";
1108 reg = <0x021bc000 0x4000>;
1109 clocks = <&clks IMX6QDL_CLK_IIM>;
1110 };
1111
1112 tzasc@021d0000 { /* TZASC1 */
1113 reg = <0x021d0000 0x4000>;
1114 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1115 };
1116
1117 tzasc@021d4000 { /* TZASC2 */
1118 reg = <0x021d4000 0x4000>;
1119 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1120 };
1121
1122 audmux: audmux@021d8000 {
1123 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1124 reg = <0x021d8000 0x4000>;
1125 status = "disabled";
1126 };
1127
1128 mipi_csi: mipi@021dc000 {
1129 reg = <0x021dc000 0x4000>;
1130 };
1131
1132 mipi_dsi: mipi@021e0000 {
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135 reg = <0x021e0000 0x4000>;
1136 status = "disabled";
1137
1138 ports {
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141
1142 port@0 {
1143 reg = <0>;
1144
1145 mipi_mux_0: endpoint {
1146 remote-endpoint = <&ipu1_di0_mipi>;
1147 };
1148 };
1149
1150 port@1 {
1151 reg = <1>;
1152
1153 mipi_mux_1: endpoint {
1154 remote-endpoint = <&ipu1_di1_mipi>;
1155 };
1156 };
1157 };
1158 };
1159
1160 vdoa@021e4000 {
1161 reg = <0x021e4000 0x4000>;
1162 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1163 };
1164
1165 uart2: serial@021e8000 {
1166 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1167 reg = <0x021e8000 0x4000>;
1168 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1170 <&clks IMX6QDL_CLK_UART_SERIAL>;
1171 clock-names = "ipg", "per";
1172 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1173 dma-names = "rx", "tx";
1174 status = "disabled";
1175 };
1176
1177 uart3: serial@021ec000 {
1178 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1179 reg = <0x021ec000 0x4000>;
1180 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1182 <&clks IMX6QDL_CLK_UART_SERIAL>;
1183 clock-names = "ipg", "per";
1184 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1185 dma-names = "rx", "tx";
1186 status = "disabled";
1187 };
1188
1189 uart4: serial@021f0000 {
1190 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1191 reg = <0x021f0000 0x4000>;
1192 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1194 <&clks IMX6QDL_CLK_UART_SERIAL>;
1195 clock-names = "ipg", "per";
1196 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1197 dma-names = "rx", "tx";
1198 status = "disabled";
1199 };
1200
1201 uart5: serial@021f4000 {
1202 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1203 reg = <0x021f4000 0x4000>;
1204 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1206 <&clks IMX6QDL_CLK_UART_SERIAL>;
1207 clock-names = "ipg", "per";
1208 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1209 dma-names = "rx", "tx";
1210 status = "disabled";
1211 };
1212 };
1213
1214 ipu1: ipu@02400000 {
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 compatible = "fsl,imx6q-ipu";
1218 reg = <0x02400000 0x400000>;
1219 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1220 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1221 clocks = <&clks IMX6QDL_CLK_IPU1>,
1222 <&clks IMX6QDL_CLK_IPU1_DI0>,
1223 <&clks IMX6QDL_CLK_IPU1_DI1>;
1224 clock-names = "bus", "di0", "di1";
1225 resets = <&src 2>;
1226
1227 ipu1_csi0: port@0 {
1228 reg = <0>;
1229 };
1230
1231 ipu1_csi1: port@1 {
1232 reg = <1>;
1233 };
1234
1235 ipu1_di0: port@2 {
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 reg = <2>;
1239
1240 ipu1_di0_disp0: disp0-endpoint {
1241 };
1242
1243 ipu1_di0_hdmi: hdmi-endpoint {
1244 remote-endpoint = <&hdmi_mux_0>;
1245 };
1246
1247 ipu1_di0_mipi: mipi-endpoint {
1248 remote-endpoint = <&mipi_mux_0>;
1249 };
1250
1251 ipu1_di0_lvds0: lvds0-endpoint {
1252 remote-endpoint = <&lvds0_mux_0>;
1253 };
1254
1255 ipu1_di0_lvds1: lvds1-endpoint {
1256 remote-endpoint = <&lvds1_mux_0>;
1257 };
1258 };
1259
1260 ipu1_di1: port@3 {
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1263 reg = <3>;
1264
1265 ipu1_di1_disp1: disp1-endpoint {
1266 };
1267
1268 ipu1_di1_hdmi: hdmi-endpoint {
1269 remote-endpoint = <&hdmi_mux_1>;
1270 };
1271
1272 ipu1_di1_mipi: mipi-endpoint {
1273 remote-endpoint = <&mipi_mux_1>;
1274 };
1275
1276 ipu1_di1_lvds0: lvds0-endpoint {
1277 remote-endpoint = <&lvds0_mux_1>;
1278 };
1279
1280 ipu1_di1_lvds1: lvds1-endpoint {
1281 remote-endpoint = <&lvds1_mux_1>;
1282 };
1283 };
1284 };
1285 };
1286};
"Das U-Boot" Source Tree