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1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <dt-bindings/clock/imx6ul-clock.h> | |
10 | #include <dt-bindings/gpio/gpio.h> | |
11 | #include <dt-bindings/input/input.h> | |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
13 | #include "imx6ul-pinfunc.h" | |
14 | #include "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | aliases { | |
18 | ethernet0 = &fec1; | |
19 | ethernet1 = &fec2; | |
20 | gpio0 = &gpio1; | |
21 | gpio1 = &gpio2; | |
22 | gpio2 = &gpio3; | |
23 | gpio3 = &gpio4; | |
24 | gpio4 = &gpio5; | |
25 | i2c0 = &i2c1; | |
26 | i2c1 = &i2c2; | |
27 | i2c2 = &i2c3; | |
28 | i2c3 = &i2c4; | |
29 | mmc0 = &usdhc1; | |
30 | mmc1 = &usdhc2; | |
31 | serial0 = &uart1; | |
32 | serial1 = &uart2; | |
33 | serial2 = &uart3; | |
34 | serial3 = &uart4; | |
35 | serial4 = &uart5; | |
36 | serial5 = &uart6; | |
37 | serial6 = &uart7; | |
38 | serial7 = &uart8; | |
39 | sai1 = &sai1; | |
40 | sai2 = &sai2; | |
41 | sai3 = &sai3; | |
42 | spi0 = &ecspi1; | |
43 | spi1 = &ecspi2; | |
44 | spi2 = &ecspi3; | |
45 | spi3 = &ecspi4; | |
b3cab814 SS |
46 | usbotg0 = &usbotg1; |
47 | usbotg1 = &usbotg2; | |
b8ad70f7 JT |
48 | usbphy0 = &usbphy1; |
49 | usbphy1 = &usbphy2; | |
50 | }; | |
51 | ||
52 | cpus { | |
53 | #address-cells = <1>; | |
54 | #size-cells = <0>; | |
55 | ||
56 | cpu0: cpu@0 { | |
57 | compatible = "arm,cortex-a7"; | |
58 | device_type = "cpu"; | |
59 | reg = <0>; | |
60 | clock-latency = <61036>; /* two CLK32 periods */ | |
61 | operating-points = < | |
62 | /* kHz uV */ | |
63 | 528000 1175000 | |
64 | 396000 1025000 | |
65 | 198000 950000 | |
66 | >; | |
67 | fsl,soc-operating-points = < | |
68 | /* KHz uV */ | |
69 | 528000 1175000 | |
70 | 396000 1175000 | |
71 | 198000 1175000 | |
72 | >; | |
73 | clocks = <&clks IMX6UL_CLK_ARM>, | |
74 | <&clks IMX6UL_CLK_PLL2_BUS>, | |
75 | <&clks IMX6UL_CLK_PLL2_PFD2>, | |
76 | <&clks IMX6UL_CA7_SECONDARY_SEL>, | |
77 | <&clks IMX6UL_CLK_STEP>, | |
78 | <&clks IMX6UL_CLK_PLL1_SW>, | |
79 | <&clks IMX6UL_CLK_PLL1_SYS>, | |
80 | <&clks IMX6UL_PLL1_BYPASS>, | |
81 | <&clks IMX6UL_CLK_PLL1>, | |
82 | <&clks IMX6UL_PLL1_BYPASS_SRC>, | |
83 | <&clks IMX6UL_CLK_OSC>; | |
84 | clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", | |
85 | "secondary_sel", "step", "pll1_sw", | |
86 | "pll1_sys", "pll1_bypass", "pll1", | |
87 | "pll1_bypass_src", "osc"; | |
88 | arm-supply = <®_arm>; | |
89 | soc-supply = <®_soc>; | |
90 | }; | |
91 | }; | |
92 | ||
93 | intc: interrupt-controller@00a01000 { | |
94 | compatible = "arm,cortex-a7-gic"; | |
95 | #interrupt-cells = <3>; | |
96 | interrupt-controller; | |
97 | reg = <0x00a01000 0x1000>, | |
98 | <0x00a02000 0x1000>, | |
99 | <0x00a04000 0x2000>, | |
100 | <0x00a06000 0x2000>; | |
101 | }; | |
102 | ||
103 | ckil: clock-cli { | |
104 | compatible = "fixed-clock"; | |
105 | #clock-cells = <0>; | |
106 | clock-frequency = <32768>; | |
107 | clock-output-names = "ckil"; | |
108 | }; | |
109 | ||
110 | osc: clock-osc { | |
111 | compatible = "fixed-clock"; | |
112 | #clock-cells = <0>; | |
113 | clock-frequency = <24000000>; | |
114 | clock-output-names = "osc"; | |
115 | }; | |
116 | ||
117 | ipp_di0: clock-di0 { | |
118 | compatible = "fixed-clock"; | |
119 | #clock-cells = <0>; | |
120 | clock-frequency = <0>; | |
121 | clock-output-names = "ipp_di0"; | |
122 | }; | |
123 | ||
124 | ipp_di1: clock-di1 { | |
125 | compatible = "fixed-clock"; | |
126 | #clock-cells = <0>; | |
127 | clock-frequency = <0>; | |
128 | clock-output-names = "ipp_di1"; | |
129 | }; | |
130 | ||
131 | soc { | |
132 | #address-cells = <1>; | |
133 | #size-cells = <1>; | |
134 | compatible = "simple-bus"; | |
135 | interrupt-parent = <&gpc>; | |
136 | ranges; | |
152038ea | 137 | u-boot,dm-spl; |
b8ad70f7 JT |
138 | |
139 | pmu { | |
140 | compatible = "arm,cortex-a7-pmu"; | |
141 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
142 | status = "disabled"; | |
143 | }; | |
144 | ||
145 | ocram: sram@00900000 { | |
146 | compatible = "mmio-sram"; | |
147 | reg = <0x00900000 0x20000>; | |
148 | }; | |
149 | ||
150 | dma_apbh: dma-apbh@01804000 { | |
151 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | |
152 | reg = <0x01804000 0x2000>; | |
153 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
154 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
155 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
156 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
157 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; | |
158 | #dma-cells = <1>; | |
159 | dma-channels = <4>; | |
160 | clocks = <&clks IMX6UL_CLK_APBHDMA>; | |
161 | }; | |
162 | ||
163 | gpmi: gpmi-nand@01806000 { | |
164 | compatible = "fsl,imx6q-gpmi-nand"; | |
165 | #address-cells = <1>; | |
166 | #size-cells = <1>; | |
167 | reg = <0x01806000 0x2000>, <0x01808000 0x2000>; | |
168 | reg-names = "gpmi-nand", "bch"; | |
169 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; | |
170 | interrupt-names = "bch"; | |
171 | clocks = <&clks IMX6UL_CLK_GPMI_IO>, | |
172 | <&clks IMX6UL_CLK_GPMI_APB>, | |
173 | <&clks IMX6UL_CLK_GPMI_BCH>, | |
174 | <&clks IMX6UL_CLK_GPMI_BCH_APB>, | |
175 | <&clks IMX6UL_CLK_PER_BCH>; | |
176 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
177 | "gpmi_bch_apb", "per1_bch"; | |
178 | dmas = <&dma_apbh 0>; | |
179 | dma-names = "rx-tx"; | |
180 | status = "disabled"; | |
181 | }; | |
182 | ||
183 | aips1: aips-bus@02000000 { | |
184 | compatible = "fsl,aips-bus", "simple-bus"; | |
185 | #address-cells = <1>; | |
186 | #size-cells = <1>; | |
187 | reg = <0x02000000 0x100000>; | |
188 | ranges; | |
152038ea | 189 | u-boot,dm-spl; |
b8ad70f7 JT |
190 | |
191 | spba-bus@02000000 { | |
192 | compatible = "fsl,spba-bus", "simple-bus"; | |
193 | #address-cells = <1>; | |
194 | #size-cells = <1>; | |
195 | reg = <0x02000000 0x40000>; | |
196 | ranges; | |
197 | ||
198 | ecspi1: ecspi@02008000 { | |
199 | #address-cells = <1>; | |
200 | #size-cells = <0>; | |
201 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
202 | reg = <0x02008000 0x4000>; | |
203 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
204 | clocks = <&clks IMX6UL_CLK_ECSPI1>, | |
205 | <&clks IMX6UL_CLK_ECSPI1>; | |
206 | clock-names = "ipg", "per"; | |
207 | status = "disabled"; | |
208 | }; | |
209 | ||
210 | ecspi2: ecspi@0200c000 { | |
211 | #address-cells = <1>; | |
212 | #size-cells = <0>; | |
213 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
214 | reg = <0x0200c000 0x4000>; | |
215 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
216 | clocks = <&clks IMX6UL_CLK_ECSPI2>, | |
217 | <&clks IMX6UL_CLK_ECSPI2>; | |
218 | clock-names = "ipg", "per"; | |
219 | status = "disabled"; | |
220 | }; | |
221 | ||
222 | ecspi3: ecspi@02010000 { | |
223 | #address-cells = <1>; | |
224 | #size-cells = <0>; | |
225 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
226 | reg = <0x02010000 0x4000>; | |
227 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
228 | clocks = <&clks IMX6UL_CLK_ECSPI3>, | |
229 | <&clks IMX6UL_CLK_ECSPI3>; | |
230 | clock-names = "ipg", "per"; | |
231 | status = "disabled"; | |
232 | }; | |
233 | ||
234 | ecspi4: ecspi@02014000 { | |
235 | #address-cells = <1>; | |
236 | #size-cells = <0>; | |
237 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
238 | reg = <0x02014000 0x4000>; | |
239 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
240 | clocks = <&clks IMX6UL_CLK_ECSPI4>, | |
241 | <&clks IMX6UL_CLK_ECSPI4>; | |
242 | clock-names = "ipg", "per"; | |
243 | status = "disabled"; | |
244 | }; | |
245 | ||
246 | uart7: serial@02018000 { | |
247 | compatible = "fsl,imx6ul-uart", | |
248 | "fsl,imx6q-uart"; | |
249 | reg = <0x02018000 0x4000>; | |
250 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
251 | clocks = <&clks IMX6UL_CLK_UART7_IPG>, | |
252 | <&clks IMX6UL_CLK_UART7_SERIAL>; | |
253 | clock-names = "ipg", "per"; | |
254 | status = "disabled"; | |
255 | }; | |
256 | ||
257 | uart1: serial@02020000 { | |
258 | compatible = "fsl,imx6ul-uart", | |
259 | "fsl,imx6q-uart"; | |
260 | reg = <0x02020000 0x4000>; | |
261 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
262 | clocks = <&clks IMX6UL_CLK_UART1_IPG>, | |
263 | <&clks IMX6UL_CLK_UART1_SERIAL>; | |
264 | clock-names = "ipg", "per"; | |
265 | status = "disabled"; | |
266 | }; | |
267 | ||
268 | uart8: serial@02024000 { | |
269 | compatible = "fsl,imx6ul-uart", | |
270 | "fsl,imx6q-uart"; | |
271 | reg = <0x02024000 0x4000>; | |
272 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
273 | clocks = <&clks IMX6UL_CLK_UART8_IPG>, | |
274 | <&clks IMX6UL_CLK_UART8_SERIAL>; | |
275 | clock-names = "ipg", "per"; | |
276 | status = "disabled"; | |
277 | }; | |
278 | ||
279 | sai1: sai@02028000 { | |
280 | #sound-dai-cells = <0>; | |
281 | compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
282 | reg = <0x02028000 0x4000>; | |
283 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
284 | clocks = <&clks IMX6UL_CLK_SAI1_IPG>, | |
285 | <&clks IMX6UL_CLK_SAI1>, | |
286 | <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
287 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
288 | dmas = <&sdma 35 24 0>, | |
289 | <&sdma 36 24 0>; | |
290 | dma-names = "rx", "tx"; | |
291 | status = "disabled"; | |
292 | }; | |
293 | ||
294 | sai2: sai@0202c000 { | |
295 | #sound-dai-cells = <0>; | |
296 | compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
297 | reg = <0x0202c000 0x4000>; | |
298 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
299 | clocks = <&clks IMX6UL_CLK_SAI2_IPG>, | |
300 | <&clks IMX6UL_CLK_SAI2>, | |
301 | <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
302 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
303 | dmas = <&sdma 37 24 0>, | |
304 | <&sdma 38 24 0>; | |
305 | dma-names = "rx", "tx"; | |
306 | status = "disabled"; | |
307 | }; | |
308 | ||
309 | sai3: sai@02030000 { | |
310 | #sound-dai-cells = <0>; | |
311 | compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
312 | reg = <0x02030000 0x4000>; | |
313 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
314 | clocks = <&clks IMX6UL_CLK_SAI3_IPG>, | |
315 | <&clks IMX6UL_CLK_SAI3>, | |
316 | <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
317 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
318 | dmas = <&sdma 39 24 0>, | |
319 | <&sdma 40 24 0>; | |
320 | dma-names = "rx", "tx"; | |
321 | status = "disabled"; | |
322 | }; | |
323 | }; | |
324 | ||
325 | tsc: tsc@02040000 { | |
326 | compatible = "fsl,imx6ul-tsc"; | |
327 | reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; | |
328 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
329 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
330 | clocks = <&clks IMX6UL_CLK_IPG>, | |
331 | <&clks IMX6UL_CLK_ADC2>; | |
332 | clock-names = "tsc", "adc"; | |
333 | status = "disabled"; | |
334 | }; | |
335 | ||
336 | pwm1: pwm@02080000 { | |
337 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
338 | reg = <0x02080000 0x4000>; | |
339 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
340 | clocks = <&clks IMX6UL_CLK_PWM1>, | |
341 | <&clks IMX6UL_CLK_PWM1>; | |
342 | clock-names = "ipg", "per"; | |
343 | #pwm-cells = <2>; | |
344 | status = "disabled"; | |
345 | }; | |
346 | ||
347 | pwm2: pwm@02084000 { | |
348 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
349 | reg = <0x02084000 0x4000>; | |
350 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
351 | clocks = <&clks IMX6UL_CLK_PWM2>, | |
352 | <&clks IMX6UL_CLK_PWM2>; | |
353 | clock-names = "ipg", "per"; | |
354 | #pwm-cells = <2>; | |
355 | status = "disabled"; | |
356 | }; | |
357 | ||
358 | pwm3: pwm@02088000 { | |
359 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
360 | reg = <0x02088000 0x4000>; | |
361 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
362 | clocks = <&clks IMX6UL_CLK_PWM3>, | |
363 | <&clks IMX6UL_CLK_PWM3>; | |
364 | clock-names = "ipg", "per"; | |
365 | #pwm-cells = <2>; | |
366 | status = "disabled"; | |
367 | }; | |
368 | ||
369 | pwm4: pwm@0208c000 { | |
370 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
371 | reg = <0x0208c000 0x4000>; | |
372 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
373 | clocks = <&clks IMX6UL_CLK_PWM4>, | |
374 | <&clks IMX6UL_CLK_PWM4>; | |
375 | clock-names = "ipg", "per"; | |
376 | #pwm-cells = <2>; | |
377 | status = "disabled"; | |
378 | }; | |
379 | ||
380 | can1: flexcan@02090000 { | |
381 | compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; | |
382 | reg = <0x02090000 0x4000>; | |
383 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
384 | clocks = <&clks IMX6UL_CLK_CAN1_IPG>, | |
385 | <&clks IMX6UL_CLK_CAN1_SERIAL>; | |
386 | clock-names = "ipg", "per"; | |
387 | status = "disabled"; | |
388 | }; | |
389 | ||
390 | can2: flexcan@02094000 { | |
391 | compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; | |
392 | reg = <0x02094000 0x4000>; | |
393 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
394 | clocks = <&clks IMX6UL_CLK_CAN2_IPG>, | |
395 | <&clks IMX6UL_CLK_CAN2_SERIAL>; | |
396 | clock-names = "ipg", "per"; | |
397 | status = "disabled"; | |
398 | }; | |
399 | ||
400 | gpt1: gpt@02098000 { | |
401 | compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
402 | reg = <0x02098000 0x4000>; | |
403 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
404 | clocks = <&clks IMX6UL_CLK_GPT1_BUS>, | |
405 | <&clks IMX6UL_CLK_GPT1_SERIAL>; | |
406 | clock-names = "ipg", "per"; | |
407 | }; | |
408 | ||
409 | gpio1: gpio@0209c000 { | |
410 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
411 | reg = <0x0209c000 0x4000>; | |
412 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
413 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
414 | gpio-controller; | |
415 | #gpio-cells = <2>; | |
416 | interrupt-controller; | |
417 | #interrupt-cells = <2>; | |
418 | gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, | |
419 | <&iomuxc 16 33 16>; | |
152038ea | 420 | u-boot,dm-spl; |
b8ad70f7 JT |
421 | }; |
422 | ||
423 | gpio2: gpio@020a0000 { | |
424 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
425 | reg = <0x020a0000 0x4000>; | |
426 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
427 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
428 | gpio-controller; | |
429 | #gpio-cells = <2>; | |
430 | interrupt-controller; | |
431 | #interrupt-cells = <2>; | |
432 | gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; | |
433 | }; | |
434 | ||
435 | gpio3: gpio@020a4000 { | |
436 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
437 | reg = <0x020a4000 0x4000>; | |
438 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
439 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
440 | gpio-controller; | |
441 | #gpio-cells = <2>; | |
442 | interrupt-controller; | |
443 | #interrupt-cells = <2>; | |
444 | gpio-ranges = <&iomuxc 0 65 29>; | |
445 | }; | |
446 | ||
447 | gpio4: gpio@020a8000 { | |
448 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
449 | reg = <0x020a8000 0x4000>; | |
450 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
451 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
452 | gpio-controller; | |
453 | #gpio-cells = <2>; | |
454 | interrupt-controller; | |
455 | #interrupt-cells = <2>; | |
456 | gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; | |
152038ea | 457 | u-boot,dm-spl; |
b8ad70f7 JT |
458 | }; |
459 | ||
460 | gpio5: gpio@020ac000 { | |
461 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
462 | reg = <0x020ac000 0x4000>; | |
463 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
464 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
465 | gpio-controller; | |
466 | #gpio-cells = <2>; | |
467 | interrupt-controller; | |
468 | #interrupt-cells = <2>; | |
469 | gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; | |
470 | }; | |
471 | ||
472 | fec2: ethernet@020b4000 { | |
473 | compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; | |
474 | reg = <0x020b4000 0x4000>; | |
475 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
476 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
477 | clocks = <&clks IMX6UL_CLK_ENET>, | |
478 | <&clks IMX6UL_CLK_ENET_AHB>, | |
479 | <&clks IMX6UL_CLK_ENET_PTP>, | |
480 | <&clks IMX6UL_CLK_ENET2_REF_125M>, | |
481 | <&clks IMX6UL_CLK_ENET2_REF_125M>; | |
482 | clock-names = "ipg", "ahb", "ptp", | |
483 | "enet_clk_ref", "enet_out"; | |
484 | fsl,num-tx-queues=<1>; | |
485 | fsl,num-rx-queues=<1>; | |
486 | status = "disabled"; | |
487 | }; | |
488 | ||
489 | kpp: kpp@020b8000 { | |
490 | compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; | |
491 | reg = <0x020b8000 0x4000>; | |
492 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
493 | clocks = <&clks IMX6UL_CLK_KPP>; | |
494 | status = "disabled"; | |
495 | }; | |
496 | ||
497 | wdog1: wdog@020bc000 { | |
498 | compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
499 | reg = <0x020bc000 0x4000>; | |
500 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
501 | clocks = <&clks IMX6UL_CLK_WDOG1>; | |
502 | }; | |
503 | ||
504 | wdog2: wdog@020c0000 { | |
505 | compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
506 | reg = <0x020c0000 0x4000>; | |
507 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
508 | clocks = <&clks IMX6UL_CLK_WDOG2>; | |
509 | status = "disabled"; | |
510 | }; | |
511 | ||
512 | clks: ccm@020c4000 { | |
513 | compatible = "fsl,imx6ul-ccm"; | |
514 | reg = <0x020c4000 0x4000>; | |
515 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
516 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
517 | #clock-cells = <1>; | |
518 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; | |
519 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; | |
520 | }; | |
521 | ||
522 | anatop: anatop@020c8000 { | |
523 | compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", | |
524 | "syscon", "simple-bus"; | |
525 | reg = <0x020c8000 0x1000>; | |
526 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
527 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
528 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
529 | ||
530 | reg_3p0: regulator-3p0 { | |
531 | compatible = "fsl,anatop-regulator"; | |
532 | regulator-name = "vdd3p0"; | |
533 | regulator-min-microvolt = <2625000>; | |
534 | regulator-max-microvolt = <3400000>; | |
535 | anatop-reg-offset = <0x120>; | |
536 | anatop-vol-bit-shift = <8>; | |
537 | anatop-vol-bit-width = <5>; | |
538 | anatop-min-bit-val = <0>; | |
539 | anatop-min-voltage = <2625000>; | |
540 | anatop-max-voltage = <3400000>; | |
541 | anatop-enable-bit = <0>; | |
542 | }; | |
543 | ||
544 | reg_arm: regulator-vddcore { | |
545 | compatible = "fsl,anatop-regulator"; | |
546 | regulator-name = "cpu"; | |
547 | regulator-min-microvolt = <725000>; | |
548 | regulator-max-microvolt = <1450000>; | |
549 | regulator-always-on; | |
550 | anatop-reg-offset = <0x140>; | |
551 | anatop-vol-bit-shift = <0>; | |
552 | anatop-vol-bit-width = <5>; | |
553 | anatop-delay-reg-offset = <0x170>; | |
554 | anatop-delay-bit-shift = <24>; | |
555 | anatop-delay-bit-width = <2>; | |
556 | anatop-min-bit-val = <1>; | |
557 | anatop-min-voltage = <725000>; | |
558 | anatop-max-voltage = <1450000>; | |
559 | }; | |
560 | ||
561 | reg_soc: regulator-vddsoc { | |
562 | compatible = "fsl,anatop-regulator"; | |
563 | regulator-name = "vddsoc"; | |
564 | regulator-min-microvolt = <725000>; | |
565 | regulator-max-microvolt = <1450000>; | |
566 | regulator-always-on; | |
567 | anatop-reg-offset = <0x140>; | |
568 | anatop-vol-bit-shift = <18>; | |
569 | anatop-vol-bit-width = <5>; | |
570 | anatop-delay-reg-offset = <0x170>; | |
571 | anatop-delay-bit-shift = <28>; | |
572 | anatop-delay-bit-width = <2>; | |
573 | anatop-min-bit-val = <1>; | |
574 | anatop-min-voltage = <725000>; | |
575 | anatop-max-voltage = <1450000>; | |
576 | }; | |
577 | }; | |
578 | ||
579 | usbphy1: usbphy@020c9000 { | |
580 | compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
581 | reg = <0x020c9000 0x1000>; | |
582 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
583 | clocks = <&clks IMX6UL_CLK_USBPHY1>; | |
584 | phy-3p0-supply = <®_3p0>; | |
585 | fsl,anatop = <&anatop>; | |
586 | }; | |
587 | ||
588 | usbphy2: usbphy@020ca000 { | |
589 | compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
590 | reg = <0x020ca000 0x1000>; | |
591 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
592 | clocks = <&clks IMX6UL_CLK_USBPHY2>; | |
593 | phy-3p0-supply = <®_3p0>; | |
594 | fsl,anatop = <&anatop>; | |
595 | }; | |
596 | ||
597 | snvs: snvs@020cc000 { | |
598 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; | |
599 | reg = <0x020cc000 0x4000>; | |
600 | ||
601 | snvs_rtc: snvs-rtc-lp { | |
602 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
603 | regmap = <&snvs>; | |
604 | offset = <0x34>; | |
605 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
606 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
607 | }; | |
608 | ||
609 | snvs_poweroff: snvs-poweroff { | |
610 | compatible = "syscon-poweroff"; | |
611 | regmap = <&snvs>; | |
612 | offset = <0x38>; | |
613 | mask = <0x60>; | |
614 | status = "disabled"; | |
615 | }; | |
616 | ||
617 | snvs_pwrkey: snvs-powerkey { | |
618 | compatible = "fsl,sec-v4.0-pwrkey"; | |
619 | regmap = <&snvs>; | |
620 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
621 | linux,keycode = <KEY_POWER>; | |
622 | wakeup-source; | |
623 | }; | |
624 | }; | |
625 | ||
626 | epit1: epit@020d0000 { | |
627 | reg = <0x020d0000 0x4000>; | |
628 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
629 | }; | |
630 | ||
631 | epit2: epit@020d4000 { | |
632 | reg = <0x020d4000 0x4000>; | |
633 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
634 | }; | |
635 | ||
636 | src: src@020d8000 { | |
637 | compatible = "fsl,imx6ul-src", "fsl,imx51-src"; | |
638 | reg = <0x020d8000 0x4000>; | |
639 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
640 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
641 | #reset-cells = <1>; | |
642 | }; | |
643 | ||
644 | gpc: gpc@020dc000 { | |
645 | compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; | |
646 | reg = <0x020dc000 0x4000>; | |
647 | interrupt-controller; | |
648 | #interrupt-cells = <3>; | |
649 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
650 | interrupt-parent = <&intc>; | |
651 | }; | |
652 | ||
653 | iomuxc: iomuxc@020e0000 { | |
654 | compatible = "fsl,imx6ul-iomuxc"; | |
655 | reg = <0x020e0000 0x4000>; | |
152038ea | 656 | u-boot,dm-spl; |
b8ad70f7 JT |
657 | }; |
658 | ||
659 | gpr: iomuxc-gpr@020e4000 { | |
660 | compatible = "fsl,imx6ul-iomuxc-gpr", | |
661 | "fsl,imx6q-iomuxc-gpr", "syscon"; | |
662 | reg = <0x020e4000 0x4000>; | |
663 | }; | |
664 | ||
665 | gpt2: gpt@020e8000 { | |
666 | compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
667 | reg = <0x020e8000 0x4000>; | |
668 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
669 | clocks = <&clks IMX6UL_CLK_GPT2_BUS>, | |
670 | <&clks IMX6UL_CLK_GPT2_SERIAL>; | |
671 | clock-names = "ipg", "per"; | |
672 | }; | |
673 | ||
674 | sdma: sdma@020ec000 { | |
675 | compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", | |
676 | "fsl,imx35-sdma"; | |
677 | reg = <0x020ec000 0x4000>; | |
678 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
679 | clocks = <&clks IMX6UL_CLK_SDMA>, | |
680 | <&clks IMX6UL_CLK_SDMA>; | |
681 | clock-names = "ipg", "ahb"; | |
682 | #dma-cells = <3>; | |
683 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; | |
684 | }; | |
685 | ||
686 | pwm5: pwm@020f0000 { | |
687 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
688 | reg = <0x020f0000 0x4000>; | |
689 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
690 | clocks = <&clks IMX6UL_CLK_PWM5>, | |
691 | <&clks IMX6UL_CLK_PWM5>; | |
692 | clock-names = "ipg", "per"; | |
693 | #pwm-cells = <2>; | |
694 | status = "disabled"; | |
695 | }; | |
696 | ||
697 | pwm6: pwm@020f4000 { | |
698 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
699 | reg = <0x020f4000 0x4000>; | |
700 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
701 | clocks = <&clks IMX6UL_CLK_PWM6>, | |
702 | <&clks IMX6UL_CLK_PWM6>; | |
703 | clock-names = "ipg", "per"; | |
704 | #pwm-cells = <2>; | |
705 | status = "disabled"; | |
706 | }; | |
707 | ||
708 | pwm7: pwm@020f8000 { | |
709 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
710 | reg = <0x020f8000 0x4000>; | |
711 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
712 | clocks = <&clks IMX6UL_CLK_PWM7>, | |
713 | <&clks IMX6UL_CLK_PWM7>; | |
714 | clock-names = "ipg", "per"; | |
715 | #pwm-cells = <2>; | |
716 | status = "disabled"; | |
717 | }; | |
718 | ||
719 | pwm8: pwm@020fc000 { | |
720 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
721 | reg = <0x020fc000 0x4000>; | |
722 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
723 | clocks = <&clks IMX6UL_CLK_PWM8>, | |
724 | <&clks IMX6UL_CLK_PWM8>; | |
725 | clock-names = "ipg", "per"; | |
726 | #pwm-cells = <2>; | |
727 | status = "disabled"; | |
728 | }; | |
729 | }; | |
730 | ||
731 | aips2: aips-bus@02100000 { | |
732 | compatible = "fsl,aips-bus", "simple-bus"; | |
733 | #address-cells = <1>; | |
734 | #size-cells = <1>; | |
735 | reg = <0x02100000 0x100000>; | |
736 | ranges; | |
152038ea | 737 | u-boot,dm-spl; |
b8ad70f7 JT |
738 | |
739 | usbotg1: usb@02184000 { | |
740 | compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
741 | reg = <0x02184000 0x200>; | |
742 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
743 | clocks = <&clks IMX6UL_CLK_USBOH3>; | |
744 | fsl,usbphy = <&usbphy1>; | |
745 | fsl,usbmisc = <&usbmisc 0>; | |
746 | fsl,anatop = <&anatop>; | |
747 | ahb-burst-config = <0x0>; | |
748 | tx-burst-size-dword = <0x10>; | |
749 | rx-burst-size-dword = <0x10>; | |
750 | status = "disabled"; | |
751 | }; | |
752 | ||
753 | usbotg2: usb@02184200 { | |
754 | compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
755 | reg = <0x02184200 0x200>; | |
756 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
757 | clocks = <&clks IMX6UL_CLK_USBOH3>; | |
758 | fsl,usbphy = <&usbphy2>; | |
759 | fsl,usbmisc = <&usbmisc 1>; | |
760 | ahb-burst-config = <0x0>; | |
761 | tx-burst-size-dword = <0x10>; | |
762 | rx-burst-size-dword = <0x10>; | |
763 | status = "disabled"; | |
764 | }; | |
765 | ||
766 | usbmisc: usbmisc@02184800 { | |
767 | #index-cells = <1>; | |
768 | compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; | |
769 | reg = <0x02184800 0x200>; | |
770 | }; | |
771 | ||
772 | fec1: ethernet@02188000 { | |
773 | compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; | |
774 | reg = <0x02188000 0x4000>; | |
775 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
776 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
777 | clocks = <&clks IMX6UL_CLK_ENET>, | |
778 | <&clks IMX6UL_CLK_ENET_AHB>, | |
779 | <&clks IMX6UL_CLK_ENET_PTP>, | |
780 | <&clks IMX6UL_CLK_ENET_REF>, | |
781 | <&clks IMX6UL_CLK_ENET_REF>; | |
782 | clock-names = "ipg", "ahb", "ptp", | |
783 | "enet_clk_ref", "enet_out"; | |
784 | fsl,num-tx-queues=<1>; | |
785 | fsl,num-rx-queues=<1>; | |
786 | status = "disabled"; | |
787 | }; | |
788 | ||
789 | usdhc1: usdhc@02190000 { | |
790 | compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
791 | reg = <0x02190000 0x4000>; | |
792 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
793 | clocks = <&clks IMX6UL_CLK_USDHC1>, | |
794 | <&clks IMX6UL_CLK_USDHC1>, | |
795 | <&clks IMX6UL_CLK_USDHC1>; | |
796 | clock-names = "ipg", "ahb", "per"; | |
797 | bus-width = <4>; | |
798 | status = "disabled"; | |
799 | }; | |
800 | ||
801 | usdhc2: usdhc@02194000 { | |
802 | compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
803 | reg = <0x02194000 0x4000>; | |
804 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
805 | clocks = <&clks IMX6UL_CLK_USDHC2>, | |
806 | <&clks IMX6UL_CLK_USDHC2>, | |
807 | <&clks IMX6UL_CLK_USDHC2>; | |
808 | clock-names = "ipg", "ahb", "per"; | |
809 | bus-width = <4>; | |
810 | status = "disabled"; | |
811 | }; | |
812 | ||
813 | adc1: adc@02198000 { | |
814 | compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; | |
815 | reg = <0x02198000 0x4000>; | |
816 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
817 | clocks = <&clks IMX6UL_CLK_ADC1>; | |
818 | num-channels = <2>; | |
819 | clock-names = "adc"; | |
820 | fsl,adck-max-frequency = <30000000>, <40000000>, | |
821 | <20000000>; | |
822 | status = "disabled"; | |
823 | }; | |
824 | ||
825 | i2c1: i2c@021a0000 { | |
826 | #address-cells = <1>; | |
827 | #size-cells = <0>; | |
828 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
829 | reg = <0x021a0000 0x4000>; | |
830 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
831 | clocks = <&clks IMX6UL_CLK_I2C1>; | |
832 | status = "disabled"; | |
833 | }; | |
834 | ||
835 | i2c2: i2c@021a4000 { | |
836 | #address-cells = <1>; | |
837 | #size-cells = <0>; | |
838 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
839 | reg = <0x021a4000 0x4000>; | |
840 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
841 | clocks = <&clks IMX6UL_CLK_I2C2>; | |
842 | status = "disabled"; | |
843 | }; | |
844 | ||
845 | i2c3: i2c@021a8000 { | |
846 | #address-cells = <1>; | |
847 | #size-cells = <0>; | |
848 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
849 | reg = <0x021a8000 0x4000>; | |
850 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
851 | clocks = <&clks IMX6UL_CLK_I2C3>; | |
852 | status = "disabled"; | |
853 | }; | |
854 | ||
855 | mmdc: mmdc@021b0000 { | |
856 | compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; | |
857 | reg = <0x021b0000 0x4000>; | |
858 | }; | |
859 | ||
860 | lcdif: lcdif@021c8000 { | |
861 | compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; | |
862 | reg = <0x021c8000 0x4000>; | |
863 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
864 | clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, | |
865 | <&clks IMX6UL_CLK_LCDIF_APB>, | |
866 | <&clks IMX6UL_CLK_DUMMY>; | |
867 | clock-names = "pix", "axi", "disp_axi"; | |
868 | status = "disabled"; | |
869 | }; | |
870 | ||
871 | qspi: qspi@021e0000 { | |
872 | #address-cells = <1>; | |
873 | #size-cells = <0>; | |
874 | compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; | |
875 | reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; | |
876 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
877 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
878 | clocks = <&clks IMX6UL_CLK_QSPI>, | |
879 | <&clks IMX6UL_CLK_QSPI>; | |
880 | clock-names = "qspi_en", "qspi"; | |
881 | status = "disabled"; | |
882 | }; | |
883 | ||
884 | uart2: serial@021e8000 { | |
885 | compatible = "fsl,imx6ul-uart", | |
886 | "fsl,imx6q-uart"; | |
887 | reg = <0x021e8000 0x4000>; | |
888 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
889 | clocks = <&clks IMX6UL_CLK_UART2_IPG>, | |
890 | <&clks IMX6UL_CLK_UART2_SERIAL>; | |
891 | clock-names = "ipg", "per"; | |
892 | status = "disabled"; | |
893 | }; | |
894 | ||
895 | uart3: serial@021ec000 { | |
896 | compatible = "fsl,imx6ul-uart", | |
897 | "fsl,imx6q-uart"; | |
898 | reg = <0x021ec000 0x4000>; | |
899 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
900 | clocks = <&clks IMX6UL_CLK_UART3_IPG>, | |
901 | <&clks IMX6UL_CLK_UART3_SERIAL>; | |
902 | clock-names = "ipg", "per"; | |
903 | status = "disabled"; | |
904 | }; | |
905 | ||
906 | uart4: serial@021f0000 { | |
907 | compatible = "fsl,imx6ul-uart", | |
908 | "fsl,imx6q-uart"; | |
909 | reg = <0x021f0000 0x4000>; | |
910 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
911 | clocks = <&clks IMX6UL_CLK_UART4_IPG>, | |
912 | <&clks IMX6UL_CLK_UART4_SERIAL>; | |
913 | clock-names = "ipg", "per"; | |
914 | status = "disabled"; | |
915 | }; | |
916 | ||
917 | uart5: serial@021f4000 { | |
918 | compatible = "fsl,imx6ul-uart", | |
919 | "fsl,imx6q-uart"; | |
920 | reg = <0x021f4000 0x4000>; | |
921 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
922 | clocks = <&clks IMX6UL_CLK_UART5_IPG>, | |
923 | <&clks IMX6UL_CLK_UART5_SERIAL>; | |
924 | clock-names = "ipg", "per"; | |
925 | status = "disabled"; | |
926 | }; | |
927 | ||
928 | i2c4: i2c@021f8000 { | |
929 | #address-cells = <1>; | |
930 | #size-cells = <0>; | |
931 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
932 | reg = <0x021f8000 0x4000>; | |
933 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
934 | clocks = <&clks IMX6UL_CLK_I2C4>; | |
935 | status = "disabled"; | |
936 | }; | |
937 | ||
938 | uart6: serial@021fc000 { | |
939 | compatible = "fsl,imx6ul-uart", | |
940 | "fsl,imx6q-uart"; | |
941 | reg = <0x021fc000 0x4000>; | |
942 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
943 | clocks = <&clks IMX6UL_CLK_UART6_IPG>, | |
944 | <&clks IMX6UL_CLK_UART6_SERIAL>; | |
945 | clock-names = "ipg", "per"; | |
946 | status = "disabled"; | |
947 | }; | |
948 | }; | |
949 | }; | |
950 | }; |