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4157c472 MV |
1 | /* |
2 | * Device Tree Source for the r8a7795 SoC | |
3 | * | |
4 | * Copyright (C) 2015 Renesas Electronics Corp. | |
5 | * | |
62b2bb53 | 6 | * SPDX-License-Identifier: GPL-2.0 |
4157c472 MV |
7 | */ |
8 | ||
9 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> | |
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
11 | #include <dt-bindings/power/r8a7795-sysc.h> | |
12 | ||
62b2bb53 MV |
13 | #define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 |
14 | ||
4157c472 MV |
15 | / { |
16 | compatible = "renesas,r8a7795"; | |
17 | #address-cells = <2>; | |
18 | #size-cells = <2>; | |
19 | ||
20 | aliases { | |
21 | i2c0 = &i2c0; | |
22 | i2c1 = &i2c1; | |
23 | i2c2 = &i2c2; | |
24 | i2c3 = &i2c3; | |
25 | i2c4 = &i2c4; | |
26 | i2c5 = &i2c5; | |
27 | i2c6 = &i2c6; | |
28 | i2c7 = &i2c_dvfs; | |
29 | }; | |
30 | ||
31 | psci { | |
32 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
33 | method = "smc"; | |
34 | }; | |
35 | ||
36 | cpus { | |
37 | #address-cells = <1>; | |
38 | #size-cells = <0>; | |
39 | ||
40 | a57_0: cpu@0 { | |
41 | compatible = "arm,cortex-a57", "arm,armv8"; | |
42 | reg = <0x0>; | |
43 | device_type = "cpu"; | |
44 | power-domains = <&sysc R8A7795_PD_CA57_CPU0>; | |
45 | next-level-cache = <&L2_CA57>; | |
46 | enable-method = "psci"; | |
47 | }; | |
48 | ||
49 | a57_1: cpu@1 { | |
50 | compatible = "arm,cortex-a57","arm,armv8"; | |
51 | reg = <0x1>; | |
52 | device_type = "cpu"; | |
53 | power-domains = <&sysc R8A7795_PD_CA57_CPU1>; | |
54 | next-level-cache = <&L2_CA57>; | |
55 | enable-method = "psci"; | |
56 | }; | |
57 | ||
58 | a57_2: cpu@2 { | |
59 | compatible = "arm,cortex-a57","arm,armv8"; | |
60 | reg = <0x2>; | |
61 | device_type = "cpu"; | |
62 | power-domains = <&sysc R8A7795_PD_CA57_CPU2>; | |
63 | next-level-cache = <&L2_CA57>; | |
64 | enable-method = "psci"; | |
65 | }; | |
66 | ||
67 | a57_3: cpu@3 { | |
68 | compatible = "arm,cortex-a57","arm,armv8"; | |
69 | reg = <0x3>; | |
70 | device_type = "cpu"; | |
71 | power-domains = <&sysc R8A7795_PD_CA57_CPU3>; | |
72 | next-level-cache = <&L2_CA57>; | |
73 | enable-method = "psci"; | |
74 | }; | |
75 | ||
76 | a53_0: cpu@100 { | |
77 | compatible = "arm,cortex-a53", "arm,armv8"; | |
78 | reg = <0x100>; | |
79 | device_type = "cpu"; | |
80 | power-domains = <&sysc R8A7795_PD_CA53_CPU0>; | |
81 | next-level-cache = <&L2_CA53>; | |
82 | enable-method = "psci"; | |
83 | }; | |
84 | ||
85 | a53_1: cpu@101 { | |
86 | compatible = "arm,cortex-a53","arm,armv8"; | |
87 | reg = <0x101>; | |
88 | device_type = "cpu"; | |
89 | power-domains = <&sysc R8A7795_PD_CA53_CPU1>; | |
90 | next-level-cache = <&L2_CA53>; | |
91 | enable-method = "psci"; | |
92 | }; | |
93 | ||
94 | a53_2: cpu@102 { | |
95 | compatible = "arm,cortex-a53","arm,armv8"; | |
96 | reg = <0x102>; | |
97 | device_type = "cpu"; | |
98 | power-domains = <&sysc R8A7795_PD_CA53_CPU2>; | |
99 | next-level-cache = <&L2_CA53>; | |
100 | enable-method = "psci"; | |
101 | }; | |
102 | ||
103 | a53_3: cpu@103 { | |
104 | compatible = "arm,cortex-a53","arm,armv8"; | |
105 | reg = <0x103>; | |
106 | device_type = "cpu"; | |
107 | power-domains = <&sysc R8A7795_PD_CA53_CPU3>; | |
108 | next-level-cache = <&L2_CA53>; | |
109 | enable-method = "psci"; | |
110 | }; | |
111 | ||
112 | L2_CA57: cache-controller-0 { | |
113 | compatible = "cache"; | |
114 | power-domains = <&sysc R8A7795_PD_CA57_SCU>; | |
115 | cache-unified; | |
116 | cache-level = <2>; | |
117 | }; | |
118 | ||
119 | L2_CA53: cache-controller-1 { | |
120 | compatible = "cache"; | |
121 | power-domains = <&sysc R8A7795_PD_CA53_SCU>; | |
122 | cache-unified; | |
123 | cache-level = <2>; | |
124 | }; | |
125 | }; | |
126 | ||
127 | extal_clk: extal { | |
128 | compatible = "fixed-clock"; | |
129 | #clock-cells = <0>; | |
130 | /* This value must be overridden by the board */ | |
131 | clock-frequency = <0>; | |
46933dfb | 132 | u-boot,dm-pre-reloc; |
4157c472 MV |
133 | }; |
134 | ||
135 | extalr_clk: extalr { | |
136 | compatible = "fixed-clock"; | |
137 | #clock-cells = <0>; | |
138 | /* This value must be overridden by the board */ | |
139 | clock-frequency = <0>; | |
46933dfb | 140 | u-boot,dm-pre-reloc; |
4157c472 MV |
141 | }; |
142 | ||
143 | /* | |
144 | * The external audio clocks are configured as 0 Hz fixed frequency | |
145 | * clocks by default. | |
146 | * Boards that provide audio clocks should override them. | |
147 | */ | |
148 | audio_clk_a: audio_clk_a { | |
149 | compatible = "fixed-clock"; | |
150 | #clock-cells = <0>; | |
151 | clock-frequency = <0>; | |
152 | }; | |
153 | ||
154 | audio_clk_b: audio_clk_b { | |
155 | compatible = "fixed-clock"; | |
156 | #clock-cells = <0>; | |
157 | clock-frequency = <0>; | |
158 | }; | |
159 | ||
160 | audio_clk_c: audio_clk_c { | |
161 | compatible = "fixed-clock"; | |
162 | #clock-cells = <0>; | |
163 | clock-frequency = <0>; | |
164 | }; | |
165 | ||
166 | /* External CAN clock - to be overridden by boards that provide it */ | |
167 | can_clk: can { | |
168 | compatible = "fixed-clock"; | |
169 | #clock-cells = <0>; | |
170 | clock-frequency = <0>; | |
171 | }; | |
172 | ||
173 | /* External SCIF clock - to be overridden by boards that provide it */ | |
174 | scif_clk: scif { | |
175 | compatible = "fixed-clock"; | |
176 | #clock-cells = <0>; | |
177 | clock-frequency = <0>; | |
178 | }; | |
179 | ||
180 | /* External PCIe clock - can be overridden by the board */ | |
181 | pcie_bus_clk: pcie_bus { | |
182 | compatible = "fixed-clock"; | |
183 | #clock-cells = <0>; | |
184 | clock-frequency = <0>; | |
185 | }; | |
186 | ||
37a79081 | 187 | soc: soc { |
4157c472 MV |
188 | compatible = "simple-bus"; |
189 | interrupt-parent = <&gic>; | |
190 | ||
191 | #address-cells = <2>; | |
192 | #size-cells = <2>; | |
193 | ranges; | |
46933dfb | 194 | u-boot,dm-pre-reloc; |
4157c472 MV |
195 | |
196 | gic: interrupt-controller@f1010000 { | |
197 | compatible = "arm,gic-400"; | |
198 | #interrupt-cells = <3>; | |
199 | #address-cells = <0>; | |
200 | interrupt-controller; | |
201 | reg = <0x0 0xf1010000 0 0x1000>, | |
202 | <0x0 0xf1020000 0 0x20000>, | |
203 | <0x0 0xf1040000 0 0x20000>, | |
204 | <0x0 0xf1060000 0 0x20000>; | |
205 | interrupts = <GIC_PPI 9 | |
206 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; | |
207 | clocks = <&cpg CPG_MOD 408>; | |
208 | clock-names = "clk"; | |
209 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
210 | resets = <&cpg 408>; | |
211 | }; | |
212 | ||
213 | wdt0: watchdog@e6020000 { | |
214 | compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; | |
215 | reg = <0 0xe6020000 0 0x0c>; | |
216 | clocks = <&cpg CPG_MOD 402>; | |
217 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
218 | resets = <&cpg 402>; | |
219 | status = "disabled"; | |
220 | }; | |
221 | ||
222 | gpio0: gpio@e6050000 { | |
223 | compatible = "renesas,gpio-r8a7795", | |
224 | "renesas,gpio-rcar"; | |
225 | reg = <0 0xe6050000 0 0x50>; | |
226 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
227 | #gpio-cells = <2>; | |
228 | gpio-controller; | |
229 | gpio-ranges = <&pfc 0 0 16>; | |
230 | #interrupt-cells = <2>; | |
231 | interrupt-controller; | |
232 | clocks = <&cpg CPG_MOD 912>; | |
233 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
234 | resets = <&cpg 912>; | |
235 | }; | |
236 | ||
237 | gpio1: gpio@e6051000 { | |
238 | compatible = "renesas,gpio-r8a7795", | |
239 | "renesas,gpio-rcar"; | |
240 | reg = <0 0xe6051000 0 0x50>; | |
241 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
242 | #gpio-cells = <2>; | |
243 | gpio-controller; | |
244 | gpio-ranges = <&pfc 0 32 28>; | |
245 | #interrupt-cells = <2>; | |
246 | interrupt-controller; | |
247 | clocks = <&cpg CPG_MOD 911>; | |
248 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
249 | resets = <&cpg 911>; | |
250 | }; | |
251 | ||
252 | gpio2: gpio@e6052000 { | |
253 | compatible = "renesas,gpio-r8a7795", | |
254 | "renesas,gpio-rcar"; | |
255 | reg = <0 0xe6052000 0 0x50>; | |
256 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
257 | #gpio-cells = <2>; | |
258 | gpio-controller; | |
259 | gpio-ranges = <&pfc 0 64 15>; | |
260 | #interrupt-cells = <2>; | |
261 | interrupt-controller; | |
262 | clocks = <&cpg CPG_MOD 910>; | |
263 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
264 | resets = <&cpg 910>; | |
265 | }; | |
266 | ||
267 | gpio3: gpio@e6053000 { | |
268 | compatible = "renesas,gpio-r8a7795", | |
269 | "renesas,gpio-rcar"; | |
270 | reg = <0 0xe6053000 0 0x50>; | |
271 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
272 | #gpio-cells = <2>; | |
273 | gpio-controller; | |
274 | gpio-ranges = <&pfc 0 96 16>; | |
275 | #interrupt-cells = <2>; | |
276 | interrupt-controller; | |
277 | clocks = <&cpg CPG_MOD 909>; | |
278 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
279 | resets = <&cpg 909>; | |
280 | }; | |
281 | ||
282 | gpio4: gpio@e6054000 { | |
283 | compatible = "renesas,gpio-r8a7795", | |
284 | "renesas,gpio-rcar"; | |
285 | reg = <0 0xe6054000 0 0x50>; | |
286 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
287 | #gpio-cells = <2>; | |
288 | gpio-controller; | |
289 | gpio-ranges = <&pfc 0 128 18>; | |
290 | #interrupt-cells = <2>; | |
291 | interrupt-controller; | |
292 | clocks = <&cpg CPG_MOD 908>; | |
293 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
294 | resets = <&cpg 908>; | |
295 | }; | |
296 | ||
297 | gpio5: gpio@e6055000 { | |
298 | compatible = "renesas,gpio-r8a7795", | |
299 | "renesas,gpio-rcar"; | |
300 | reg = <0 0xe6055000 0 0x50>; | |
301 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
302 | #gpio-cells = <2>; | |
303 | gpio-controller; | |
304 | gpio-ranges = <&pfc 0 160 26>; | |
305 | #interrupt-cells = <2>; | |
306 | interrupt-controller; | |
307 | clocks = <&cpg CPG_MOD 907>; | |
308 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
309 | resets = <&cpg 907>; | |
310 | }; | |
311 | ||
312 | gpio6: gpio@e6055400 { | |
313 | compatible = "renesas,gpio-r8a7795", | |
314 | "renesas,gpio-rcar"; | |
315 | reg = <0 0xe6055400 0 0x50>; | |
316 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
317 | #gpio-cells = <2>; | |
318 | gpio-controller; | |
319 | gpio-ranges = <&pfc 0 192 32>; | |
320 | #interrupt-cells = <2>; | |
321 | interrupt-controller; | |
322 | clocks = <&cpg CPG_MOD 906>; | |
323 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
324 | resets = <&cpg 906>; | |
325 | }; | |
326 | ||
327 | gpio7: gpio@e6055800 { | |
328 | compatible = "renesas,gpio-r8a7795", | |
329 | "renesas,gpio-rcar"; | |
330 | reg = <0 0xe6055800 0 0x50>; | |
331 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
332 | #gpio-cells = <2>; | |
333 | gpio-controller; | |
334 | gpio-ranges = <&pfc 0 224 4>; | |
335 | #interrupt-cells = <2>; | |
336 | interrupt-controller; | |
337 | clocks = <&cpg CPG_MOD 905>; | |
338 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
339 | resets = <&cpg 905>; | |
340 | }; | |
341 | ||
342 | pmu_a57 { | |
343 | compatible = "arm,cortex-a57-pmu"; | |
344 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
345 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
346 | <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
347 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
348 | interrupt-affinity = <&a57_0>, | |
349 | <&a57_1>, | |
350 | <&a57_2>, | |
351 | <&a57_3>; | |
352 | }; | |
353 | ||
354 | pmu_a53 { | |
355 | compatible = "arm,cortex-a53-pmu"; | |
356 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, | |
357 | <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
358 | <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, | |
359 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
360 | interrupt-affinity = <&a53_0>, | |
361 | <&a53_1>, | |
362 | <&a53_2>, | |
363 | <&a53_3>; | |
364 | }; | |
365 | ||
366 | timer { | |
367 | compatible = "arm,armv8-timer"; | |
368 | interrupts = <GIC_PPI 13 | |
369 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
370 | <GIC_PPI 14 | |
371 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
372 | <GIC_PPI 11 | |
373 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
374 | <GIC_PPI 10 | |
375 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
376 | }; | |
377 | ||
378 | cpg: clock-controller@e6150000 { | |
379 | compatible = "renesas,r8a7795-cpg-mssr"; | |
380 | reg = <0 0xe6150000 0 0x1000>; | |
381 | clocks = <&extal_clk>, <&extalr_clk>; | |
382 | clock-names = "extal", "extalr"; | |
383 | #clock-cells = <2>; | |
384 | #power-domain-cells = <0>; | |
385 | #reset-cells = <1>; | |
46933dfb | 386 | u-boot,dm-pre-reloc; |
4157c472 MV |
387 | }; |
388 | ||
389 | rst: reset-controller@e6160000 { | |
390 | compatible = "renesas,r8a7795-rst"; | |
391 | reg = <0 0xe6160000 0 0x0200>; | |
392 | }; | |
393 | ||
394 | prr: chipid@fff00044 { | |
395 | compatible = "renesas,prr"; | |
396 | reg = <0 0xfff00044 0 4>; | |
d7f0b852 | 397 | u-boot,dm-pre-reloc; |
4157c472 MV |
398 | }; |
399 | ||
400 | sysc: system-controller@e6180000 { | |
401 | compatible = "renesas,r8a7795-sysc"; | |
402 | reg = <0 0xe6180000 0 0x0400>; | |
403 | #power-domain-cells = <1>; | |
404 | }; | |
405 | ||
37a79081 | 406 | pfc: pin-controller@e6060000 { |
4157c472 MV |
407 | compatible = "renesas,pfc-r8a7795"; |
408 | reg = <0 0xe6060000 0 0x50c>; | |
409 | }; | |
410 | ||
411 | intc_ex: interrupt-controller@e61c0000 { | |
412 | compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; | |
413 | #interrupt-cells = <2>; | |
414 | interrupt-controller; | |
415 | reg = <0 0xe61c0000 0 0x200>; | |
416 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH | |
417 | GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH | |
418 | GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH | |
419 | GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH | |
420 | GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH | |
421 | GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; | |
422 | clocks = <&cpg CPG_MOD 407>; | |
423 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
424 | resets = <&cpg 407>; | |
425 | }; | |
426 | ||
427 | dmac0: dma-controller@e6700000 { | |
428 | compatible = "renesas,dmac-r8a7795", | |
429 | "renesas,rcar-dmac"; | |
430 | reg = <0 0xe6700000 0 0x10000>; | |
431 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH | |
432 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
433 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
434 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
435 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
436 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
437 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
438 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
439 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
440 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
441 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
442 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
443 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
444 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
445 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
446 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH | |
447 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
448 | interrupt-names = "error", | |
449 | "ch0", "ch1", "ch2", "ch3", | |
450 | "ch4", "ch5", "ch6", "ch7", | |
451 | "ch8", "ch9", "ch10", "ch11", | |
452 | "ch12", "ch13", "ch14", "ch15"; | |
453 | clocks = <&cpg CPG_MOD 219>; | |
454 | clock-names = "fck"; | |
455 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
456 | resets = <&cpg 219>; | |
457 | #dma-cells = <1>; | |
458 | dma-channels = <16>; | |
459 | }; | |
460 | ||
461 | dmac1: dma-controller@e7300000 { | |
462 | compatible = "renesas,dmac-r8a7795", | |
463 | "renesas,rcar-dmac"; | |
464 | reg = <0 0xe7300000 0 0x10000>; | |
465 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH | |
466 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
467 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
468 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
469 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
470 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
471 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
472 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
473 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
474 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
475 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
476 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
477 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
478 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
479 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
480 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH | |
481 | GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; | |
482 | interrupt-names = "error", | |
483 | "ch0", "ch1", "ch2", "ch3", | |
484 | "ch4", "ch5", "ch6", "ch7", | |
485 | "ch8", "ch9", "ch10", "ch11", | |
486 | "ch12", "ch13", "ch14", "ch15"; | |
487 | clocks = <&cpg CPG_MOD 218>; | |
488 | clock-names = "fck"; | |
489 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
490 | resets = <&cpg 218>; | |
491 | #dma-cells = <1>; | |
492 | dma-channels = <16>; | |
493 | }; | |
494 | ||
495 | dmac2: dma-controller@e7310000 { | |
496 | compatible = "renesas,dmac-r8a7795", | |
497 | "renesas,rcar-dmac"; | |
498 | reg = <0 0xe7310000 0 0x10000>; | |
499 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH | |
500 | GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH | |
501 | GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH | |
502 | GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH | |
503 | GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH | |
504 | GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH | |
505 | GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH | |
506 | GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH | |
507 | GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH | |
508 | GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH | |
509 | GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH | |
510 | GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH | |
511 | GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH | |
512 | GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH | |
513 | GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH | |
514 | GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH | |
515 | GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
516 | interrupt-names = "error", | |
517 | "ch0", "ch1", "ch2", "ch3", | |
518 | "ch4", "ch5", "ch6", "ch7", | |
519 | "ch8", "ch9", "ch10", "ch11", | |
520 | "ch12", "ch13", "ch14", "ch15"; | |
521 | clocks = <&cpg CPG_MOD 217>; | |
522 | clock-names = "fck"; | |
523 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
524 | resets = <&cpg 217>; | |
525 | #dma-cells = <1>; | |
526 | dma-channels = <16>; | |
527 | }; | |
528 | ||
529 | audma0: dma-controller@ec700000 { | |
530 | compatible = "renesas,dmac-r8a7795", | |
531 | "renesas,rcar-dmac"; | |
532 | reg = <0 0xec700000 0 0x10000>; | |
533 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH | |
534 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | |
535 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | |
536 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | |
537 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | |
538 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | |
539 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | |
540 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | |
541 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | |
542 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | |
543 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | |
544 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | |
545 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | |
546 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH | |
547 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | |
548 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | |
549 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | |
550 | interrupt-names = "error", | |
551 | "ch0", "ch1", "ch2", "ch3", | |
552 | "ch4", "ch5", "ch6", "ch7", | |
553 | "ch8", "ch9", "ch10", "ch11", | |
554 | "ch12", "ch13", "ch14", "ch15"; | |
555 | clocks = <&cpg CPG_MOD 502>; | |
556 | clock-names = "fck"; | |
557 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
558 | resets = <&cpg 502>; | |
559 | #dma-cells = <1>; | |
560 | dma-channels = <16>; | |
561 | }; | |
562 | ||
563 | audma1: dma-controller@ec720000 { | |
564 | compatible = "renesas,dmac-r8a7795", | |
565 | "renesas,rcar-dmac"; | |
566 | reg = <0 0xec720000 0 0x10000>; | |
567 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH | |
568 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | |
569 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | |
570 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | |
571 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | |
572 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | |
573 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | |
574 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | |
575 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | |
576 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | |
577 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH | |
578 | GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH | |
579 | GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH | |
580 | GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH | |
581 | GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH | |
582 | GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH | |
583 | GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | |
584 | interrupt-names = "error", | |
585 | "ch0", "ch1", "ch2", "ch3", | |
586 | "ch4", "ch5", "ch6", "ch7", | |
587 | "ch8", "ch9", "ch10", "ch11", | |
588 | "ch12", "ch13", "ch14", "ch15"; | |
589 | clocks = <&cpg CPG_MOD 501>; | |
590 | clock-names = "fck"; | |
591 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
592 | resets = <&cpg 501>; | |
593 | #dma-cells = <1>; | |
594 | dma-channels = <16>; | |
595 | }; | |
596 | ||
597 | avb: ethernet@e6800000 { | |
598 | compatible = "renesas,etheravb-r8a7795", | |
599 | "renesas,etheravb-rcar-gen3"; | |
600 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; | |
601 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
602 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
603 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
604 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
605 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
606 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
607 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
608 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
609 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
610 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
611 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
612 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
613 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
614 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
615 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
616 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
617 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
618 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
619 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
620 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
621 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
622 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
623 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
624 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
625 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
626 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
627 | "ch4", "ch5", "ch6", "ch7", | |
628 | "ch8", "ch9", "ch10", "ch11", | |
629 | "ch12", "ch13", "ch14", "ch15", | |
630 | "ch16", "ch17", "ch18", "ch19", | |
631 | "ch20", "ch21", "ch22", "ch23", | |
632 | "ch24"; | |
633 | clocks = <&cpg CPG_MOD 812>; | |
634 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
635 | resets = <&cpg 812>; | |
636 | phy-mode = "rgmii-txid"; | |
637 | #address-cells = <1>; | |
638 | #size-cells = <0>; | |
639 | status = "disabled"; | |
640 | }; | |
641 | ||
642 | can0: can@e6c30000 { | |
643 | compatible = "renesas,can-r8a7795", | |
644 | "renesas,rcar-gen3-can"; | |
645 | reg = <0 0xe6c30000 0 0x1000>; | |
646 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
647 | clocks = <&cpg CPG_MOD 916>, | |
648 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
649 | <&can_clk>; | |
650 | clock-names = "clkp1", "clkp2", "can_clk"; | |
651 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
652 | assigned-clock-rates = <40000000>; | |
653 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
654 | resets = <&cpg 916>; | |
655 | status = "disabled"; | |
656 | }; | |
657 | ||
658 | can1: can@e6c38000 { | |
659 | compatible = "renesas,can-r8a7795", | |
660 | "renesas,rcar-gen3-can"; | |
661 | reg = <0 0xe6c38000 0 0x1000>; | |
662 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
663 | clocks = <&cpg CPG_MOD 915>, | |
664 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
665 | <&can_clk>; | |
666 | clock-names = "clkp1", "clkp2", "can_clk"; | |
667 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
668 | assigned-clock-rates = <40000000>; | |
669 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
670 | resets = <&cpg 915>; | |
671 | status = "disabled"; | |
672 | }; | |
673 | ||
674 | canfd: can@e66c0000 { | |
675 | compatible = "renesas,r8a7795-canfd", | |
676 | "renesas,rcar-gen3-canfd"; | |
677 | reg = <0 0xe66c0000 0 0x8000>; | |
678 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, | |
679 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
680 | clocks = <&cpg CPG_MOD 914>, | |
681 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
682 | <&can_clk>; | |
683 | clock-names = "fck", "canfd", "can_clk"; | |
684 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
685 | assigned-clock-rates = <40000000>; | |
686 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
687 | resets = <&cpg 914>; | |
688 | status = "disabled"; | |
689 | ||
690 | channel0 { | |
691 | status = "disabled"; | |
692 | }; | |
693 | ||
694 | channel1 { | |
695 | status = "disabled"; | |
696 | }; | |
697 | }; | |
698 | ||
62b2bb53 MV |
699 | drif00: rif@e6f40000 { |
700 | compatible = "renesas,r8a7795-drif", | |
701 | "renesas,rcar-gen3-drif"; | |
702 | reg = <0 0xe6f40000 0 0x64>; | |
703 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
704 | clocks = <&cpg CPG_MOD 515>; | |
705 | clock-names = "fck"; | |
706 | dmas = <&dmac1 0x20>, <&dmac2 0x20>; | |
707 | dma-names = "rx", "rx"; | |
708 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
709 | resets = <&cpg 515>; | |
710 | renesas,bonding = <&drif01>; | |
711 | status = "disabled"; | |
712 | }; | |
713 | ||
714 | drif01: rif@e6f50000 { | |
715 | compatible = "renesas,r8a7795-drif", | |
716 | "renesas,rcar-gen3-drif"; | |
717 | reg = <0 0xe6f50000 0 0x64>; | |
718 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
719 | clocks = <&cpg CPG_MOD 514>; | |
720 | clock-names = "fck"; | |
721 | dmas = <&dmac1 0x22>, <&dmac2 0x22>; | |
722 | dma-names = "rx", "rx"; | |
723 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
724 | resets = <&cpg 514>; | |
725 | renesas,bonding = <&drif00>; | |
726 | status = "disabled"; | |
727 | }; | |
728 | ||
729 | drif10: rif@e6f60000 { | |
730 | compatible = "renesas,r8a7795-drif", | |
731 | "renesas,rcar-gen3-drif"; | |
732 | reg = <0 0xe6f60000 0 0x64>; | |
733 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
734 | clocks = <&cpg CPG_MOD 513>; | |
735 | clock-names = "fck"; | |
736 | dmas = <&dmac1 0x24>, <&dmac2 0x24>; | |
737 | dma-names = "rx", "rx"; | |
738 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
739 | resets = <&cpg 513>; | |
740 | renesas,bonding = <&drif11>; | |
741 | status = "disabled"; | |
742 | }; | |
743 | ||
744 | drif11: rif@e6f70000 { | |
745 | compatible = "renesas,r8a7795-drif", | |
746 | "renesas,rcar-gen3-drif"; | |
747 | reg = <0 0xe6f70000 0 0x64>; | |
748 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
749 | clocks = <&cpg CPG_MOD 512>; | |
750 | clock-names = "fck"; | |
751 | dmas = <&dmac1 0x26>, <&dmac2 0x26>; | |
752 | dma-names = "rx", "rx"; | |
753 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
754 | resets = <&cpg 512>; | |
755 | renesas,bonding = <&drif10>; | |
756 | status = "disabled"; | |
757 | }; | |
758 | ||
759 | drif20: rif@e6f80000 { | |
760 | compatible = "renesas,r8a7795-drif", | |
761 | "renesas,rcar-gen3-drif"; | |
762 | reg = <0 0xe6f80000 0 0x64>; | |
763 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
764 | clocks = <&cpg CPG_MOD 511>; | |
765 | clock-names = "fck"; | |
766 | dmas = <&dmac1 0x28>, <&dmac2 0x28>; | |
767 | dma-names = "rx", "rx"; | |
768 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
769 | resets = <&cpg 511>; | |
770 | renesas,bonding = <&drif21>; | |
771 | status = "disabled"; | |
772 | }; | |
773 | ||
774 | drif21: rif@e6f90000 { | |
775 | compatible = "renesas,r8a7795-drif", | |
776 | "renesas,rcar-gen3-drif"; | |
777 | reg = <0 0xe6f90000 0 0x64>; | |
778 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
779 | clocks = <&cpg CPG_MOD 510>; | |
780 | clock-names = "fck"; | |
781 | dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; | |
782 | dma-names = "rx", "rx"; | |
783 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
784 | resets = <&cpg 510>; | |
785 | renesas,bonding = <&drif20>; | |
786 | status = "disabled"; | |
787 | }; | |
788 | ||
789 | drif30: rif@e6fa0000 { | |
790 | compatible = "renesas,r8a7795-drif", | |
791 | "renesas,rcar-gen3-drif"; | |
792 | reg = <0 0xe6fa0000 0 0x64>; | |
793 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
794 | clocks = <&cpg CPG_MOD 509>; | |
795 | clock-names = "fck"; | |
796 | dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; | |
797 | dma-names = "rx", "rx"; | |
798 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
799 | resets = <&cpg 509>; | |
800 | renesas,bonding = <&drif31>; | |
801 | status = "disabled"; | |
802 | }; | |
803 | ||
804 | drif31: rif@e6fb0000 { | |
805 | compatible = "renesas,r8a7795-drif", | |
806 | "renesas,rcar-gen3-drif"; | |
807 | reg = <0 0xe6fb0000 0 0x64>; | |
808 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
809 | clocks = <&cpg CPG_MOD 508>; | |
810 | clock-names = "fck"; | |
811 | dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; | |
812 | dma-names = "rx", "rx"; | |
813 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
814 | resets = <&cpg 508>; | |
815 | renesas,bonding = <&drif30>; | |
816 | status = "disabled"; | |
817 | }; | |
818 | ||
4157c472 MV |
819 | hscif0: serial@e6540000 { |
820 | compatible = "renesas,hscif-r8a7795", | |
821 | "renesas,rcar-gen3-hscif", | |
822 | "renesas,hscif"; | |
823 | reg = <0 0xe6540000 0 96>; | |
824 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
825 | clocks = <&cpg CPG_MOD 520>, | |
826 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
827 | <&scif_clk>; | |
828 | clock-names = "fck", "brg_int", "scif_clk"; | |
829 | dmas = <&dmac1 0x31>, <&dmac1 0x30>; | |
830 | dma-names = "tx", "rx"; | |
831 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
832 | resets = <&cpg 520>; | |
833 | status = "disabled"; | |
834 | }; | |
835 | ||
836 | hscif1: serial@e6550000 { | |
837 | compatible = "renesas,hscif-r8a7795", | |
838 | "renesas,rcar-gen3-hscif", | |
839 | "renesas,hscif"; | |
840 | reg = <0 0xe6550000 0 96>; | |
841 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
842 | clocks = <&cpg CPG_MOD 519>, | |
843 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
844 | <&scif_clk>; | |
845 | clock-names = "fck", "brg_int", "scif_clk"; | |
846 | dmas = <&dmac1 0x33>, <&dmac1 0x32>; | |
847 | dma-names = "tx", "rx"; | |
848 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
849 | resets = <&cpg 519>; | |
850 | status = "disabled"; | |
851 | }; | |
852 | ||
853 | hscif2: serial@e6560000 { | |
854 | compatible = "renesas,hscif-r8a7795", | |
855 | "renesas,rcar-gen3-hscif", | |
856 | "renesas,hscif"; | |
857 | reg = <0 0xe6560000 0 96>; | |
858 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
859 | clocks = <&cpg CPG_MOD 518>, | |
860 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
861 | <&scif_clk>; | |
862 | clock-names = "fck", "brg_int", "scif_clk"; | |
863 | dmas = <&dmac1 0x35>, <&dmac1 0x34>; | |
864 | dma-names = "tx", "rx"; | |
865 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
866 | resets = <&cpg 518>; | |
867 | status = "disabled"; | |
868 | }; | |
869 | ||
870 | hscif3: serial@e66a0000 { | |
871 | compatible = "renesas,hscif-r8a7795", | |
872 | "renesas,rcar-gen3-hscif", | |
873 | "renesas,hscif"; | |
874 | reg = <0 0xe66a0000 0 96>; | |
875 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
876 | clocks = <&cpg CPG_MOD 517>, | |
877 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
878 | <&scif_clk>; | |
879 | clock-names = "fck", "brg_int", "scif_clk"; | |
880 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
881 | dma-names = "tx", "rx"; | |
882 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
883 | resets = <&cpg 517>; | |
884 | status = "disabled"; | |
885 | }; | |
886 | ||
887 | hscif4: serial@e66b0000 { | |
888 | compatible = "renesas,hscif-r8a7795", | |
889 | "renesas,rcar-gen3-hscif", | |
890 | "renesas,hscif"; | |
891 | reg = <0 0xe66b0000 0 96>; | |
892 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
893 | clocks = <&cpg CPG_MOD 516>, | |
894 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
895 | <&scif_clk>; | |
896 | clock-names = "fck", "brg_int", "scif_clk"; | |
897 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; | |
898 | dma-names = "tx", "rx"; | |
899 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
900 | resets = <&cpg 516>; | |
901 | status = "disabled"; | |
902 | }; | |
903 | ||
62b2bb53 MV |
904 | msiof0: spi@e6e90000 { |
905 | compatible = "renesas,msiof-r8a7795", | |
906 | "renesas,rcar-gen3-msiof"; | |
907 | reg = <0 0xe6e90000 0 0x0064>; | |
908 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
909 | clocks = <&cpg CPG_MOD 211>; | |
910 | dmas = <&dmac1 0x41>, <&dmac1 0x40>, | |
911 | <&dmac2 0x41>, <&dmac2 0x40>; | |
912 | dma-names = "tx", "rx", "tx", "rx"; | |
913 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
914 | resets = <&cpg 211>; | |
915 | #address-cells = <1>; | |
916 | #size-cells = <0>; | |
917 | status = "disabled"; | |
918 | }; | |
919 | ||
920 | msiof1: spi@e6ea0000 { | |
921 | compatible = "renesas,msiof-r8a7795", | |
922 | "renesas,rcar-gen3-msiof"; | |
923 | reg = <0 0xe6ea0000 0 0x0064>; | |
924 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; | |
925 | clocks = <&cpg CPG_MOD 210>; | |
926 | dmas = <&dmac1 0x43>, <&dmac1 0x42>, | |
927 | <&dmac2 0x43>, <&dmac2 0x42>; | |
928 | dma-names = "tx", "rx", "tx", "rx"; | |
929 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
930 | resets = <&cpg 210>; | |
931 | #address-cells = <1>; | |
932 | #size-cells = <0>; | |
933 | status = "disabled"; | |
934 | }; | |
935 | ||
936 | msiof2: spi@e6c00000 { | |
937 | compatible = "renesas,msiof-r8a7795", | |
938 | "renesas,rcar-gen3-msiof"; | |
939 | reg = <0 0xe6c00000 0 0x0064>; | |
940 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
941 | clocks = <&cpg CPG_MOD 209>; | |
942 | dmas = <&dmac0 0x45>, <&dmac0 0x44>; | |
943 | dma-names = "tx", "rx"; | |
944 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
945 | resets = <&cpg 209>; | |
946 | #address-cells = <1>; | |
947 | #size-cells = <0>; | |
948 | status = "disabled"; | |
949 | }; | |
950 | ||
951 | msiof3: spi@e6c10000 { | |
952 | compatible = "renesas,msiof-r8a7795", | |
953 | "renesas,rcar-gen3-msiof"; | |
954 | reg = <0 0xe6c10000 0 0x0064>; | |
955 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; | |
956 | clocks = <&cpg CPG_MOD 208>; | |
957 | dmas = <&dmac0 0x47>, <&dmac0 0x46>; | |
958 | dma-names = "tx", "rx"; | |
959 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
960 | resets = <&cpg 208>; | |
961 | #address-cells = <1>; | |
962 | #size-cells = <0>; | |
963 | status = "disabled"; | |
964 | }; | |
965 | ||
4157c472 MV |
966 | scif0: serial@e6e60000 { |
967 | compatible = "renesas,scif-r8a7795", | |
968 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
969 | reg = <0 0xe6e60000 0 64>; | |
970 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
971 | clocks = <&cpg CPG_MOD 207>, | |
972 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
973 | <&scif_clk>; | |
974 | clock-names = "fck", "brg_int", "scif_clk"; | |
975 | dmas = <&dmac1 0x51>, <&dmac1 0x50>; | |
976 | dma-names = "tx", "rx"; | |
977 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
978 | resets = <&cpg 207>; | |
979 | status = "disabled"; | |
980 | }; | |
981 | ||
982 | scif1: serial@e6e68000 { | |
983 | compatible = "renesas,scif-r8a7795", | |
984 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
985 | reg = <0 0xe6e68000 0 64>; | |
986 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
987 | clocks = <&cpg CPG_MOD 206>, | |
988 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
989 | <&scif_clk>; | |
990 | clock-names = "fck", "brg_int", "scif_clk"; | |
991 | dmas = <&dmac1 0x53>, <&dmac1 0x52>; | |
992 | dma-names = "tx", "rx"; | |
993 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
994 | resets = <&cpg 206>; | |
995 | status = "disabled"; | |
996 | }; | |
997 | ||
998 | scif2: serial@e6e88000 { | |
999 | compatible = "renesas,scif-r8a7795", | |
1000 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1001 | reg = <0 0xe6e88000 0 64>; | |
1002 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
1003 | clocks = <&cpg CPG_MOD 310>, | |
1004 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
1005 | <&scif_clk>; | |
1006 | clock-names = "fck", "brg_int", "scif_clk"; | |
1007 | dmas = <&dmac1 0x13>, <&dmac1 0x12>; | |
1008 | dma-names = "tx", "rx"; | |
1009 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1010 | resets = <&cpg 310>; | |
1011 | status = "disabled"; | |
1012 | }; | |
1013 | ||
1014 | scif3: serial@e6c50000 { | |
1015 | compatible = "renesas,scif-r8a7795", | |
1016 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1017 | reg = <0 0xe6c50000 0 64>; | |
1018 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
1019 | clocks = <&cpg CPG_MOD 204>, | |
1020 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
1021 | <&scif_clk>; | |
1022 | clock-names = "fck", "brg_int", "scif_clk"; | |
1023 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
1024 | dma-names = "tx", "rx"; | |
1025 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1026 | resets = <&cpg 204>; | |
1027 | status = "disabled"; | |
1028 | }; | |
1029 | ||
1030 | scif4: serial@e6c40000 { | |
1031 | compatible = "renesas,scif-r8a7795", | |
1032 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1033 | reg = <0 0xe6c40000 0 64>; | |
1034 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
1035 | clocks = <&cpg CPG_MOD 203>, | |
1036 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
1037 | <&scif_clk>; | |
1038 | clock-names = "fck", "brg_int", "scif_clk"; | |
1039 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
1040 | dma-names = "tx", "rx"; | |
1041 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1042 | resets = <&cpg 203>; | |
1043 | status = "disabled"; | |
1044 | }; | |
1045 | ||
1046 | scif5: serial@e6f30000 { | |
1047 | compatible = "renesas,scif-r8a7795", | |
1048 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1049 | reg = <0 0xe6f30000 0 64>; | |
1050 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
1051 | clocks = <&cpg CPG_MOD 202>, | |
1052 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
1053 | <&scif_clk>; | |
1054 | clock-names = "fck", "brg_int", "scif_clk"; | |
1055 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; | |
1056 | dma-names = "tx", "rx"; | |
1057 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1058 | resets = <&cpg 202>; | |
1059 | status = "disabled"; | |
1060 | }; | |
1061 | ||
1062 | i2c_dvfs: i2c@e60b0000 { | |
1063 | #address-cells = <1>; | |
1064 | #size-cells = <0>; | |
1065 | compatible = "renesas,iic-r8a7795", | |
1066 | "renesas,rcar-gen3-iic", | |
1067 | "renesas,rmobile-iic"; | |
1068 | reg = <0 0xe60b0000 0 0x425>; | |
1069 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; | |
1070 | clocks = <&cpg CPG_MOD 926>; | |
1071 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1072 | resets = <&cpg 926>; | |
37a79081 MV |
1073 | dmas = <&dmac0 0x11>, <&dmac0 0x10>; |
1074 | dma-names = "tx", "rx"; | |
4157c472 MV |
1075 | status = "disabled"; |
1076 | }; | |
1077 | ||
1078 | i2c0: i2c@e6500000 { | |
1079 | #address-cells = <1>; | |
1080 | #size-cells = <0>; | |
1081 | compatible = "renesas,i2c-r8a7795", | |
1082 | "renesas,rcar-gen3-i2c"; | |
1083 | reg = <0 0xe6500000 0 0x40>; | |
1084 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
1085 | clocks = <&cpg CPG_MOD 931>; | |
1086 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1087 | resets = <&cpg 931>; | |
1088 | dmas = <&dmac1 0x91>, <&dmac1 0x90>; | |
1089 | dma-names = "tx", "rx"; | |
1090 | i2c-scl-internal-delay-ns = <110>; | |
1091 | status = "disabled"; | |
1092 | }; | |
1093 | ||
1094 | i2c1: i2c@e6508000 { | |
1095 | #address-cells = <1>; | |
1096 | #size-cells = <0>; | |
1097 | compatible = "renesas,i2c-r8a7795", | |
1098 | "renesas,rcar-gen3-i2c"; | |
1099 | reg = <0 0xe6508000 0 0x40>; | |
1100 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
1101 | clocks = <&cpg CPG_MOD 930>; | |
1102 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1103 | resets = <&cpg 930>; | |
1104 | dmas = <&dmac1 0x93>, <&dmac1 0x92>; | |
1105 | dma-names = "tx", "rx"; | |
1106 | i2c-scl-internal-delay-ns = <6>; | |
1107 | status = "disabled"; | |
1108 | }; | |
1109 | ||
1110 | i2c2: i2c@e6510000 { | |
1111 | #address-cells = <1>; | |
1112 | #size-cells = <0>; | |
1113 | compatible = "renesas,i2c-r8a7795", | |
1114 | "renesas,rcar-gen3-i2c"; | |
1115 | reg = <0 0xe6510000 0 0x40>; | |
1116 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
1117 | clocks = <&cpg CPG_MOD 929>; | |
1118 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1119 | resets = <&cpg 929>; | |
1120 | dmas = <&dmac1 0x95>, <&dmac1 0x94>; | |
1121 | dma-names = "tx", "rx"; | |
1122 | i2c-scl-internal-delay-ns = <6>; | |
1123 | status = "disabled"; | |
1124 | }; | |
1125 | ||
1126 | i2c3: i2c@e66d0000 { | |
1127 | #address-cells = <1>; | |
1128 | #size-cells = <0>; | |
1129 | compatible = "renesas,i2c-r8a7795", | |
1130 | "renesas,rcar-gen3-i2c"; | |
1131 | reg = <0 0xe66d0000 0 0x40>; | |
1132 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
1133 | clocks = <&cpg CPG_MOD 928>; | |
1134 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1135 | resets = <&cpg 928>; | |
1136 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; | |
1137 | dma-names = "tx", "rx"; | |
1138 | i2c-scl-internal-delay-ns = <110>; | |
1139 | status = "disabled"; | |
1140 | }; | |
1141 | ||
1142 | i2c4: i2c@e66d8000 { | |
1143 | #address-cells = <1>; | |
1144 | #size-cells = <0>; | |
1145 | compatible = "renesas,i2c-r8a7795", | |
1146 | "renesas,rcar-gen3-i2c"; | |
1147 | reg = <0 0xe66d8000 0 0x40>; | |
1148 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
1149 | clocks = <&cpg CPG_MOD 927>; | |
1150 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1151 | resets = <&cpg 927>; | |
1152 | dmas = <&dmac0 0x99>, <&dmac0 0x98>; | |
1153 | dma-names = "tx", "rx"; | |
1154 | i2c-scl-internal-delay-ns = <110>; | |
1155 | status = "disabled"; | |
1156 | }; | |
1157 | ||
1158 | i2c5: i2c@e66e0000 { | |
1159 | #address-cells = <1>; | |
1160 | #size-cells = <0>; | |
1161 | compatible = "renesas,i2c-r8a7795", | |
1162 | "renesas,rcar-gen3-i2c"; | |
1163 | reg = <0 0xe66e0000 0 0x40>; | |
1164 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
1165 | clocks = <&cpg CPG_MOD 919>; | |
1166 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1167 | resets = <&cpg 919>; | |
1168 | dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; | |
1169 | dma-names = "tx", "rx"; | |
1170 | i2c-scl-internal-delay-ns = <110>; | |
1171 | status = "disabled"; | |
1172 | }; | |
1173 | ||
1174 | i2c6: i2c@e66e8000 { | |
1175 | #address-cells = <1>; | |
1176 | #size-cells = <0>; | |
1177 | compatible = "renesas,i2c-r8a7795", | |
1178 | "renesas,rcar-gen3-i2c"; | |
1179 | reg = <0 0xe66e8000 0 0x40>; | |
1180 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
1181 | clocks = <&cpg CPG_MOD 918>; | |
1182 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1183 | resets = <&cpg 918>; | |
1184 | dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; | |
1185 | dma-names = "tx", "rx"; | |
1186 | i2c-scl-internal-delay-ns = <6>; | |
1187 | status = "disabled"; | |
1188 | }; | |
1189 | ||
1190 | pwm0: pwm@e6e30000 { | |
1191 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
1192 | reg = <0 0xe6e30000 0 0x8>; | |
1193 | clocks = <&cpg CPG_MOD 523>; | |
1194 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1195 | resets = <&cpg 523>; | |
1196 | #pwm-cells = <2>; | |
1197 | status = "disabled"; | |
1198 | }; | |
1199 | ||
1200 | pwm1: pwm@e6e31000 { | |
1201 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
1202 | reg = <0 0xe6e31000 0 0x8>; | |
1203 | clocks = <&cpg CPG_MOD 523>; | |
1204 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1205 | resets = <&cpg 523>; | |
1206 | #pwm-cells = <2>; | |
1207 | status = "disabled"; | |
1208 | }; | |
1209 | ||
1210 | pwm2: pwm@e6e32000 { | |
1211 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
1212 | reg = <0 0xe6e32000 0 0x8>; | |
1213 | clocks = <&cpg CPG_MOD 523>; | |
1214 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1215 | resets = <&cpg 523>; | |
1216 | #pwm-cells = <2>; | |
1217 | status = "disabled"; | |
1218 | }; | |
1219 | ||
1220 | pwm3: pwm@e6e33000 { | |
1221 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
1222 | reg = <0 0xe6e33000 0 0x8>; | |
1223 | clocks = <&cpg CPG_MOD 523>; | |
1224 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1225 | resets = <&cpg 523>; | |
1226 | #pwm-cells = <2>; | |
1227 | status = "disabled"; | |
1228 | }; | |
1229 | ||
1230 | pwm4: pwm@e6e34000 { | |
1231 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
1232 | reg = <0 0xe6e34000 0 0x8>; | |
1233 | clocks = <&cpg CPG_MOD 523>; | |
1234 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1235 | resets = <&cpg 523>; | |
1236 | #pwm-cells = <2>; | |
1237 | status = "disabled"; | |
1238 | }; | |
1239 | ||
1240 | pwm5: pwm@e6e35000 { | |
1241 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
1242 | reg = <0 0xe6e35000 0 0x8>; | |
1243 | clocks = <&cpg CPG_MOD 523>; | |
1244 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1245 | resets = <&cpg 523>; | |
1246 | #pwm-cells = <2>; | |
1247 | status = "disabled"; | |
1248 | }; | |
1249 | ||
1250 | pwm6: pwm@e6e36000 { | |
1251 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
1252 | reg = <0 0xe6e36000 0 0x8>; | |
1253 | clocks = <&cpg CPG_MOD 523>; | |
1254 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1255 | resets = <&cpg 523>; | |
1256 | #pwm-cells = <2>; | |
1257 | status = "disabled"; | |
1258 | }; | |
1259 | ||
1260 | rcar_sound: sound@ec500000 { | |
1261 | /* | |
1262 | * #sound-dai-cells is required | |
1263 | * | |
1264 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
1265 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
1266 | */ | |
1267 | /* | |
1268 | * #clock-cells is required for audio_clkout0/1/2/3 | |
1269 | * | |
1270 | * clkout : #clock-cells = <0>; <&rcar_sound>; | |
1271 | * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; | |
1272 | */ | |
1273 | compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; | |
1274 | reg = <0 0xec500000 0 0x1000>, /* SCU */ | |
1275 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1276 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
1277 | <0 0xec541000 0 0x280>, /* SSI */ | |
1278 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ | |
1279 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
1280 | ||
1281 | clocks = <&cpg CPG_MOD 1005>, | |
1282 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
1283 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
1284 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
1285 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
1286 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
1287 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, | |
1288 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
1289 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
1290 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
1291 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
1292 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
1293 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
1294 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, | |
1295 | <&audio_clk_a>, <&audio_clk_b>, | |
1296 | <&audio_clk_c>, | |
1297 | <&cpg CPG_CORE R8A7795_CLK_S0D4>; | |
1298 | clock-names = "ssi-all", | |
1299 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
1300 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
1301 | "ssi.1", "ssi.0", | |
1302 | "src.9", "src.8", "src.7", "src.6", | |
1303 | "src.5", "src.4", "src.3", "src.2", | |
1304 | "src.1", "src.0", | |
1305 | "mix.1", "mix.0", | |
1306 | "ctu.1", "ctu.0", | |
1307 | "dvc.0", "dvc.1", | |
1308 | "clk_a", "clk_b", "clk_c", "clk_i"; | |
1309 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
37a79081 MV |
1310 | resets = <&cpg 1005>, |
1311 | <&cpg 1006>, <&cpg 1007>, | |
1312 | <&cpg 1008>, <&cpg 1009>, | |
1313 | <&cpg 1010>, <&cpg 1011>, | |
1314 | <&cpg 1012>, <&cpg 1013>, | |
1315 | <&cpg 1014>, <&cpg 1015>; | |
1316 | reset-names = "ssi-all", | |
1317 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
1318 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
1319 | "ssi.1", "ssi.0"; | |
4157c472 MV |
1320 | status = "disabled"; |
1321 | ||
1322 | rcar_sound,dvc { | |
1323 | dvc0: dvc-0 { | |
1324 | dmas = <&audma1 0xbc>; | |
1325 | dma-names = "tx"; | |
1326 | }; | |
1327 | dvc1: dvc-1 { | |
1328 | dmas = <&audma1 0xbe>; | |
1329 | dma-names = "tx"; | |
1330 | }; | |
1331 | }; | |
1332 | ||
1333 | rcar_sound,mix { | |
1334 | mix0: mix-0 { }; | |
1335 | mix1: mix-1 { }; | |
1336 | }; | |
1337 | ||
1338 | rcar_sound,ctu { | |
1339 | ctu00: ctu-0 { }; | |
1340 | ctu01: ctu-1 { }; | |
1341 | ctu02: ctu-2 { }; | |
1342 | ctu03: ctu-3 { }; | |
1343 | ctu10: ctu-4 { }; | |
1344 | ctu11: ctu-5 { }; | |
1345 | ctu12: ctu-6 { }; | |
1346 | ctu13: ctu-7 { }; | |
1347 | }; | |
1348 | ||
1349 | rcar_sound,src { | |
1350 | src0: src-0 { | |
1351 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; | |
1352 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
1353 | dma-names = "rx", "tx"; | |
1354 | }; | |
1355 | src1: src-1 { | |
1356 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
1357 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
1358 | dma-names = "rx", "tx"; | |
1359 | }; | |
1360 | src2: src-2 { | |
1361 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
1362 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
1363 | dma-names = "rx", "tx"; | |
1364 | }; | |
1365 | src3: src-3 { | |
1366 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
1367 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
1368 | dma-names = "rx", "tx"; | |
1369 | }; | |
1370 | src4: src-4 { | |
1371 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
1372 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
1373 | dma-names = "rx", "tx"; | |
1374 | }; | |
1375 | src5: src-5 { | |
1376 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
1377 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
1378 | dma-names = "rx", "tx"; | |
1379 | }; | |
1380 | src6: src-6 { | |
1381 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
1382 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
1383 | dma-names = "rx", "tx"; | |
1384 | }; | |
1385 | src7: src-7 { | |
1386 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
1387 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
1388 | dma-names = "rx", "tx"; | |
1389 | }; | |
1390 | src8: src-8 { | |
1391 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; | |
1392 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
1393 | dma-names = "rx", "tx"; | |
1394 | }; | |
1395 | src9: src-9 { | |
1396 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; | |
1397 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
1398 | dma-names = "rx", "tx"; | |
1399 | }; | |
1400 | }; | |
1401 | ||
1402 | rcar_sound,ssi { | |
1403 | ssi0: ssi-0 { | |
1404 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
1405 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; | |
1406 | dma-names = "rx", "tx", "rxu", "txu"; | |
1407 | }; | |
1408 | ssi1: ssi-1 { | |
1409 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
1410 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; | |
1411 | dma-names = "rx", "tx", "rxu", "txu"; | |
1412 | }; | |
1413 | ssi2: ssi-2 { | |
1414 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; | |
1415 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; | |
1416 | dma-names = "rx", "tx", "rxu", "txu"; | |
1417 | }; | |
1418 | ssi3: ssi-3 { | |
1419 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
1420 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; | |
1421 | dma-names = "rx", "tx", "rxu", "txu"; | |
1422 | }; | |
1423 | ssi4: ssi-4 { | |
1424 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; | |
1425 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; | |
1426 | dma-names = "rx", "tx", "rxu", "txu"; | |
1427 | }; | |
1428 | ssi5: ssi-5 { | |
1429 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; | |
1430 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; | |
1431 | dma-names = "rx", "tx", "rxu", "txu"; | |
1432 | }; | |
1433 | ssi6: ssi-6 { | |
1434 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; | |
1435 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; | |
1436 | dma-names = "rx", "tx", "rxu", "txu"; | |
1437 | }; | |
1438 | ssi7: ssi-7 { | |
1439 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; | |
1440 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; | |
1441 | dma-names = "rx", "tx", "rxu", "txu"; | |
1442 | }; | |
1443 | ssi8: ssi-8 { | |
1444 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; | |
1445 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; | |
1446 | dma-names = "rx", "tx", "rxu", "txu"; | |
1447 | }; | |
1448 | ssi9: ssi-9 { | |
1449 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; | |
1450 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; | |
1451 | dma-names = "rx", "tx", "rxu", "txu"; | |
1452 | }; | |
1453 | }; | |
1454 | }; | |
1455 | ||
1456 | sata: sata@ee300000 { | |
62b2bb53 MV |
1457 | compatible = "renesas,sata-r8a7795", |
1458 | "renesas,rcar-gen3-sata"; | |
4157c472 MV |
1459 | reg = <0 0xee300000 0 0x200000>; |
1460 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
1461 | clocks = <&cpg CPG_MOD 815>; | |
1462 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1463 | resets = <&cpg 815>; | |
1464 | status = "disabled"; | |
1465 | }; | |
1466 | ||
1467 | xhci0: usb@ee000000 { | |
1468 | compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; | |
1469 | reg = <0 0xee000000 0 0xc00>; | |
1470 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
1471 | clocks = <&cpg CPG_MOD 328>; | |
1472 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1473 | resets = <&cpg 328>; | |
1474 | status = "disabled"; | |
1475 | }; | |
1476 | ||
4157c472 MV |
1477 | usb_dmac0: dma-controller@e65a0000 { |
1478 | compatible = "renesas,r8a7795-usb-dmac", | |
1479 | "renesas,usb-dmac"; | |
1480 | reg = <0 0xe65a0000 0 0x100>; | |
1481 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH | |
1482 | GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
1483 | interrupt-names = "ch0", "ch1"; | |
1484 | clocks = <&cpg CPG_MOD 330>; | |
1485 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1486 | resets = <&cpg 330>; | |
1487 | #dma-cells = <1>; | |
1488 | dma-channels = <2>; | |
1489 | }; | |
1490 | ||
1491 | usb_dmac1: dma-controller@e65b0000 { | |
1492 | compatible = "renesas,r8a7795-usb-dmac", | |
1493 | "renesas,usb-dmac"; | |
1494 | reg = <0 0xe65b0000 0 0x100>; | |
1495 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH | |
1496 | GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
1497 | interrupt-names = "ch0", "ch1"; | |
1498 | clocks = <&cpg CPG_MOD 331>; | |
1499 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1500 | resets = <&cpg 331>; | |
1501 | #dma-cells = <1>; | |
1502 | dma-channels = <2>; | |
1503 | }; | |
1504 | ||
62b2bb53 MV |
1505 | usb_dmac2: dma-controller@e6460000 { |
1506 | compatible = "renesas,r8a7795-usb-dmac", | |
1507 | "renesas,usb-dmac"; | |
1508 | reg = <0 0xe6460000 0 0x100>; | |
1509 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH | |
1510 | GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
1511 | interrupt-names = "ch0", "ch1"; | |
1512 | clocks = <&cpg CPG_MOD 326>; | |
1513 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1514 | resets = <&cpg 326>; | |
1515 | #dma-cells = <1>; | |
1516 | dma-channels = <2>; | |
1517 | }; | |
1518 | ||
1519 | usb_dmac3: dma-controller@e6470000 { | |
1520 | compatible = "renesas,r8a7795-usb-dmac", | |
1521 | "renesas,usb-dmac"; | |
1522 | reg = <0 0xe6470000 0 0x100>; | |
1523 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH | |
1524 | GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
1525 | interrupt-names = "ch0", "ch1"; | |
1526 | clocks = <&cpg CPG_MOD 329>; | |
1527 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1528 | resets = <&cpg 329>; | |
1529 | #dma-cells = <1>; | |
1530 | dma-channels = <2>; | |
1531 | }; | |
1532 | ||
4157c472 MV |
1533 | sdhi0: sd@ee100000 { |
1534 | compatible = "renesas,sdhi-r8a7795"; | |
1535 | reg = <0 0xee100000 0 0x2000>; | |
1536 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; | |
1537 | clocks = <&cpg CPG_MOD 314>; | |
1538 | max-frequency = <200000000>; | |
1539 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1540 | resets = <&cpg 314>; | |
1541 | status = "disabled"; | |
1542 | }; | |
1543 | ||
1544 | sdhi1: sd@ee120000 { | |
1545 | compatible = "renesas,sdhi-r8a7795"; | |
1546 | reg = <0 0xee120000 0 0x2000>; | |
1547 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; | |
1548 | clocks = <&cpg CPG_MOD 313>; | |
1549 | max-frequency = <200000000>; | |
1550 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1551 | resets = <&cpg 313>; | |
1552 | status = "disabled"; | |
1553 | }; | |
1554 | ||
1555 | sdhi2: sd@ee140000 { | |
1556 | compatible = "renesas,sdhi-r8a7795"; | |
1557 | reg = <0 0xee140000 0 0x2000>; | |
1558 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; | |
1559 | clocks = <&cpg CPG_MOD 312>; | |
1560 | max-frequency = <200000000>; | |
1561 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1562 | resets = <&cpg 312>; | |
1563 | status = "disabled"; | |
1564 | }; | |
1565 | ||
1566 | sdhi3: sd@ee160000 { | |
1567 | compatible = "renesas,sdhi-r8a7795"; | |
1568 | reg = <0 0xee160000 0 0x2000>; | |
1569 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; | |
1570 | clocks = <&cpg CPG_MOD 311>; | |
1571 | max-frequency = <200000000>; | |
1572 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1573 | resets = <&cpg 311>; | |
1574 | status = "disabled"; | |
1575 | }; | |
1576 | ||
1577 | usb2_phy0: usb-phy@ee080200 { | |
1578 | compatible = "renesas,usb2-phy-r8a7795", | |
1579 | "renesas,rcar-gen3-usb2-phy"; | |
1580 | reg = <0 0xee080200 0 0x700>; | |
1581 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
1582 | clocks = <&cpg CPG_MOD 703>; | |
1583 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1584 | resets = <&cpg 703>; | |
1585 | #phy-cells = <0>; | |
1586 | status = "disabled"; | |
1587 | }; | |
1588 | ||
1589 | usb2_phy1: usb-phy@ee0a0200 { | |
1590 | compatible = "renesas,usb2-phy-r8a7795", | |
1591 | "renesas,rcar-gen3-usb2-phy"; | |
1592 | reg = <0 0xee0a0200 0 0x700>; | |
1593 | clocks = <&cpg CPG_MOD 702>; | |
1594 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1595 | resets = <&cpg 702>; | |
1596 | #phy-cells = <0>; | |
1597 | status = "disabled"; | |
1598 | }; | |
1599 | ||
1600 | usb2_phy2: usb-phy@ee0c0200 { | |
1601 | compatible = "renesas,usb2-phy-r8a7795", | |
1602 | "renesas,rcar-gen3-usb2-phy"; | |
1603 | reg = <0 0xee0c0200 0 0x700>; | |
1604 | clocks = <&cpg CPG_MOD 701>; | |
1605 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1606 | resets = <&cpg 701>; | |
1607 | #phy-cells = <0>; | |
1608 | status = "disabled"; | |
1609 | }; | |
1610 | ||
62b2bb53 MV |
1611 | usb2_phy3: usb-phy@ee0e0200 { |
1612 | compatible = "renesas,usb2-phy-r8a7795", | |
1613 | "renesas,rcar-gen3-usb2-phy"; | |
1614 | reg = <0 0xee0e0200 0 0x700>; | |
1615 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
1616 | clocks = <&cpg CPG_MOD 700>; | |
1617 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1618 | resets = <&cpg 700>; | |
1619 | #phy-cells = <0>; | |
1620 | status = "disabled"; | |
1621 | }; | |
1622 | ||
4157c472 MV |
1623 | ehci0: usb@ee080100 { |
1624 | compatible = "generic-ehci"; | |
1625 | reg = <0 0xee080100 0 0x100>; | |
1626 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
1627 | clocks = <&cpg CPG_MOD 703>; | |
1628 | phys = <&usb2_phy0>; | |
1629 | phy-names = "usb"; | |
62b2bb53 | 1630 | companion = <&ohci0>; |
4157c472 MV |
1631 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
1632 | resets = <&cpg 703>; | |
1633 | status = "disabled"; | |
1634 | }; | |
1635 | ||
1636 | ehci1: usb@ee0a0100 { | |
1637 | compatible = "generic-ehci"; | |
1638 | reg = <0 0xee0a0100 0 0x100>; | |
1639 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
1640 | clocks = <&cpg CPG_MOD 702>; | |
1641 | phys = <&usb2_phy1>; | |
1642 | phy-names = "usb"; | |
62b2bb53 | 1643 | companion = <&ohci1>; |
4157c472 MV |
1644 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
1645 | resets = <&cpg 702>; | |
1646 | status = "disabled"; | |
1647 | }; | |
1648 | ||
1649 | ehci2: usb@ee0c0100 { | |
1650 | compatible = "generic-ehci"; | |
1651 | reg = <0 0xee0c0100 0 0x100>; | |
1652 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
1653 | clocks = <&cpg CPG_MOD 701>; | |
1654 | phys = <&usb2_phy2>; | |
1655 | phy-names = "usb"; | |
62b2bb53 | 1656 | companion = <&ohci2>; |
4157c472 MV |
1657 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
1658 | resets = <&cpg 701>; | |
1659 | status = "disabled"; | |
1660 | }; | |
1661 | ||
62b2bb53 MV |
1662 | ehci3: usb@ee0e0100 { |
1663 | compatible = "generic-ehci"; | |
1664 | reg = <0 0xee0e0100 0 0x100>; | |
1665 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
1666 | clocks = <&cpg CPG_MOD 700>; | |
1667 | phys = <&usb2_phy3>; | |
1668 | phy-names = "usb"; | |
1669 | companion = <&ohci3>; | |
1670 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1671 | resets = <&cpg 700>; | |
1672 | status = "disabled"; | |
1673 | }; | |
1674 | ||
4157c472 MV |
1675 | ohci0: usb@ee080000 { |
1676 | compatible = "generic-ohci"; | |
1677 | reg = <0 0xee080000 0 0x100>; | |
1678 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
1679 | clocks = <&cpg CPG_MOD 703>; | |
1680 | phys = <&usb2_phy0>; | |
1681 | phy-names = "usb"; | |
1682 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1683 | resets = <&cpg 703>; | |
1684 | status = "disabled"; | |
1685 | }; | |
1686 | ||
1687 | ohci1: usb@ee0a0000 { | |
1688 | compatible = "generic-ohci"; | |
1689 | reg = <0 0xee0a0000 0 0x100>; | |
1690 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
1691 | clocks = <&cpg CPG_MOD 702>; | |
1692 | phys = <&usb2_phy1>; | |
1693 | phy-names = "usb"; | |
1694 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1695 | resets = <&cpg 702>; | |
1696 | status = "disabled"; | |
1697 | }; | |
1698 | ||
1699 | ohci2: usb@ee0c0000 { | |
1700 | compatible = "generic-ohci"; | |
1701 | reg = <0 0xee0c0000 0 0x100>; | |
1702 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
1703 | clocks = <&cpg CPG_MOD 701>; | |
1704 | phys = <&usb2_phy2>; | |
1705 | phy-names = "usb"; | |
1706 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1707 | resets = <&cpg 701>; | |
1708 | status = "disabled"; | |
1709 | }; | |
1710 | ||
62b2bb53 MV |
1711 | ohci3: usb@ee0e0000 { |
1712 | compatible = "generic-ohci"; | |
1713 | reg = <0 0xee0e0000 0 0x100>; | |
1714 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
1715 | clocks = <&cpg CPG_MOD 700>; | |
1716 | phys = <&usb2_phy3>; | |
1717 | phy-names = "usb"; | |
1718 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1719 | resets = <&cpg 700>; | |
1720 | status = "disabled"; | |
1721 | }; | |
1722 | ||
4157c472 MV |
1723 | hsusb: usb@e6590000 { |
1724 | compatible = "renesas,usbhs-r8a7795", | |
1725 | "renesas,rcar-gen3-usbhs"; | |
1726 | reg = <0 0xe6590000 0 0x100>; | |
1727 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
1728 | clocks = <&cpg CPG_MOD 704>; | |
1729 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, | |
1730 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
1731 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
1732 | renesas,buswait = <11>; | |
1733 | phys = <&usb2_phy0>; | |
1734 | phy-names = "usb"; | |
1735 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1736 | resets = <&cpg 704>; | |
1737 | status = "disabled"; | |
1738 | }; | |
1739 | ||
62b2bb53 MV |
1740 | hsusb3: usb@e659c000 { |
1741 | compatible = "renesas,usbhs-r8a7795", | |
1742 | "renesas,rcar-gen3-usbhs"; | |
1743 | reg = <0 0xe659c000 0 0x100>; | |
1744 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
1745 | clocks = <&cpg CPG_MOD 705>; | |
1746 | dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, | |
1747 | <&usb_dmac3 0>, <&usb_dmac3 1>; | |
1748 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
1749 | renesas,buswait = <11>; | |
1750 | phys = <&usb2_phy3>; | |
1751 | phy-names = "usb"; | |
1752 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1753 | resets = <&cpg 705>; | |
1754 | status = "disabled"; | |
1755 | }; | |
1756 | ||
4157c472 MV |
1757 | pciec0: pcie@fe000000 { |
1758 | compatible = "renesas,pcie-r8a7795", | |
1759 | "renesas,pcie-rcar-gen3"; | |
1760 | reg = <0 0xfe000000 0 0x80000>; | |
1761 | #address-cells = <3>; | |
1762 | #size-cells = <2>; | |
1763 | bus-range = <0x00 0xff>; | |
1764 | device_type = "pci"; | |
1765 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
1766 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
1767 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
1768 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
1769 | /* Map all possible DDR as inbound ranges */ | |
1770 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; | |
1771 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
1772 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
1773 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
1774 | #interrupt-cells = <1>; | |
1775 | interrupt-map-mask = <0 0 0 0>; | |
1776 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
1777 | clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; | |
1778 | clock-names = "pcie", "pcie_bus"; | |
1779 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1780 | resets = <&cpg 319>; | |
1781 | status = "disabled"; | |
1782 | }; | |
1783 | ||
1784 | pciec1: pcie@ee800000 { | |
1785 | compatible = "renesas,pcie-r8a7795", | |
1786 | "renesas,pcie-rcar-gen3"; | |
1787 | reg = <0 0xee800000 0 0x80000>; | |
1788 | #address-cells = <3>; | |
1789 | #size-cells = <2>; | |
1790 | bus-range = <0x00 0xff>; | |
1791 | device_type = "pci"; | |
1792 | ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 | |
1793 | 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 | |
1794 | 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 | |
1795 | 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; | |
1796 | /* Map all possible DDR as inbound ranges */ | |
1797 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; | |
1798 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, | |
1799 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
1800 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
1801 | #interrupt-cells = <1>; | |
1802 | interrupt-map-mask = <0 0 0 0>; | |
1803 | interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
1804 | clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; | |
1805 | clock-names = "pcie", "pcie_bus"; | |
1806 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1807 | resets = <&cpg 318>; | |
1808 | status = "disabled"; | |
1809 | }; | |
1810 | ||
62b2bb53 MV |
1811 | imr-lx4@fe860000 { |
1812 | compatible = "renesas,r8a7795-imr-lx4", | |
1813 | "renesas,imr-lx4"; | |
1814 | reg = <0 0xfe860000 0 0x2000>; | |
1815 | interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; | |
1816 | clocks = <&cpg CPG_MOD 823>; | |
1817 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
1818 | resets = <&cpg 823>; | |
1819 | }; | |
1820 | ||
1821 | imr-lx4@fe870000 { | |
1822 | compatible = "renesas,r8a7795-imr-lx4", | |
1823 | "renesas,imr-lx4"; | |
1824 | reg = <0 0xfe870000 0 0x2000>; | |
1825 | interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | |
1826 | clocks = <&cpg CPG_MOD 822>; | |
1827 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
1828 | resets = <&cpg 822>; | |
1829 | }; | |
1830 | ||
1831 | imr-lx4@fe880000 { | |
1832 | compatible = "renesas,r8a7795-imr-lx4", | |
1833 | "renesas,imr-lx4"; | |
1834 | reg = <0 0xfe880000 0 0x2000>; | |
1835 | interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; | |
1836 | clocks = <&cpg CPG_MOD 821>; | |
1837 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
1838 | resets = <&cpg 821>; | |
1839 | }; | |
1840 | ||
1841 | imr-lx4@fe890000 { | |
1842 | compatible = "renesas,r8a7795-imr-lx4", | |
1843 | "renesas,imr-lx4"; | |
1844 | reg = <0 0xfe890000 0 0x2000>; | |
1845 | interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; | |
1846 | clocks = <&cpg CPG_MOD 820>; | |
1847 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
1848 | resets = <&cpg 820>; | |
1849 | }; | |
1850 | ||
4157c472 MV |
1851 | vspbc: vsp@fe920000 { |
1852 | compatible = "renesas,vsp2"; | |
1853 | reg = <0 0xfe920000 0 0x8000>; | |
1854 | interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; | |
1855 | clocks = <&cpg CPG_MOD 624>; | |
1856 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1857 | resets = <&cpg 624>; | |
1858 | ||
1859 | renesas,fcp = <&fcpvb1>; | |
1860 | }; | |
1861 | ||
1862 | fcpvb1: fcp@fe92f000 { | |
1863 | compatible = "renesas,fcpv"; | |
1864 | reg = <0 0xfe92f000 0 0x200>; | |
1865 | clocks = <&cpg CPG_MOD 606>; | |
1866 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1867 | resets = <&cpg 606>; | |
1868 | }; | |
1869 | ||
1870 | fcpf0: fcp@fe950000 { | |
1871 | compatible = "renesas,fcpf"; | |
1872 | reg = <0 0xfe950000 0 0x200>; | |
1873 | clocks = <&cpg CPG_MOD 615>; | |
1874 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1875 | resets = <&cpg 615>; | |
1876 | }; | |
1877 | ||
1878 | fcpf1: fcp@fe951000 { | |
1879 | compatible = "renesas,fcpf"; | |
1880 | reg = <0 0xfe951000 0 0x200>; | |
1881 | clocks = <&cpg CPG_MOD 614>; | |
1882 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1883 | resets = <&cpg 614>; | |
1884 | }; | |
1885 | ||
4157c472 MV |
1886 | vspbd: vsp@fe960000 { |
1887 | compatible = "renesas,vsp2"; | |
1888 | reg = <0 0xfe960000 0 0x8000>; | |
1889 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; | |
1890 | clocks = <&cpg CPG_MOD 626>; | |
1891 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1892 | resets = <&cpg 626>; | |
1893 | ||
1894 | renesas,fcp = <&fcpvb0>; | |
1895 | }; | |
1896 | ||
1897 | fcpvb0: fcp@fe96f000 { | |
1898 | compatible = "renesas,fcpv"; | |
1899 | reg = <0 0xfe96f000 0 0x200>; | |
1900 | clocks = <&cpg CPG_MOD 607>; | |
1901 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1902 | resets = <&cpg 607>; | |
1903 | }; | |
1904 | ||
1905 | vspi0: vsp@fe9a0000 { | |
1906 | compatible = "renesas,vsp2"; | |
1907 | reg = <0 0xfe9a0000 0 0x8000>; | |
1908 | interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; | |
1909 | clocks = <&cpg CPG_MOD 631>; | |
1910 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1911 | resets = <&cpg 631>; | |
1912 | ||
1913 | renesas,fcp = <&fcpvi0>; | |
1914 | }; | |
1915 | ||
1916 | fcpvi0: fcp@fe9af000 { | |
1917 | compatible = "renesas,fcpv"; | |
1918 | reg = <0 0xfe9af000 0 0x200>; | |
1919 | clocks = <&cpg CPG_MOD 611>; | |
1920 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1921 | resets = <&cpg 611>; | |
1922 | }; | |
1923 | ||
1924 | vspi1: vsp@fe9b0000 { | |
1925 | compatible = "renesas,vsp2"; | |
1926 | reg = <0 0xfe9b0000 0 0x8000>; | |
1927 | interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; | |
1928 | clocks = <&cpg CPG_MOD 630>; | |
1929 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1930 | resets = <&cpg 630>; | |
1931 | ||
1932 | renesas,fcp = <&fcpvi1>; | |
1933 | }; | |
1934 | ||
1935 | fcpvi1: fcp@fe9bf000 { | |
1936 | compatible = "renesas,fcpv"; | |
1937 | reg = <0 0xfe9bf000 0 0x200>; | |
1938 | clocks = <&cpg CPG_MOD 610>; | |
1939 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
1940 | resets = <&cpg 610>; | |
1941 | }; | |
1942 | ||
4157c472 MV |
1943 | vspd0: vsp@fea20000 { |
1944 | compatible = "renesas,vsp2"; | |
1945 | reg = <0 0xfea20000 0 0x4000>; | |
1946 | interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; | |
1947 | clocks = <&cpg CPG_MOD 623>; | |
1948 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1949 | resets = <&cpg 623>; | |
1950 | ||
1951 | renesas,fcp = <&fcpvd0>; | |
1952 | }; | |
1953 | ||
1954 | fcpvd0: fcp@fea27000 { | |
1955 | compatible = "renesas,fcpv"; | |
1956 | reg = <0 0xfea27000 0 0x200>; | |
1957 | clocks = <&cpg CPG_MOD 603>; | |
1958 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1959 | resets = <&cpg 603>; | |
1960 | }; | |
1961 | ||
1962 | vspd1: vsp@fea28000 { | |
1963 | compatible = "renesas,vsp2"; | |
1964 | reg = <0 0xfea28000 0 0x4000>; | |
1965 | interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; | |
1966 | clocks = <&cpg CPG_MOD 622>; | |
1967 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1968 | resets = <&cpg 622>; | |
1969 | ||
1970 | renesas,fcp = <&fcpvd1>; | |
1971 | }; | |
1972 | ||
1973 | fcpvd1: fcp@fea2f000 { | |
1974 | compatible = "renesas,fcpv"; | |
1975 | reg = <0 0xfea2f000 0 0x200>; | |
1976 | clocks = <&cpg CPG_MOD 602>; | |
1977 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1978 | resets = <&cpg 602>; | |
1979 | }; | |
1980 | ||
1981 | vspd2: vsp@fea30000 { | |
1982 | compatible = "renesas,vsp2"; | |
1983 | reg = <0 0xfea30000 0 0x4000>; | |
1984 | interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; | |
1985 | clocks = <&cpg CPG_MOD 621>; | |
1986 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1987 | resets = <&cpg 621>; | |
1988 | ||
1989 | renesas,fcp = <&fcpvd2>; | |
1990 | }; | |
1991 | ||
1992 | fcpvd2: fcp@fea37000 { | |
1993 | compatible = "renesas,fcpv"; | |
1994 | reg = <0 0xfea37000 0 0x200>; | |
1995 | clocks = <&cpg CPG_MOD 601>; | |
1996 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
1997 | resets = <&cpg 601>; | |
1998 | }; | |
1999 | ||
4157c472 MV |
2000 | fdp1@fe940000 { |
2001 | compatible = "renesas,fdp1"; | |
2002 | reg = <0 0xfe940000 0 0x2400>; | |
2003 | interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | |
2004 | clocks = <&cpg CPG_MOD 119>; | |
2005 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
2006 | resets = <&cpg 119>; | |
2007 | renesas,fcp = <&fcpf0>; | |
2008 | }; | |
2009 | ||
2010 | fdp1@fe944000 { | |
2011 | compatible = "renesas,fdp1"; | |
2012 | reg = <0 0xfe944000 0 0x2400>; | |
2013 | interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; | |
2014 | clocks = <&cpg CPG_MOD 118>; | |
2015 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
2016 | resets = <&cpg 118>; | |
2017 | renesas,fcp = <&fcpf1>; | |
2018 | }; | |
2019 | ||
37a79081 MV |
2020 | hdmi0: hdmi0@fead0000 { |
2021 | compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; | |
2022 | reg = <0 0xfead0000 0 0x10000>; | |
2023 | interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; | |
2024 | clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; | |
2025 | clock-names = "iahb", "isfr"; | |
2026 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
2027 | resets = <&cpg 729>; | |
2028 | status = "disabled"; | |
2029 | ||
2030 | ports { | |
2031 | #address-cells = <1>; | |
2032 | #size-cells = <0>; | |
2033 | port@0 { | |
2034 | reg = <0>; | |
2035 | dw_hdmi0_in: endpoint { | |
2036 | remote-endpoint = <&du_out_hdmi0>; | |
2037 | }; | |
2038 | }; | |
2039 | port@1 { | |
2040 | reg = <1>; | |
2041 | }; | |
2042 | }; | |
2043 | }; | |
2044 | ||
2045 | hdmi1: hdmi1@feae0000 { | |
2046 | compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; | |
2047 | reg = <0 0xfeae0000 0 0x10000>; | |
2048 | interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; | |
2049 | clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; | |
2050 | clock-names = "iahb", "isfr"; | |
2051 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
2052 | resets = <&cpg 728>; | |
2053 | status = "disabled"; | |
2054 | ||
2055 | ports { | |
2056 | #address-cells = <1>; | |
2057 | #size-cells = <0>; | |
2058 | port@0 { | |
2059 | reg = <0>; | |
2060 | dw_hdmi1_in: endpoint { | |
2061 | remote-endpoint = <&du_out_hdmi1>; | |
2062 | }; | |
2063 | }; | |
2064 | port@1 { | |
2065 | reg = <1>; | |
2066 | }; | |
2067 | }; | |
4157c472 MV |
2068 | }; |
2069 | ||
2070 | du: display@feb00000 { | |
62b2bb53 | 2071 | compatible = "renesas,du-r8a7795"; |
4157c472 MV |
2072 | reg = <0 0xfeb00000 0 0x80000>, |
2073 | <0 0xfeb90000 0 0x14>; | |
2074 | reg-names = "du", "lvds.0"; | |
2075 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, | |
2076 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, | |
2077 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, | |
2078 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; | |
2079 | clocks = <&cpg CPG_MOD 724>, | |
2080 | <&cpg CPG_MOD 723>, | |
2081 | <&cpg CPG_MOD 722>, | |
2082 | <&cpg CPG_MOD 721>, | |
2083 | <&cpg CPG_MOD 727>; | |
2084 | clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; | |
62b2bb53 | 2085 | vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; |
4157c472 MV |
2086 | status = "disabled"; |
2087 | ||
4157c472 MV |
2088 | ports { |
2089 | #address-cells = <1>; | |
2090 | #size-cells = <0>; | |
2091 | ||
2092 | port@0 { | |
2093 | reg = <0>; | |
2094 | du_out_rgb: endpoint { | |
2095 | }; | |
2096 | }; | |
2097 | port@1 { | |
2098 | reg = <1>; | |
2099 | du_out_hdmi0: endpoint { | |
37a79081 | 2100 | remote-endpoint = <&dw_hdmi0_in>; |
4157c472 MV |
2101 | }; |
2102 | }; | |
2103 | port@2 { | |
2104 | reg = <2>; | |
2105 | du_out_hdmi1: endpoint { | |
37a79081 | 2106 | remote-endpoint = <&dw_hdmi1_in>; |
4157c472 MV |
2107 | }; |
2108 | }; | |
2109 | port@3 { | |
2110 | reg = <3>; | |
2111 | du_out_lvds0: endpoint { | |
2112 | }; | |
2113 | }; | |
2114 | }; | |
2115 | }; | |
2116 | ||
2117 | tsc: thermal@e6198000 { | |
2118 | compatible = "renesas,r8a7795-thermal"; | |
2119 | reg = <0 0xe6198000 0 0x68>, | |
2120 | <0 0xe61a0000 0 0x5c>, | |
2121 | <0 0xe61a8000 0 0x5c>; | |
2122 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
2123 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
2124 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
2125 | clocks = <&cpg CPG_MOD 522>; | |
2126 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
2127 | resets = <&cpg 522>; | |
2128 | #thermal-sensor-cells = <1>; | |
2129 | status = "okay"; | |
2130 | }; | |
2131 | ||
2132 | thermal-zones { | |
2133 | sensor_thermal1: sensor-thermal1 { | |
2134 | polling-delay-passive = <250>; | |
2135 | polling-delay = <1000>; | |
2136 | thermal-sensors = <&tsc 0>; | |
2137 | ||
2138 | trips { | |
2139 | sensor1_crit: sensor1-crit { | |
2140 | temperature = <120000>; | |
2141 | hysteresis = <2000>; | |
2142 | type = "critical"; | |
2143 | }; | |
2144 | }; | |
2145 | }; | |
2146 | ||
2147 | sensor_thermal2: sensor-thermal2 { | |
2148 | polling-delay-passive = <250>; | |
2149 | polling-delay = <1000>; | |
2150 | thermal-sensors = <&tsc 1>; | |
2151 | ||
2152 | trips { | |
2153 | sensor2_crit: sensor2-crit { | |
2154 | temperature = <120000>; | |
2155 | hysteresis = <2000>; | |
2156 | type = "critical"; | |
2157 | }; | |
2158 | }; | |
2159 | }; | |
2160 | ||
2161 | sensor_thermal3: sensor-thermal3 { | |
2162 | polling-delay-passive = <250>; | |
2163 | polling-delay = <1000>; | |
2164 | thermal-sensors = <&tsc 2>; | |
2165 | ||
2166 | trips { | |
2167 | sensor3_crit: sensor3-crit { | |
2168 | temperature = <120000>; | |
2169 | hysteresis = <2000>; | |
2170 | type = "critical"; | |
2171 | }; | |
2172 | }; | |
2173 | }; | |
2174 | }; | |
2175 | }; | |
2176 | }; |