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4157c472 MV |
1 | /* |
2 | * Device Tree Source for the r8a7796 SoC | |
3 | * | |
4 | * Copyright (C) 2016 Renesas Electronics Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <dt-bindings/clock/r8a7796-cpg-mssr.h> | |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
13 | #include <dt-bindings/power/r8a7796-sysc.h> | |
14 | ||
15 | / { | |
16 | compatible = "renesas,r8a7796"; | |
17 | #address-cells = <2>; | |
18 | #size-cells = <2>; | |
19 | ||
20 | aliases { | |
21 | i2c0 = &i2c0; | |
22 | i2c1 = &i2c1; | |
23 | i2c2 = &i2c2; | |
24 | i2c3 = &i2c3; | |
25 | i2c4 = &i2c4; | |
26 | i2c5 = &i2c5; | |
27 | i2c6 = &i2c6; | |
28 | i2c7 = &i2c_dvfs; | |
29 | }; | |
30 | ||
31 | psci { | |
32 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
33 | method = "smc"; | |
34 | }; | |
35 | ||
36 | cpus { | |
37 | #address-cells = <1>; | |
38 | #size-cells = <0>; | |
39 | ||
40 | a57_0: cpu@0 { | |
41 | compatible = "arm,cortex-a57", "arm,armv8"; | |
42 | reg = <0x0>; | |
43 | device_type = "cpu"; | |
44 | power-domains = <&sysc R8A7796_PD_CA57_CPU0>; | |
45 | next-level-cache = <&L2_CA57>; | |
46 | enable-method = "psci"; | |
47 | }; | |
48 | ||
49 | a57_1: cpu@1 { | |
50 | compatible = "arm,cortex-a57","arm,armv8"; | |
51 | reg = <0x1>; | |
52 | device_type = "cpu"; | |
53 | power-domains = <&sysc R8A7796_PD_CA57_CPU1>; | |
54 | next-level-cache = <&L2_CA57>; | |
55 | enable-method = "psci"; | |
56 | }; | |
57 | ||
58 | a53_0: cpu@100 { | |
59 | compatible = "arm,cortex-a53", "arm,armv8"; | |
60 | reg = <0x100>; | |
61 | device_type = "cpu"; | |
62 | power-domains = <&sysc R8A7796_PD_CA53_CPU0>; | |
63 | next-level-cache = <&L2_CA53>; | |
64 | enable-method = "psci"; | |
65 | }; | |
66 | ||
67 | a53_1: cpu@101 { | |
68 | compatible = "arm,cortex-a53","arm,armv8"; | |
69 | reg = <0x101>; | |
70 | device_type = "cpu"; | |
71 | power-domains = <&sysc R8A7796_PD_CA53_CPU1>; | |
72 | next-level-cache = <&L2_CA53>; | |
73 | enable-method = "psci"; | |
74 | }; | |
75 | ||
76 | a53_2: cpu@102 { | |
77 | compatible = "arm,cortex-a53","arm,armv8"; | |
78 | reg = <0x102>; | |
79 | device_type = "cpu"; | |
80 | power-domains = <&sysc R8A7796_PD_CA53_CPU2>; | |
81 | next-level-cache = <&L2_CA53>; | |
82 | enable-method = "psci"; | |
83 | }; | |
84 | ||
85 | a53_3: cpu@103 { | |
86 | compatible = "arm,cortex-a53","arm,armv8"; | |
87 | reg = <0x103>; | |
88 | device_type = "cpu"; | |
89 | power-domains = <&sysc R8A7796_PD_CA53_CPU3>; | |
90 | next-level-cache = <&L2_CA53>; | |
91 | enable-method = "psci"; | |
92 | }; | |
93 | ||
94 | L2_CA57: cache-controller-0 { | |
95 | compatible = "cache"; | |
96 | power-domains = <&sysc R8A7796_PD_CA57_SCU>; | |
97 | cache-unified; | |
98 | cache-level = <2>; | |
99 | }; | |
100 | ||
101 | L2_CA53: cache-controller-1 { | |
102 | compatible = "cache"; | |
103 | power-domains = <&sysc R8A7796_PD_CA53_SCU>; | |
104 | cache-unified; | |
105 | cache-level = <2>; | |
106 | }; | |
107 | }; | |
108 | ||
109 | extal_clk: extal { | |
110 | compatible = "fixed-clock"; | |
111 | #clock-cells = <0>; | |
112 | /* This value must be overridden by the board */ | |
113 | clock-frequency = <0>; | |
46933dfb | 114 | u-boot,dm-pre-reloc; |
4157c472 MV |
115 | }; |
116 | ||
117 | extalr_clk: extalr { | |
118 | compatible = "fixed-clock"; | |
119 | #clock-cells = <0>; | |
120 | /* This value must be overridden by the board */ | |
121 | clock-frequency = <0>; | |
46933dfb | 122 | u-boot,dm-pre-reloc; |
4157c472 MV |
123 | }; |
124 | ||
37a79081 MV |
125 | /* |
126 | * The external audio clocks are configured as 0 Hz fixed frequency | |
127 | * clocks by default. | |
128 | * Boards that provide audio clocks should override them. | |
129 | */ | |
130 | audio_clk_a: audio_clk_a { | |
131 | compatible = "fixed-clock"; | |
132 | #clock-cells = <0>; | |
133 | clock-frequency = <0>; | |
134 | }; | |
135 | ||
136 | audio_clk_b: audio_clk_b { | |
137 | compatible = "fixed-clock"; | |
138 | #clock-cells = <0>; | |
139 | clock-frequency = <0>; | |
140 | }; | |
141 | ||
142 | audio_clk_c: audio_clk_c { | |
143 | compatible = "fixed-clock"; | |
144 | #clock-cells = <0>; | |
145 | clock-frequency = <0>; | |
146 | }; | |
147 | ||
4157c472 MV |
148 | /* External CAN clock - to be overridden by boards that provide it */ |
149 | can_clk: can { | |
150 | compatible = "fixed-clock"; | |
151 | #clock-cells = <0>; | |
152 | clock-frequency = <0>; | |
153 | }; | |
154 | ||
155 | /* External SCIF clock - to be overridden by boards that provide it */ | |
156 | scif_clk: scif { | |
157 | compatible = "fixed-clock"; | |
158 | #clock-cells = <0>; | |
159 | clock-frequency = <0>; | |
160 | }; | |
161 | ||
37a79081 MV |
162 | /* External PCIe clock - can be overridden by the board */ |
163 | pcie_bus_clk: pcie_bus { | |
164 | compatible = "fixed-clock"; | |
165 | #clock-cells = <0>; | |
166 | clock-frequency = <0>; | |
167 | }; | |
168 | ||
4157c472 MV |
169 | soc { |
170 | compatible = "simple-bus"; | |
171 | interrupt-parent = <&gic>; | |
172 | #address-cells = <2>; | |
173 | #size-cells = <2>; | |
174 | ranges; | |
46933dfb | 175 | u-boot,dm-pre-reloc; |
4157c472 MV |
176 | |
177 | gic: interrupt-controller@f1010000 { | |
178 | compatible = "arm,gic-400"; | |
179 | #interrupt-cells = <3>; | |
180 | #address-cells = <0>; | |
181 | interrupt-controller; | |
182 | reg = <0x0 0xf1010000 0 0x1000>, | |
183 | <0x0 0xf1020000 0 0x20000>, | |
184 | <0x0 0xf1040000 0 0x20000>, | |
185 | <0x0 0xf1060000 0 0x20000>; | |
186 | interrupts = <GIC_PPI 9 | |
187 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; | |
188 | clocks = <&cpg CPG_MOD 408>; | |
189 | clock-names = "clk"; | |
190 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
191 | resets = <&cpg 408>; | |
192 | }; | |
193 | ||
194 | timer { | |
195 | compatible = "arm,armv8-timer"; | |
196 | interrupts = <GIC_PPI 13 | |
197 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
198 | <GIC_PPI 14 | |
199 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
200 | <GIC_PPI 11 | |
201 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
202 | <GIC_PPI 10 | |
203 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; | |
204 | }; | |
205 | ||
206 | wdt0: watchdog@e6020000 { | |
207 | compatible = "renesas,r8a7796-wdt", | |
208 | "renesas,rcar-gen3-wdt"; | |
209 | reg = <0 0xe6020000 0 0x0c>; | |
210 | clocks = <&cpg CPG_MOD 402>; | |
211 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
212 | resets = <&cpg 402>; | |
213 | status = "disabled"; | |
214 | }; | |
215 | ||
216 | gpio0: gpio@e6050000 { | |
217 | compatible = "renesas,gpio-r8a7796", | |
218 | "renesas,gpio-rcar"; | |
219 | reg = <0 0xe6050000 0 0x50>; | |
220 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
221 | #gpio-cells = <2>; | |
222 | gpio-controller; | |
223 | gpio-ranges = <&pfc 0 0 16>; | |
224 | #interrupt-cells = <2>; | |
225 | interrupt-controller; | |
226 | clocks = <&cpg CPG_MOD 912>; | |
227 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
228 | resets = <&cpg 912>; | |
229 | }; | |
230 | ||
231 | gpio1: gpio@e6051000 { | |
232 | compatible = "renesas,gpio-r8a7796", | |
233 | "renesas,gpio-rcar"; | |
234 | reg = <0 0xe6051000 0 0x50>; | |
235 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
236 | #gpio-cells = <2>; | |
237 | gpio-controller; | |
238 | gpio-ranges = <&pfc 0 32 29>; | |
239 | #interrupt-cells = <2>; | |
240 | interrupt-controller; | |
241 | clocks = <&cpg CPG_MOD 911>; | |
242 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
243 | resets = <&cpg 911>; | |
244 | }; | |
245 | ||
246 | gpio2: gpio@e6052000 { | |
247 | compatible = "renesas,gpio-r8a7796", | |
248 | "renesas,gpio-rcar"; | |
249 | reg = <0 0xe6052000 0 0x50>; | |
250 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
251 | #gpio-cells = <2>; | |
252 | gpio-controller; | |
253 | gpio-ranges = <&pfc 0 64 15>; | |
254 | #interrupt-cells = <2>; | |
255 | interrupt-controller; | |
256 | clocks = <&cpg CPG_MOD 910>; | |
257 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
258 | resets = <&cpg 910>; | |
259 | }; | |
260 | ||
261 | gpio3: gpio@e6053000 { | |
262 | compatible = "renesas,gpio-r8a7796", | |
263 | "renesas,gpio-rcar"; | |
264 | reg = <0 0xe6053000 0 0x50>; | |
265 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
266 | #gpio-cells = <2>; | |
267 | gpio-controller; | |
268 | gpio-ranges = <&pfc 0 96 16>; | |
269 | #interrupt-cells = <2>; | |
270 | interrupt-controller; | |
271 | clocks = <&cpg CPG_MOD 909>; | |
272 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
273 | resets = <&cpg 909>; | |
274 | }; | |
275 | ||
276 | gpio4: gpio@e6054000 { | |
277 | compatible = "renesas,gpio-r8a7796", | |
278 | "renesas,gpio-rcar"; | |
279 | reg = <0 0xe6054000 0 0x50>; | |
280 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
281 | #gpio-cells = <2>; | |
282 | gpio-controller; | |
283 | gpio-ranges = <&pfc 0 128 18>; | |
284 | #interrupt-cells = <2>; | |
285 | interrupt-controller; | |
286 | clocks = <&cpg CPG_MOD 908>; | |
287 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
288 | resets = <&cpg 908>; | |
289 | }; | |
290 | ||
291 | gpio5: gpio@e6055000 { | |
292 | compatible = "renesas,gpio-r8a7796", | |
293 | "renesas,gpio-rcar"; | |
294 | reg = <0 0xe6055000 0 0x50>; | |
295 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
296 | #gpio-cells = <2>; | |
297 | gpio-controller; | |
298 | gpio-ranges = <&pfc 0 160 26>; | |
299 | #interrupt-cells = <2>; | |
300 | interrupt-controller; | |
301 | clocks = <&cpg CPG_MOD 907>; | |
302 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
303 | resets = <&cpg 907>; | |
304 | }; | |
305 | ||
306 | gpio6: gpio@e6055400 { | |
307 | compatible = "renesas,gpio-r8a7796", | |
308 | "renesas,gpio-rcar"; | |
309 | reg = <0 0xe6055400 0 0x50>; | |
310 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
311 | #gpio-cells = <2>; | |
312 | gpio-controller; | |
313 | gpio-ranges = <&pfc 0 192 32>; | |
314 | #interrupt-cells = <2>; | |
315 | interrupt-controller; | |
316 | clocks = <&cpg CPG_MOD 906>; | |
317 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
318 | resets = <&cpg 906>; | |
319 | }; | |
320 | ||
321 | gpio7: gpio@e6055800 { | |
322 | compatible = "renesas,gpio-r8a7796", | |
323 | "renesas,gpio-rcar"; | |
324 | reg = <0 0xe6055800 0 0x50>; | |
325 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
326 | #gpio-cells = <2>; | |
327 | gpio-controller; | |
328 | gpio-ranges = <&pfc 0 224 4>; | |
329 | #interrupt-cells = <2>; | |
330 | interrupt-controller; | |
331 | clocks = <&cpg CPG_MOD 905>; | |
332 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
333 | resets = <&cpg 905>; | |
334 | }; | |
335 | ||
336 | pfc: pin-controller@e6060000 { | |
337 | compatible = "renesas,pfc-r8a7796"; | |
338 | reg = <0 0xe6060000 0 0x50c>; | |
339 | }; | |
340 | ||
341 | pmu_a57 { | |
342 | compatible = "arm,cortex-a57-pmu"; | |
343 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
344 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
345 | interrupt-affinity = <&a57_0>, | |
346 | <&a57_1>; | |
347 | }; | |
348 | ||
349 | pmu_a53 { | |
350 | compatible = "arm,cortex-a53-pmu"; | |
351 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, | |
352 | <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
353 | <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, | |
354 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
355 | interrupt-affinity = <&a53_0>, | |
356 | <&a53_1>, | |
357 | <&a53_2>, | |
358 | <&a53_3>; | |
359 | }; | |
360 | ||
361 | cpg: clock-controller@e6150000 { | |
362 | compatible = "renesas,r8a7796-cpg-mssr"; | |
363 | reg = <0 0xe6150000 0 0x1000>; | |
364 | clocks = <&extal_clk>, <&extalr_clk>; | |
365 | clock-names = "extal", "extalr"; | |
366 | #clock-cells = <2>; | |
367 | #power-domain-cells = <0>; | |
368 | #reset-cells = <1>; | |
46933dfb | 369 | u-boot,dm-pre-reloc; |
4157c472 MV |
370 | }; |
371 | ||
372 | rst: reset-controller@e6160000 { | |
373 | compatible = "renesas,r8a7796-rst"; | |
374 | reg = <0 0xe6160000 0 0x0200>; | |
375 | }; | |
376 | ||
377 | prr: chipid@fff00044 { | |
378 | compatible = "renesas,prr"; | |
379 | reg = <0 0xfff00044 0 4>; | |
d7f0b852 | 380 | u-boot,dm-pre-reloc; |
4157c472 MV |
381 | }; |
382 | ||
383 | sysc: system-controller@e6180000 { | |
384 | compatible = "renesas,r8a7796-sysc"; | |
385 | reg = <0 0xe6180000 0 0x0400>; | |
386 | #power-domain-cells = <1>; | |
387 | }; | |
388 | ||
389 | i2c_dvfs: i2c@e60b0000 { | |
390 | #address-cells = <1>; | |
391 | #size-cells = <0>; | |
392 | compatible = "renesas,iic-r8a7796", | |
393 | "renesas,rcar-gen3-iic", | |
394 | "renesas,rmobile-iic"; | |
395 | reg = <0 0xe60b0000 0 0x425>; | |
396 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; | |
397 | clocks = <&cpg CPG_MOD 926>; | |
398 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
399 | resets = <&cpg 926>; | |
37a79081 MV |
400 | dmas = <&dmac0 0x11>, <&dmac0 0x10>; |
401 | dma-names = "tx", "rx"; | |
402 | status = "disabled"; | |
403 | }; | |
404 | ||
405 | pwm0: pwm@e6e30000 { | |
406 | compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; | |
407 | reg = <0 0xe6e30000 0 8>; | |
408 | #pwm-cells = <2>; | |
409 | clocks = <&cpg CPG_MOD 523>; | |
410 | resets = <&cpg 523>; | |
411 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
412 | status = "disabled"; | |
413 | }; | |
414 | ||
415 | pwm1: pwm@e6e31000 { | |
416 | compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; | |
417 | reg = <0 0xe6e31000 0 8>; | |
418 | #pwm-cells = <2>; | |
419 | clocks = <&cpg CPG_MOD 523>; | |
420 | resets = <&cpg 523>; | |
421 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
422 | status = "disabled"; | |
423 | }; | |
424 | ||
425 | pwm2: pwm@e6e32000 { | |
426 | compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; | |
427 | reg = <0 0xe6e32000 0 8>; | |
428 | #pwm-cells = <2>; | |
429 | clocks = <&cpg CPG_MOD 523>; | |
430 | resets = <&cpg 523>; | |
431 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
432 | status = "disabled"; | |
433 | }; | |
434 | ||
435 | pwm3: pwm@e6e33000 { | |
436 | compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; | |
437 | reg = <0 0xe6e33000 0 8>; | |
438 | #pwm-cells = <2>; | |
439 | clocks = <&cpg CPG_MOD 523>; | |
440 | resets = <&cpg 523>; | |
441 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
442 | status = "disabled"; | |
443 | }; | |
444 | ||
445 | pwm4: pwm@e6e34000 { | |
446 | compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; | |
447 | reg = <0 0xe6e34000 0 8>; | |
448 | #pwm-cells = <2>; | |
449 | clocks = <&cpg CPG_MOD 523>; | |
450 | resets = <&cpg 523>; | |
451 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
452 | status = "disabled"; | |
453 | }; | |
454 | ||
455 | pwm5: pwm@e6e35000 { | |
456 | compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; | |
457 | reg = <0 0xe6e35000 0 8>; | |
458 | #pwm-cells = <2>; | |
459 | clocks = <&cpg CPG_MOD 523>; | |
460 | resets = <&cpg 523>; | |
461 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
465 | pwm6: pwm@e6e36000 { | |
466 | compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; | |
467 | reg = <0 0xe6e36000 0 8>; | |
468 | #pwm-cells = <2>; | |
469 | clocks = <&cpg CPG_MOD 523>; | |
470 | resets = <&cpg 523>; | |
471 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
4157c472 MV |
472 | status = "disabled"; |
473 | }; | |
474 | ||
475 | i2c0: i2c@e6500000 { | |
476 | #address-cells = <1>; | |
477 | #size-cells = <0>; | |
478 | compatible = "renesas,i2c-r8a7796", | |
479 | "renesas,rcar-gen3-i2c"; | |
480 | reg = <0 0xe6500000 0 0x40>; | |
481 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
482 | clocks = <&cpg CPG_MOD 931>; | |
483 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
484 | resets = <&cpg 931>; | |
485 | dmas = <&dmac1 0x91>, <&dmac1 0x90>, | |
486 | <&dmac2 0x91>, <&dmac2 0x90>; | |
487 | dma-names = "tx", "rx", "tx", "rx"; | |
488 | i2c-scl-internal-delay-ns = <110>; | |
489 | status = "disabled"; | |
490 | }; | |
491 | ||
492 | i2c1: i2c@e6508000 { | |
493 | #address-cells = <1>; | |
494 | #size-cells = <0>; | |
495 | compatible = "renesas,i2c-r8a7796", | |
496 | "renesas,rcar-gen3-i2c"; | |
497 | reg = <0 0xe6508000 0 0x40>; | |
498 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
499 | clocks = <&cpg CPG_MOD 930>; | |
500 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
501 | resets = <&cpg 930>; | |
502 | dmas = <&dmac1 0x93>, <&dmac1 0x92>, | |
503 | <&dmac2 0x93>, <&dmac2 0x92>; | |
504 | dma-names = "tx", "rx", "tx", "rx"; | |
505 | i2c-scl-internal-delay-ns = <6>; | |
506 | status = "disabled"; | |
507 | }; | |
508 | ||
509 | i2c2: i2c@e6510000 { | |
510 | #address-cells = <1>; | |
511 | #size-cells = <0>; | |
512 | compatible = "renesas,i2c-r8a7796", | |
513 | "renesas,rcar-gen3-i2c"; | |
514 | reg = <0 0xe6510000 0 0x40>; | |
515 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
516 | clocks = <&cpg CPG_MOD 929>; | |
517 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
518 | resets = <&cpg 929>; | |
519 | dmas = <&dmac1 0x95>, <&dmac1 0x94>, | |
520 | <&dmac2 0x95>, <&dmac2 0x94>; | |
521 | dma-names = "tx", "rx", "tx", "rx"; | |
522 | i2c-scl-internal-delay-ns = <6>; | |
523 | status = "disabled"; | |
524 | }; | |
525 | ||
526 | i2c3: i2c@e66d0000 { | |
527 | #address-cells = <1>; | |
528 | #size-cells = <0>; | |
529 | compatible = "renesas,i2c-r8a7796", | |
530 | "renesas,rcar-gen3-i2c"; | |
531 | reg = <0 0xe66d0000 0 0x40>; | |
532 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
533 | clocks = <&cpg CPG_MOD 928>; | |
534 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
535 | resets = <&cpg 928>; | |
536 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; | |
537 | dma-names = "tx", "rx"; | |
538 | i2c-scl-internal-delay-ns = <110>; | |
539 | status = "disabled"; | |
540 | }; | |
541 | ||
542 | i2c4: i2c@e66d8000 { | |
543 | #address-cells = <1>; | |
544 | #size-cells = <0>; | |
545 | compatible = "renesas,i2c-r8a7796", | |
546 | "renesas,rcar-gen3-i2c"; | |
547 | reg = <0 0xe66d8000 0 0x40>; | |
548 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
549 | clocks = <&cpg CPG_MOD 927>; | |
550 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
551 | resets = <&cpg 927>; | |
552 | dmas = <&dmac0 0x99>, <&dmac0 0x98>; | |
553 | dma-names = "tx", "rx"; | |
554 | i2c-scl-internal-delay-ns = <110>; | |
555 | status = "disabled"; | |
556 | }; | |
557 | ||
558 | i2c5: i2c@e66e0000 { | |
559 | #address-cells = <1>; | |
560 | #size-cells = <0>; | |
561 | compatible = "renesas,i2c-r8a7796", | |
562 | "renesas,rcar-gen3-i2c"; | |
563 | reg = <0 0xe66e0000 0 0x40>; | |
564 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
565 | clocks = <&cpg CPG_MOD 919>; | |
566 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
567 | resets = <&cpg 919>; | |
568 | dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; | |
569 | dma-names = "tx", "rx"; | |
570 | i2c-scl-internal-delay-ns = <110>; | |
571 | status = "disabled"; | |
572 | }; | |
573 | ||
574 | i2c6: i2c@e66e8000 { | |
575 | #address-cells = <1>; | |
576 | #size-cells = <0>; | |
577 | compatible = "renesas,i2c-r8a7796", | |
578 | "renesas,rcar-gen3-i2c"; | |
579 | reg = <0 0xe66e8000 0 0x40>; | |
580 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
581 | clocks = <&cpg CPG_MOD 918>; | |
582 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
583 | resets = <&cpg 918>; | |
584 | dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; | |
585 | dma-names = "tx", "rx"; | |
586 | i2c-scl-internal-delay-ns = <6>; | |
587 | status = "disabled"; | |
588 | }; | |
589 | ||
590 | can0: can@e6c30000 { | |
591 | compatible = "renesas,can-r8a7796", | |
592 | "renesas,rcar-gen3-can"; | |
593 | reg = <0 0xe6c30000 0 0x1000>; | |
594 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
595 | clocks = <&cpg CPG_MOD 916>, | |
596 | <&cpg CPG_CORE R8A7796_CLK_CANFD>, | |
597 | <&can_clk>; | |
598 | clock-names = "clkp1", "clkp2", "can_clk"; | |
599 | assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; | |
600 | assigned-clock-rates = <40000000>; | |
601 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
602 | resets = <&cpg 916>; | |
603 | status = "disabled"; | |
604 | }; | |
605 | ||
606 | can1: can@e6c38000 { | |
607 | compatible = "renesas,can-r8a7796", | |
608 | "renesas,rcar-gen3-can"; | |
609 | reg = <0 0xe6c38000 0 0x1000>; | |
610 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
611 | clocks = <&cpg CPG_MOD 915>, | |
612 | <&cpg CPG_CORE R8A7796_CLK_CANFD>, | |
613 | <&can_clk>; | |
614 | clock-names = "clkp1", "clkp2", "can_clk"; | |
615 | assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; | |
616 | assigned-clock-rates = <40000000>; | |
617 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
618 | resets = <&cpg 915>; | |
619 | status = "disabled"; | |
620 | }; | |
621 | ||
622 | canfd: can@e66c0000 { | |
623 | compatible = "renesas,r8a7796-canfd", | |
624 | "renesas,rcar-gen3-canfd"; | |
625 | reg = <0 0xe66c0000 0 0x8000>; | |
626 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, | |
627 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
628 | clocks = <&cpg CPG_MOD 914>, | |
629 | <&cpg CPG_CORE R8A7796_CLK_CANFD>, | |
630 | <&can_clk>; | |
631 | clock-names = "fck", "canfd", "can_clk"; | |
632 | assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; | |
633 | assigned-clock-rates = <40000000>; | |
634 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
635 | resets = <&cpg 914>; | |
636 | status = "disabled"; | |
637 | ||
638 | channel0 { | |
639 | status = "disabled"; | |
640 | }; | |
641 | ||
642 | channel1 { | |
643 | status = "disabled"; | |
644 | }; | |
645 | }; | |
646 | ||
647 | avb: ethernet@e6800000 { | |
648 | compatible = "renesas,etheravb-r8a7796", | |
649 | "renesas,etheravb-rcar-gen3"; | |
650 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; | |
651 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
652 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
653 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
654 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
655 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
656 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
657 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
658 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
659 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
660 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
661 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
662 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
663 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
664 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
665 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
666 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
667 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
668 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
669 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
670 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
671 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
672 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
673 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
674 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
675 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
676 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
677 | "ch4", "ch5", "ch6", "ch7", | |
678 | "ch8", "ch9", "ch10", "ch11", | |
679 | "ch12", "ch13", "ch14", "ch15", | |
680 | "ch16", "ch17", "ch18", "ch19", | |
681 | "ch20", "ch21", "ch22", "ch23", | |
682 | "ch24"; | |
683 | clocks = <&cpg CPG_MOD 812>; | |
684 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
685 | resets = <&cpg 812>; | |
686 | phy-mode = "rgmii-txid"; | |
687 | #address-cells = <1>; | |
688 | #size-cells = <0>; | |
689 | status = "disabled"; | |
690 | }; | |
691 | ||
692 | hscif0: serial@e6540000 { | |
693 | compatible = "renesas,hscif-r8a7796", | |
694 | "renesas,rcar-gen3-hscif", | |
695 | "renesas,hscif"; | |
696 | reg = <0 0xe6540000 0 0x60>; | |
697 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
698 | clocks = <&cpg CPG_MOD 520>, | |
699 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
700 | <&scif_clk>; | |
701 | clock-names = "fck", "brg_int", "scif_clk"; | |
702 | dmas = <&dmac1 0x31>, <&dmac1 0x30>, | |
703 | <&dmac2 0x31>, <&dmac2 0x30>; | |
704 | dma-names = "tx", "rx", "tx", "rx"; | |
705 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
706 | resets = <&cpg 520>; | |
707 | status = "disabled"; | |
708 | }; | |
709 | ||
710 | hscif1: serial@e6550000 { | |
711 | compatible = "renesas,hscif-r8a7796", | |
712 | "renesas,rcar-gen3-hscif", | |
713 | "renesas,hscif"; | |
714 | reg = <0 0xe6550000 0 0x60>; | |
715 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
716 | clocks = <&cpg CPG_MOD 519>, | |
717 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
718 | <&scif_clk>; | |
719 | clock-names = "fck", "brg_int", "scif_clk"; | |
720 | dmas = <&dmac1 0x33>, <&dmac1 0x32>, | |
721 | <&dmac2 0x33>, <&dmac2 0x32>; | |
722 | dma-names = "tx", "rx", "tx", "rx"; | |
723 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
724 | resets = <&cpg 519>; | |
725 | status = "disabled"; | |
726 | }; | |
727 | ||
728 | hscif2: serial@e6560000 { | |
729 | compatible = "renesas,hscif-r8a7796", | |
730 | "renesas,rcar-gen3-hscif", | |
731 | "renesas,hscif"; | |
732 | reg = <0 0xe6560000 0 0x60>; | |
733 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
734 | clocks = <&cpg CPG_MOD 518>, | |
735 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
736 | <&scif_clk>; | |
737 | clock-names = "fck", "brg_int", "scif_clk"; | |
738 | dmas = <&dmac1 0x35>, <&dmac1 0x34>, | |
739 | <&dmac2 0x35>, <&dmac2 0x34>; | |
740 | dma-names = "tx", "rx", "tx", "rx"; | |
741 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
742 | resets = <&cpg 518>; | |
743 | status = "disabled"; | |
744 | }; | |
745 | ||
746 | hscif3: serial@e66a0000 { | |
747 | compatible = "renesas,hscif-r8a7796", | |
748 | "renesas,rcar-gen3-hscif", | |
749 | "renesas,hscif"; | |
750 | reg = <0 0xe66a0000 0 0x60>; | |
751 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
752 | clocks = <&cpg CPG_MOD 517>, | |
753 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
754 | <&scif_clk>; | |
755 | clock-names = "fck", "brg_int", "scif_clk"; | |
756 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
757 | dma-names = "tx", "rx"; | |
758 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
759 | resets = <&cpg 517>; | |
760 | status = "disabled"; | |
761 | }; | |
762 | ||
763 | hscif4: serial@e66b0000 { | |
764 | compatible = "renesas,hscif-r8a7796", | |
765 | "renesas,rcar-gen3-hscif", | |
766 | "renesas,hscif"; | |
767 | reg = <0 0xe66b0000 0 0x60>; | |
768 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
769 | clocks = <&cpg CPG_MOD 516>, | |
770 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
771 | <&scif_clk>; | |
772 | clock-names = "fck", "brg_int", "scif_clk"; | |
773 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; | |
774 | dma-names = "tx", "rx"; | |
775 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
776 | resets = <&cpg 516>; | |
777 | status = "disabled"; | |
778 | }; | |
779 | ||
780 | scif0: serial@e6e60000 { | |
781 | compatible = "renesas,scif-r8a7796", | |
782 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
783 | reg = <0 0xe6e60000 0 64>; | |
784 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
785 | clocks = <&cpg CPG_MOD 207>, | |
786 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
787 | <&scif_clk>; | |
788 | clock-names = "fck", "brg_int", "scif_clk"; | |
789 | dmas = <&dmac1 0x51>, <&dmac1 0x50>, | |
790 | <&dmac2 0x51>, <&dmac2 0x50>; | |
791 | dma-names = "tx", "rx", "tx", "rx"; | |
792 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
793 | resets = <&cpg 207>; | |
794 | status = "disabled"; | |
795 | }; | |
796 | ||
797 | scif1: serial@e6e68000 { | |
798 | compatible = "renesas,scif-r8a7796", | |
799 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
800 | reg = <0 0xe6e68000 0 64>; | |
801 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
802 | clocks = <&cpg CPG_MOD 206>, | |
803 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
804 | <&scif_clk>; | |
805 | clock-names = "fck", "brg_int", "scif_clk"; | |
806 | dmas = <&dmac1 0x53>, <&dmac1 0x52>, | |
807 | <&dmac2 0x53>, <&dmac2 0x52>; | |
808 | dma-names = "tx", "rx", "tx", "rx"; | |
809 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
810 | resets = <&cpg 206>; | |
811 | status = "disabled"; | |
812 | }; | |
813 | ||
814 | scif2: serial@e6e88000 { | |
815 | compatible = "renesas,scif-r8a7796", | |
816 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
817 | reg = <0 0xe6e88000 0 64>; | |
818 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
819 | clocks = <&cpg CPG_MOD 310>, | |
820 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
821 | <&scif_clk>; | |
822 | clock-names = "fck", "brg_int", "scif_clk"; | |
823 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
824 | resets = <&cpg 310>; | |
825 | status = "disabled"; | |
826 | }; | |
827 | ||
828 | scif3: serial@e6c50000 { | |
829 | compatible = "renesas,scif-r8a7796", | |
830 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
831 | reg = <0 0xe6c50000 0 64>; | |
832 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
833 | clocks = <&cpg CPG_MOD 204>, | |
834 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
835 | <&scif_clk>; | |
836 | clock-names = "fck", "brg_int", "scif_clk"; | |
837 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
838 | dma-names = "tx", "rx"; | |
839 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
840 | resets = <&cpg 204>; | |
841 | status = "disabled"; | |
842 | }; | |
843 | ||
844 | scif4: serial@e6c40000 { | |
845 | compatible = "renesas,scif-r8a7796", | |
846 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
847 | reg = <0 0xe6c40000 0 64>; | |
848 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
849 | clocks = <&cpg CPG_MOD 203>, | |
850 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
851 | <&scif_clk>; | |
852 | clock-names = "fck", "brg_int", "scif_clk"; | |
853 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
854 | dma-names = "tx", "rx"; | |
855 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
856 | resets = <&cpg 203>; | |
857 | status = "disabled"; | |
858 | }; | |
859 | ||
860 | scif5: serial@e6f30000 { | |
861 | compatible = "renesas,scif-r8a7796", | |
862 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
863 | reg = <0 0xe6f30000 0 64>; | |
864 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
865 | clocks = <&cpg CPG_MOD 202>, | |
866 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
867 | <&scif_clk>; | |
868 | clock-names = "fck", "brg_int", "scif_clk"; | |
869 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, | |
870 | <&dmac2 0x5b>, <&dmac2 0x5a>; | |
871 | dma-names = "tx", "rx", "tx", "rx"; | |
872 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
873 | resets = <&cpg 202>; | |
874 | status = "disabled"; | |
875 | }; | |
876 | ||
877 | msiof0: spi@e6e90000 { | |
878 | compatible = "renesas,msiof-r8a7796", | |
879 | "renesas,rcar-gen3-msiof"; | |
880 | reg = <0 0xe6e90000 0 0x0064>; | |
881 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
882 | clocks = <&cpg CPG_MOD 211>; | |
883 | dmas = <&dmac1 0x41>, <&dmac1 0x40>, | |
884 | <&dmac2 0x41>, <&dmac2 0x40>; | |
885 | dma-names = "tx", "rx"; | |
886 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
887 | resets = <&cpg 211>; | |
888 | #address-cells = <1>; | |
889 | #size-cells = <0>; | |
890 | status = "disabled"; | |
891 | }; | |
892 | ||
893 | msiof1: spi@e6ea0000 { | |
894 | compatible = "renesas,msiof-r8a7796", | |
895 | "renesas,rcar-gen3-msiof"; | |
896 | reg = <0 0xe6ea0000 0 0x0064>; | |
897 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; | |
898 | clocks = <&cpg CPG_MOD 210>; | |
899 | dmas = <&dmac1 0x43>, <&dmac1 0x42>, | |
900 | <&dmac2 0x43>, <&dmac2 0x42>; | |
901 | dma-names = "tx", "rx"; | |
902 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
903 | resets = <&cpg 210>; | |
904 | #address-cells = <1>; | |
905 | #size-cells = <0>; | |
906 | status = "disabled"; | |
907 | }; | |
908 | ||
909 | msiof2: spi@e6c00000 { | |
910 | compatible = "renesas,msiof-r8a7796", | |
911 | "renesas,rcar-gen3-msiof"; | |
912 | reg = <0 0xe6c00000 0 0x0064>; | |
913 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
914 | clocks = <&cpg CPG_MOD 209>; | |
915 | dmas = <&dmac0 0x45>, <&dmac0 0x44>; | |
916 | dma-names = "tx", "rx"; | |
917 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
918 | resets = <&cpg 209>; | |
919 | #address-cells = <1>; | |
920 | #size-cells = <0>; | |
921 | status = "disabled"; | |
922 | }; | |
923 | ||
924 | msiof3: spi@e6c10000 { | |
925 | compatible = "renesas,msiof-r8a7796", | |
926 | "renesas,rcar-gen3-msiof"; | |
927 | reg = <0 0xe6c10000 0 0x0064>; | |
928 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; | |
929 | clocks = <&cpg CPG_MOD 208>; | |
930 | dmas = <&dmac0 0x47>, <&dmac0 0x46>; | |
931 | dma-names = "tx", "rx"; | |
932 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
933 | resets = <&cpg 208>; | |
934 | #address-cells = <1>; | |
935 | #size-cells = <0>; | |
936 | status = "disabled"; | |
937 | }; | |
938 | ||
939 | dmac0: dma-controller@e6700000 { | |
940 | compatible = "renesas,dmac-r8a7796", | |
941 | "renesas,rcar-dmac"; | |
942 | reg = <0 0xe6700000 0 0x10000>; | |
943 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH | |
944 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
945 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
946 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
947 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
948 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
949 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
950 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
951 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
952 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
953 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
954 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
955 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
956 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
957 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
958 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH | |
959 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
960 | interrupt-names = "error", | |
961 | "ch0", "ch1", "ch2", "ch3", | |
962 | "ch4", "ch5", "ch6", "ch7", | |
963 | "ch8", "ch9", "ch10", "ch11", | |
964 | "ch12", "ch13", "ch14", "ch15"; | |
965 | clocks = <&cpg CPG_MOD 219>; | |
966 | clock-names = "fck"; | |
967 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
968 | resets = <&cpg 219>; | |
969 | #dma-cells = <1>; | |
970 | dma-channels = <16>; | |
971 | }; | |
972 | ||
973 | dmac1: dma-controller@e7300000 { | |
974 | compatible = "renesas,dmac-r8a7796", | |
975 | "renesas,rcar-dmac"; | |
976 | reg = <0 0xe7300000 0 0x10000>; | |
977 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH | |
978 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
979 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
980 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
981 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
982 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
983 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
984 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
985 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
986 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
987 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
988 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
989 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
990 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
991 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
992 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH | |
993 | GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; | |
994 | interrupt-names = "error", | |
995 | "ch0", "ch1", "ch2", "ch3", | |
996 | "ch4", "ch5", "ch6", "ch7", | |
997 | "ch8", "ch9", "ch10", "ch11", | |
998 | "ch12", "ch13", "ch14", "ch15"; | |
999 | clocks = <&cpg CPG_MOD 218>; | |
1000 | clock-names = "fck"; | |
1001 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1002 | resets = <&cpg 218>; | |
1003 | #dma-cells = <1>; | |
1004 | dma-channels = <16>; | |
1005 | }; | |
1006 | ||
1007 | dmac2: dma-controller@e7310000 { | |
1008 | compatible = "renesas,dmac-r8a7796", | |
1009 | "renesas,rcar-dmac"; | |
1010 | reg = <0 0xe7310000 0 0x10000>; | |
1011 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH | |
1012 | GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH | |
1013 | GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH | |
1014 | GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH | |
1015 | GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH | |
1016 | GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH | |
1017 | GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH | |
1018 | GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH | |
1019 | GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH | |
1020 | GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH | |
1021 | GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH | |
1022 | GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH | |
1023 | GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH | |
1024 | GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH | |
1025 | GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH | |
1026 | GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH | |
1027 | GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
1028 | interrupt-names = "error", | |
1029 | "ch0", "ch1", "ch2", "ch3", | |
1030 | "ch4", "ch5", "ch6", "ch7", | |
1031 | "ch8", "ch9", "ch10", "ch11", | |
1032 | "ch12", "ch13", "ch14", "ch15"; | |
1033 | clocks = <&cpg CPG_MOD 217>; | |
1034 | clock-names = "fck"; | |
1035 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1036 | resets = <&cpg 217>; | |
1037 | #dma-cells = <1>; | |
1038 | dma-channels = <16>; | |
1039 | }; | |
1040 | ||
37a79081 MV |
1041 | audma0: dma-controller@ec700000 { |
1042 | compatible = "renesas,dmac-r8a7796", | |
1043 | "renesas,rcar-dmac"; | |
1044 | reg = <0 0xec700000 0 0x10000>; | |
1045 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH | |
1046 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | |
1047 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | |
1048 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | |
1049 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | |
1050 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | |
1051 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | |
1052 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | |
1053 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | |
1054 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | |
1055 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | |
1056 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | |
1057 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | |
1058 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH | |
1059 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | |
1060 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | |
1061 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | |
1062 | interrupt-names = "error", | |
1063 | "ch0", "ch1", "ch2", "ch3", | |
1064 | "ch4", "ch5", "ch6", "ch7", | |
1065 | "ch8", "ch9", "ch10", "ch11", | |
1066 | "ch12", "ch13", "ch14", "ch15"; | |
1067 | clocks = <&cpg CPG_MOD 502>; | |
1068 | clock-names = "fck"; | |
1069 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1070 | resets = <&cpg 502>; | |
1071 | #dma-cells = <1>; | |
1072 | dma-channels = <16>; | |
1073 | }; | |
1074 | ||
1075 | audma1: dma-controller@ec720000 { | |
1076 | compatible = "renesas,dmac-r8a7796", | |
1077 | "renesas,rcar-dmac"; | |
1078 | reg = <0 0xec720000 0 0x10000>; | |
1079 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH | |
1080 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | |
1081 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | |
1082 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | |
1083 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | |
1084 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | |
1085 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | |
1086 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | |
1087 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | |
1088 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | |
1089 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH | |
1090 | GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH | |
1091 | GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH | |
1092 | GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH | |
1093 | GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH | |
1094 | GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH | |
1095 | GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | |
1096 | interrupt-names = "error", | |
1097 | "ch0", "ch1", "ch2", "ch3", | |
1098 | "ch4", "ch5", "ch6", "ch7", | |
1099 | "ch8", "ch9", "ch10", "ch11", | |
1100 | "ch12", "ch13", "ch14", "ch15"; | |
1101 | clocks = <&cpg CPG_MOD 501>; | |
1102 | clock-names = "fck"; | |
1103 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1104 | resets = <&cpg 501>; | |
1105 | #dma-cells = <1>; | |
1106 | dma-channels = <16>; | |
1107 | }; | |
1108 | ||
1109 | hsusb: usb@e6590000 { | |
1d871465 MV |
1110 | compatible = "renesas,usbhs-r8a7796", |
1111 | "renesas,rcar-gen3-usbhs"; | |
1112 | reg = <0 0xe6590000 0 0x100>; | |
1113 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
1114 | clocks = <&cpg CPG_MOD 704>; | |
1115 | renesas,buswait = <11>; | |
1116 | phys = <&usb2_phy0>; | |
1117 | phy-names = "usb"; | |
1118 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1119 | resets = <&cpg 704>; | |
1120 | status = "disabled"; | |
37a79081 MV |
1121 | }; |
1122 | ||
1123 | xhci0: usb@ee000000 { | |
e8f86f2b MV |
1124 | compatible = "renesas,xhci-r8a7796", "renesas,rcar-gen3-xhci"; |
1125 | reg = <0 0xee000000 0 0xc00>; | |
1126 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
1127 | clocks = <&cpg CPG_MOD 328>; | |
1128 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1129 | resets = <&cpg 328>; | |
1130 | status = "disabled"; | |
37a79081 MV |
1131 | }; |
1132 | ||
1133 | ohci0: usb@ee080000 { | |
1134 | /* placeholder */ | |
1135 | }; | |
1136 | ||
1137 | ehci0: usb@ee080100 { | |
1d871465 MV |
1138 | compatible = "generic-ehci"; |
1139 | reg = <0 0xee080100 0 0x100>; | |
1140 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
1141 | clocks = <&cpg CPG_MOD 703>; | |
1142 | phys = <&usb2_phy0>; | |
1143 | phy-names = "usb"; | |
1144 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1145 | resets = <&cpg 703>; | |
1146 | status = "disabled"; | |
37a79081 MV |
1147 | }; |
1148 | ||
1149 | usb2_phy0: usb-phy@ee080200 { | |
1d871465 MV |
1150 | compatible = "renesas,usb2-phy-r8a7796", |
1151 | "renesas,rcar-gen3-usb2-phy"; | |
1152 | reg = <0 0xee080200 0 0x700>; | |
1153 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
1154 | clocks = <&cpg CPG_MOD 703>; | |
1155 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1156 | resets = <&cpg 703>; | |
1157 | #phy-cells = <0>; | |
1158 | status = "disabled"; | |
37a79081 MV |
1159 | }; |
1160 | ||
1161 | ohci1: usb@ee0a0000 { | |
1162 | /* placeholder */ | |
1163 | }; | |
1164 | ||
1165 | ehci1: usb@ee0a0100 { | |
1d871465 MV |
1166 | compatible = "generic-ehci"; |
1167 | reg = <0 0xee0a0100 0 0x100>; | |
1168 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
1169 | clocks = <&cpg CPG_MOD 702>; | |
1170 | phys = <&usb2_phy1>; | |
1171 | phy-names = "usb"; | |
1172 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1173 | resets = <&cpg 702>; | |
1174 | status = "disabled"; | |
37a79081 MV |
1175 | }; |
1176 | ||
1177 | usb2_phy1: usb-phy@ee0a0200 { | |
1d871465 MV |
1178 | compatible = "renesas,usb2-phy-r8a7796", |
1179 | "renesas,rcar-gen3-usb2-phy"; | |
1180 | reg = <0 0xee0a0200 0 0x700>; | |
1181 | clocks = <&cpg CPG_MOD 702>; | |
1182 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1183 | resets = <&cpg 702>; | |
1184 | #phy-cells = <0>; | |
1185 | status = "disabled"; | |
37a79081 MV |
1186 | }; |
1187 | ||
4157c472 MV |
1188 | sdhi0: sd@ee100000 { |
1189 | compatible = "renesas,sdhi-r8a7796"; | |
1190 | reg = <0 0xee100000 0 0x2000>; | |
1191 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; | |
1192 | clocks = <&cpg CPG_MOD 314>; | |
1193 | max-frequency = <200000000>; | |
1194 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1195 | resets = <&cpg 314>; | |
1196 | status = "disabled"; | |
1197 | }; | |
1198 | ||
1199 | sdhi1: sd@ee120000 { | |
1200 | compatible = "renesas,sdhi-r8a7796"; | |
1201 | reg = <0 0xee120000 0 0x2000>; | |
1202 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; | |
1203 | clocks = <&cpg CPG_MOD 313>; | |
1204 | max-frequency = <200000000>; | |
1205 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1206 | resets = <&cpg 313>; | |
1207 | status = "disabled"; | |
1208 | }; | |
1209 | ||
1210 | sdhi2: sd@ee140000 { | |
1211 | compatible = "renesas,sdhi-r8a7796"; | |
1212 | reg = <0 0xee140000 0 0x2000>; | |
1213 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; | |
1214 | clocks = <&cpg CPG_MOD 312>; | |
1215 | max-frequency = <200000000>; | |
1216 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1217 | resets = <&cpg 312>; | |
1218 | status = "disabled"; | |
1219 | }; | |
1220 | ||
1221 | sdhi3: sd@ee160000 { | |
1222 | compatible = "renesas,sdhi-r8a7796"; | |
1223 | reg = <0 0xee160000 0 0x2000>; | |
1224 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; | |
1225 | clocks = <&cpg CPG_MOD 311>; | |
1226 | max-frequency = <200000000>; | |
1227 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1228 | resets = <&cpg 311>; | |
1229 | status = "disabled"; | |
1230 | }; | |
1231 | ||
1232 | tsc: thermal@e6198000 { | |
1233 | compatible = "renesas,r8a7796-thermal"; | |
1234 | reg = <0 0xe6198000 0 0x68>, | |
1235 | <0 0xe61a0000 0 0x5c>, | |
1236 | <0 0xe61a8000 0 0x5c>; | |
1237 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
1238 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
1239 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
1240 | clocks = <&cpg CPG_MOD 522>; | |
1241 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1242 | resets = <&cpg 522>; | |
1243 | #thermal-sensor-cells = <1>; | |
1244 | status = "okay"; | |
1245 | }; | |
1246 | ||
1247 | thermal-zones { | |
1248 | sensor_thermal1: sensor-thermal1 { | |
1249 | polling-delay-passive = <250>; | |
1250 | polling-delay = <1000>; | |
1251 | thermal-sensors = <&tsc 0>; | |
1252 | ||
1253 | trips { | |
1254 | sensor1_crit: sensor1-crit { | |
1255 | temperature = <120000>; | |
1256 | hysteresis = <2000>; | |
1257 | type = "critical"; | |
1258 | }; | |
1259 | }; | |
1260 | }; | |
1261 | ||
1262 | sensor_thermal2: sensor-thermal2 { | |
1263 | polling-delay-passive = <250>; | |
1264 | polling-delay = <1000>; | |
1265 | thermal-sensors = <&tsc 1>; | |
1266 | ||
1267 | trips { | |
1268 | sensor2_crit: sensor2-crit { | |
1269 | temperature = <120000>; | |
1270 | hysteresis = <2000>; | |
1271 | type = "critical"; | |
1272 | }; | |
1273 | }; | |
1274 | }; | |
1275 | ||
1276 | sensor_thermal3: sensor-thermal3 { | |
1277 | polling-delay-passive = <250>; | |
1278 | polling-delay = <1000>; | |
1279 | thermal-sensors = <&tsc 2>; | |
1280 | ||
1281 | trips { | |
1282 | sensor3_crit: sensor3-crit { | |
1283 | temperature = <120000>; | |
1284 | hysteresis = <2000>; | |
1285 | type = "critical"; | |
1286 | }; | |
1287 | }; | |
1288 | }; | |
1289 | }; | |
37a79081 MV |
1290 | |
1291 | rcar_sound: sound@ec500000 { | |
1292 | /* | |
1293 | * #sound-dai-cells is required | |
1294 | * | |
1295 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
1296 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
1297 | */ | |
1298 | /* | |
1299 | * #clock-cells is required for audio_clkout0/1/2/3 | |
1300 | * | |
1301 | * clkout : #clock-cells = <0>; <&rcar_sound>; | |
1302 | * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; | |
1303 | */ | |
1304 | compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; | |
1305 | reg = <0 0xec500000 0 0x1000>, /* SCU */ | |
1306 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1307 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
1308 | <0 0xec541000 0 0x280>, /* SSI */ | |
1309 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ | |
1310 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
1311 | ||
1312 | clocks = <&cpg CPG_MOD 1005>, | |
1313 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
1314 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
1315 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
1316 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
1317 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
1318 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, | |
1319 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
1320 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
1321 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
1322 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
1323 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
1324 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
1325 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, | |
1326 | <&audio_clk_a>, <&audio_clk_b>, | |
1327 | <&audio_clk_c>, | |
1328 | <&cpg CPG_CORE R8A7796_CLK_S0D4>; | |
1329 | clock-names = "ssi-all", | |
1330 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
1331 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
1332 | "ssi.1", "ssi.0", | |
1333 | "src.9", "src.8", "src.7", "src.6", | |
1334 | "src.5", "src.4", "src.3", "src.2", | |
1335 | "src.1", "src.0", | |
1336 | "mix.1", "mix.0", | |
1337 | "ctu.1", "ctu.0", | |
1338 | "dvc.0", "dvc.1", | |
1339 | "clk_a", "clk_b", "clk_c", "clk_i"; | |
1340 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
1341 | resets = <&cpg 1005>, | |
1342 | <&cpg 1006>, <&cpg 1007>, | |
1343 | <&cpg 1008>, <&cpg 1009>, | |
1344 | <&cpg 1010>, <&cpg 1011>, | |
1345 | <&cpg 1012>, <&cpg 1013>, | |
1346 | <&cpg 1014>, <&cpg 1015>; | |
1347 | reset-names = "ssi-all", | |
1348 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
1349 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
1350 | "ssi.1", "ssi.0"; | |
1351 | status = "disabled"; | |
1352 | ||
1353 | rcar_sound,dvc { | |
1354 | dvc0: dvc-0 { | |
1355 | dmas = <&audma1 0xbc>; | |
1356 | dma-names = "tx"; | |
1357 | }; | |
1358 | dvc1: dvc-1 { | |
1359 | dmas = <&audma1 0xbe>; | |
1360 | dma-names = "tx"; | |
1361 | }; | |
1362 | }; | |
1363 | ||
1364 | rcar_sound,mix { | |
1365 | mix0: mix-0 { }; | |
1366 | mix1: mix-1 { }; | |
1367 | }; | |
1368 | ||
1369 | rcar_sound,ctu { | |
1370 | ctu00: ctu-0 { }; | |
1371 | ctu01: ctu-1 { }; | |
1372 | ctu02: ctu-2 { }; | |
1373 | ctu03: ctu-3 { }; | |
1374 | ctu10: ctu-4 { }; | |
1375 | ctu11: ctu-5 { }; | |
1376 | ctu12: ctu-6 { }; | |
1377 | ctu13: ctu-7 { }; | |
1378 | }; | |
1379 | ||
1380 | rcar_sound,src { | |
1381 | src0: src-0 { | |
1382 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; | |
1383 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
1384 | dma-names = "rx", "tx"; | |
1385 | }; | |
1386 | src1: src-1 { | |
1387 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
1388 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
1389 | dma-names = "rx", "tx"; | |
1390 | }; | |
1391 | src2: src-2 { | |
1392 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
1393 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
1394 | dma-names = "rx", "tx"; | |
1395 | }; | |
1396 | src3: src-3 { | |
1397 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
1398 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
1399 | dma-names = "rx", "tx"; | |
1400 | }; | |
1401 | src4: src-4 { | |
1402 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
1403 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
1404 | dma-names = "rx", "tx"; | |
1405 | }; | |
1406 | src5: src-5 { | |
1407 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
1408 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
1409 | dma-names = "rx", "tx"; | |
1410 | }; | |
1411 | src6: src-6 { | |
1412 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
1413 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
1414 | dma-names = "rx", "tx"; | |
1415 | }; | |
1416 | src7: src-7 { | |
1417 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
1418 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
1419 | dma-names = "rx", "tx"; | |
1420 | }; | |
1421 | src8: src-8 { | |
1422 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; | |
1423 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
1424 | dma-names = "rx", "tx"; | |
1425 | }; | |
1426 | src9: src-9 { | |
1427 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; | |
1428 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
1429 | dma-names = "rx", "tx"; | |
1430 | }; | |
1431 | }; | |
1432 | ||
1433 | rcar_sound,ssi { | |
1434 | ssi0: ssi-0 { | |
1435 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
1436 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; | |
1437 | dma-names = "rx", "tx", "rxu", "txu"; | |
1438 | }; | |
1439 | ssi1: ssi-1 { | |
1440 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
1441 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; | |
1442 | dma-names = "rx", "tx", "rxu", "txu"; | |
1443 | }; | |
1444 | ssi2: ssi-2 { | |
1445 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; | |
1446 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; | |
1447 | dma-names = "rx", "tx", "rxu", "txu"; | |
1448 | }; | |
1449 | ssi3: ssi-3 { | |
1450 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
1451 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; | |
1452 | dma-names = "rx", "tx", "rxu", "txu"; | |
1453 | }; | |
1454 | ssi4: ssi-4 { | |
1455 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; | |
1456 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; | |
1457 | dma-names = "rx", "tx", "rxu", "txu"; | |
1458 | }; | |
1459 | ssi5: ssi-5 { | |
1460 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; | |
1461 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; | |
1462 | dma-names = "rx", "tx", "rxu", "txu"; | |
1463 | }; | |
1464 | ssi6: ssi-6 { | |
1465 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; | |
1466 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; | |
1467 | dma-names = "rx", "tx", "rxu", "txu"; | |
1468 | }; | |
1469 | ssi7: ssi-7 { | |
1470 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; | |
1471 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; | |
1472 | dma-names = "rx", "tx", "rxu", "txu"; | |
1473 | }; | |
1474 | ssi8: ssi-8 { | |
1475 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; | |
1476 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; | |
1477 | dma-names = "rx", "tx", "rxu", "txu"; | |
1478 | }; | |
1479 | ssi9: ssi-9 { | |
1480 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; | |
1481 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; | |
1482 | dma-names = "rx", "tx", "rxu", "txu"; | |
1483 | }; | |
1484 | }; | |
1485 | }; | |
1486 | ||
1487 | pciec0: pcie@fe000000 { | |
1488 | /* placeholder */ | |
1489 | }; | |
1490 | ||
1491 | pciec1: pcie@ee800000 { | |
1492 | /* placeholder */ | |
1493 | }; | |
1494 | ||
1495 | du: display@feb00000 { | |
1496 | /* placeholder */ | |
1497 | ||
1498 | ports { | |
1499 | #address-cells = <1>; | |
1500 | #size-cells = <0>; | |
1501 | ||
1502 | port@0 { | |
1503 | reg = <0>; | |
1504 | du_out_rgb: endpoint { | |
1505 | }; | |
1506 | }; | |
1507 | }; | |
1508 | }; | |
4157c472 MV |
1509 | }; |
1510 | }; |