[people/ms/u-boot.git] / arch / arm / dts / sama5d2.dtsi

#include "skeleton.dtsi"

/ {
	model = "Atmel SAMA5D2 family SoC";
	compatible = "atmel,sama5d2";

	aliases {
		spi0 = &spi0;
		spi1 = &qspi0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		u-boot,dm-pre-reloc;

		usb1: ohci@00400000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00400000 0x100000>;
			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb2: ehci@00500000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00500000 0x100000>;
			clocks = <&utmi>, <&uhphs_clk>;
			clock-names = "usb_clk", "ehci_clk";
			status = "disabled";
		};

		sdmmc0: sdio-host@a0000000 {
			compatible = "atmel,sama5d2-sdhci";
			reg = <0xa0000000 0x300>;
			clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
			clock-names = "hclock", "multclk", "baseclk";
			status = "disabled";
		};

		sdmmc1: sdio-host@b0000000 {
			compatible = "atmel,sama5d2-sdhci";
			reg = <0xb0000000 0x300>;
			clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
			clock-names = "hclock", "multclk", "baseclk";
			status = "disabled";
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			u-boot,dm-pre-reloc;

			pmc: pmc@f0014000 {
				compatible = "atmel,sama5d2-pmc", "syscon";
				reg = <0xf0014000 0x160>;
				#address-cells = <1>;
				#size-cells = <0>;
				#interrupt-cells = <1>;
				u-boot,dm-pre-reloc;

				main: mainck {
					compatible = "atmel,at91sam9x5-clk-main";
					#clock-cells = <0>;
					u-boot,dm-pre-reloc;
				};

				plla: pllack@0 {
					compatible = "atmel,sama5d3-clk-pll";
					#clock-cells = <0>;
					clocks = <&main>;
					reg = <0>;
					atmel,clk-input-range = <12000000 12000000>;
					#atmel,pll-clk-output-range-cells = <4>;
					atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
					u-boot,dm-pre-reloc;
				};

				plladiv: plladivck {
					compatible = "atmel,at91sam9x5-clk-plldiv";
					#clock-cells = <0>;
					clocks = <&plla>;
				};

				audio_pll_frac: audiopll_fracck {
					compatible = "atmel,sama5d2-clk-audio-pll-frac";
					#clock-cells = <0>;
					clocks = <&main>;
				};

				audio_pll_pad: audiopll_padck {
					compatible = "atmel,sama5d2-clk-audio-pll-pad";
					#clock-cells = <0>;
					clocks = <&audio_pll_frac>;
				};

				audio_pll_pmc: audiopll_pmcck {
					compatible = "atmel,sama5d2-clk-audio-pll-pmc";
					#clock-cells = <0>;
					clocks = <&audio_pll_frac>;
				};

				utmi: utmick {
					compatible = "atmel,at91sam9x5-clk-utmi";
					#clock-cells = <0>;
					clocks = <&main>;
					regmap-sfr = <&sfr>;
					u-boot,dm-pre-reloc;
				};

				mck: masterck {
					compatible = "atmel,at91sam9x5-clk-master";
					#clock-cells = <0>;
					clocks = <&main>, <&plladiv>, <&utmi>;
					atmel,clk-output-range = <124000000 166000000>;
					atmel,clk-divisors = <1 2 4 3>;
					u-boot,dm-pre-reloc;
				};

				h32ck: h32mxck {
					#clock-cells = <0>;
					compatible = "atmel,sama5d4-clk-h32mx";
					clocks = <&mck>;
					u-boot,dm-pre-reloc;
				};

				usb: usbck {
					compatible = "atmel,at91sam9x5-clk-usb";
					#clock-cells = <0>;
					clocks = <&plladiv>, <&utmi>;
				};

				prog: progck {
					compatible = "atmel,at91sam9x5-clk-programmable";
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&pmc>;
					clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;

					prog0: prog@0 {
						#clock-cells = <0>;
						reg = <0>;
					};

					prog1: prog@1 {
						#clock-cells = <0>;
						reg = <1>;
					};

					prog2: prog@2 {
						#clock-cells = <0>;
						reg = <2>;
					};
				};

				systemck {
					compatible = "atmel,at91rm9200-clk-system";
					#address-cells = <1>;
					#size-cells = <0>;

					ddrck: ddrck@2 {
						#clock-cells = <0>;
						reg = <2>;
						clocks = <&mck>;
					};

					lcdck: lcdck@3 {
						#clock-cells = <0>;
						reg = <3>;
						clocks = <&mck>;
					};

					uhpck: uhpck@6 {
						#clock-cells = <0>;
						reg = <6>;
						clocks = <&usb>;
					};

					udpck: udpck@7 {
						#clock-cells = <0>;
						reg = <7>;
						clocks = <&usb>;
					};

					pck0: pck0@8 {
						#clock-cells = <0>;
						reg = <8>;
						clocks = <&prog0>;
					};

					pck1: pck1@9 {
						#clock-cells = <0>;
						reg = <9>;
						clocks = <&prog1>;
					};

					pck2: pck2@10 {
						#clock-cells = <0>;
						reg = <10>;
						clocks = <&prog2>;
					};

					iscck: iscck@18 {
						#clock-cells = <0>;
						reg = <18>;
						clocks = <&mck>;
					};
				};

				periph32ck {
					compatible = "atmel,at91sam9x5-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&h32ck>;
					u-boot,dm-pre-reloc;

					macb0_clk: macb0_clk@5 {
						#clock-cells = <0>;
						reg = <5>;
						atmel,clk-output-range = <0 83000000>;
					};

					tdes_clk: tdes_clk@11 {
						#clock-cells = <0>;
						reg = <11>;
						atmel,clk-output-range = <0 83000000>;
					};

					matrix1_clk: matrix1_clk@14 {
						#clock-cells = <0>;
						reg = <14>;
					};

					hsmc_clk: hsmc_clk@17 {
						#clock-cells = <0>;
						reg = <17>;
					};

					pioA_clk: pioA_clk@18 {
						#clock-cells = <0>;
						reg = <18>;
						atmel,clk-output-range = <0 83000000>;
						u-boot,dm-pre-reloc;
					};

					flx0_clk: flx0_clk@19 {
						#clock-cells = <0>;
						reg = <19>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx1_clk: flx1_clk@20 {
						#clock-cells = <0>;
						reg = <20>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx2_clk: flx2_clk@21 {
						#clock-cells = <0>;
						reg = <21>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx3_clk: flx3_clk@22 {
						#clock-cells = <0>;
						reg = <22>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx4_clk: flx4_clk@23 {
						#clock-cells = <0>;
						reg = <23>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart0_clk: uart0_clk@24 {
						#clock-cells = <0>;
						reg = <24>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart1_clk: uart1_clk@25 {
						#clock-cells = <0>;
						reg = <25>;
						atmel,clk-output-range = <0 83000000>;
						u-boot,dm-pre-reloc;
					};

					uart2_clk: uart2_clk@26 {
						#clock-cells = <0>;
						reg = <26>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart3_clk: uart3_clk@27 {
						#clock-cells = <0>;
						reg = <27>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart4_clk: uart4_clk@28 {
						#clock-cells = <0>;
						reg = <28>;
						atmel,clk-output-range = <0 83000000>;
					};

					twi0_clk: twi0_clk@29 {
						reg = <29>;
						#clock-cells = <0>;
						atmel,clk-output-range = <0 83000000>;
					};

					twi1_clk: twi1_clk@30 {
						#clock-cells = <0>;
						reg = <30>;
						atmel,clk-output-range = <0 83000000>;
					};

					spi0_clk: spi0_clk@33 {
						#clock-cells = <0>;
						reg = <33>;
						atmel,clk-output-range = <0 83000000>;
						u-boot,dm-pre-reloc;
					};

					spi1_clk: spi1_clk@34 {
						#clock-cells = <0>;
						reg = <34>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb0_clk: tcb0_clk@35 {
						#clock-cells = <0>;
						reg = <35>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb1_clk: tcb1_clk@36 {
						#clock-cells = <0>;
						reg = <36>;
						atmel,clk-output-range = <0 83000000>;
					};

					pwm_clk: pwm_clk@38 {
						#clock-cells = <0>;
						reg = <38>;
						atmel,clk-output-range = <0 83000000>;
					};

					adc_clk: adc_clk@40 {
						#clock-cells = <0>;
						reg = <40>;
						atmel,clk-output-range = <0 83000000>;
					};

					uhphs_clk: uhphs_clk@41 {
						#clock-cells = <0>;
						reg = <41>;
						atmel,clk-output-range = <0 83000000>;
					};

					udphs_clk: udphs_clk@42 {
						#clock-cells = <0>;
						reg = <42>;
						atmel,clk-output-range = <0 83000000>;
					};

					ssc0_clk: ssc0_clk@43 {
						#clock-cells = <0>;
						reg = <43>;
						atmel,clk-output-range = <0 83000000>;
					};

					ssc1_clk: ssc1_clk@44 {
						#clock-cells = <0>;
						reg = <44>;
						atmel,clk-output-range = <0 83000000>;
					};

					trng_clk: trng_clk@47 {
						#clock-cells = <0>;
						reg = <47>;
						atmel,clk-output-range = <0 83000000>;
					};

					pdmic_clk: pdmic_clk@48 {
						#clock-cells = <0>;
						reg = <48>;
						atmel,clk-output-range = <0 83000000>;
					};

					i2s0_clk: i2s0_clk@54 {
						#clock-cells = <0>;
						reg = <54>;
						atmel,clk-output-range = <0 83000000>;
					};

					i2s1_clk: i2s1_clk@55 {
						#clock-cells = <0>;
						reg = <55>;
						atmel,clk-output-range = <0 83000000>;
					};

					can0_clk: can0_clk@56 {
						#clock-cells = <0>;
						reg = <56>;
						atmel,clk-output-range = <0 83000000>;
					};

					can1_clk: can1_clk@57 {
						#clock-cells = <0>;
						reg = <57>;
						atmel,clk-output-range = <0 83000000>;
					};

					classd_clk: classd_clk@59 {
						#clock-cells = <0>;
						reg = <59>;
						atmel,clk-output-range = <0 83000000>;
					};
				};

				periph64ck {
					compatible = "atmel,at91sam9x5-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&mck>;
					u-boot,dm-pre-reloc;

					dma0_clk: dma0_clk@6 {
						#clock-cells = <0>;
						reg = <6>;
					};

					dma1_clk: dma1_clk@7 {
						#clock-cells = <0>;
						reg = <7>;
					};

					aes_clk: aes_clk@9 {
						#clock-cells = <0>;
						reg = <9>;
					};

					aesb_clk: aesb_clk@10 {
						#clock-cells = <0>;
						reg = <10>;
					};

					sha_clk: sha_clk@12 {
						#clock-cells = <0>;
						reg = <12>;
					};

					mpddr_clk: mpddr_clk@13 {
						#clock-cells = <0>;
						reg = <13>;
					};

					matrix0_clk: matrix0_clk@15 {
						#clock-cells = <0>;
						reg = <15>;
					};

					sdmmc0_hclk: sdmmc0_hclk@31 {
						#clock-cells = <0>;
						reg = <31>;
						u-boot,dm-pre-reloc;
					};

					sdmmc1_hclk: sdmmc1_hclk@32 {
						#clock-cells = <0>;
						reg = <32>;
						u-boot,dm-pre-reloc;
					};

					lcdc_clk: lcdc_clk@45 {
						#clock-cells = <0>;
						reg = <45>;
					};

					isc_clk: isc_clk@46 {
						#clock-cells = <0>;
						reg = <46>;
					};

					qspi0_clk: qspi0_clk@52 {
						#clock-cells = <0>;
						reg = <52>;
						u-boot,dm-pre-reloc;
					};

					qspi1_clk: qspi1_clk@53 {
						#clock-cells = <0>;
						reg = <53>;
						u-boot,dm-pre-reloc;
					};
				};

				gck {
					compatible = "atmel,sama5d2-clk-generated";
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&pmc>;
					clocks = <&main>, <&plla>, <&utmi>, <&mck>;
					u-boot,dm-pre-reloc;

					sdmmc0_gclk: sdmmc0_gclk@31 {
						#clock-cells = <0>;
						reg = <31>;
						u-boot,dm-pre-reloc;
					};

					sdmmc1_gclk: sdmmc1_gclk@32 {
						#clock-cells = <0>;
						reg = <32>;
						u-boot,dm-pre-reloc;
					};

					tcb0_gclk: tcb0_gclk@35 {
						#clock-cells = <0>;
						reg = <35>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb1_gclk: tcb1_gclk@36 {
						#clock-cells = <0>;
						reg = <36>;
						atmel,clk-output-range = <0 83000000>;
					};

					pwm_gclk: pwm_gclk@38 {
						#clock-cells = <0>;
						reg = <38>;
						atmel,clk-output-range = <0 83000000>;
					};

					pdmic_gclk: pdmic_gclk@48 {
						#clock-cells = <0>;
						reg = <48>;
					};

					i2s0_gclk: i2s0_gclk@54 {
						#clock-cells = <0>;
						reg = <54>;
					};

					i2s1_gclk: i2s1_gclk@55 {
						#clock-cells = <0>;
						reg = <55>;
					};

					can0_gclk: can0_gclk@56 {
						#clock-cells = <0>;
						reg = <56>;
						atmel,clk-output-range = <0 80000000>;
					};

					can1_gclk: can1_gclk@57 {
						#clock-cells = <0>;
						reg = <57>;
						atmel,clk-output-range = <0 80000000>;
					};

					classd_gclk: classd_gclk@59 {
						#clock-cells = <0>;
						reg = <59>;
						atmel,clk-output-range = <0 100000000>;
					};
				};
			};

			qspi0: spi@f0020000 {
				compatible = "atmel,sama5d2-qspi";
				reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
				reg-names = "qspi_base", "qspi_mmap";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&qspi0_clk>;
				status = "disabled";
			};

			qspi1: spi@f0024000 {
				compatible = "atmel,sama5d2-qspi";
				reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
				reg-names = "qspi_base", "qspi_mmap";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&qspi1_clk>;
				status = "disabled";
			};

			spi0: spi@f8000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf8000000 0x100>;
				clocks = <&spi0_clk>;
				clock-names = "spi_clk";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			macb0: ethernet@f8008000 {
				compatible = "cdns,macb";
				reg = <0xf8008000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&macb0_clk>, <&macb0_clk>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			uart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x100>;
				clocks = <&uart1_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			i2c0: i2c@f8028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xf8028000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&twi0_clk>;
				status = "disabled";
			};

			rstc@f8048000 {
				compatible = "atmel,sama5d3-rstc";
				reg = <0xf8048000 0x10>;
				clocks = <&clk32k>;
			};

			shdwc@f8048010 {
				compatible = "atmel,sama5d2-shdwc";
				reg = <0xf8048010 0x10>;
				clocks = <&clk32k>;
				#address-cells = <1>;
				#size-cells = <0>;
				atmel,wakeup-rtc-timer;
			};

			pit: timer@f8048030 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xf8048030 0x10>;
				clocks = <&h32ck>;
			};

			watchdog@f8048040 {
				compatible = "atmel,sama5d4-wdt";
				reg = <0xf8048040 0x10>;
				clocks = <&clk32k>;
				status = "disabled";
			};

			sfr: sfr@f8030000 {
				compatible = "atmel,sama5d2-sfr", "syscon";
				reg = <0xf8030000 0x98>;
			};

			sckc@f8048050 {
				compatible = "atmel,at91sam9x5-sckc";
				reg = <0xf8048050 0x4>;

				slow_rc_osc: slow_rc_osc {
					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
					#clock-cells = <0>;
					clock-frequency = <32768>;
					clock-accuracy = <250000000>;
					atmel,startup-time-usec = <75>;
				};

				slow_osc: slow_osc {
					compatible = "atmel,at91sam9x5-clk-slow-osc";
					#clock-cells = <0>;
					clocks = <&slow_xtal>;
					atmel,startup-time-usec = <1200000>;
				};

				clk32k: slowck {
					compatible = "atmel,at91sam9x5-clk-slow";
					#clock-cells = <0>;
					clocks = <&slow_rc_osc &slow_osc>;
				};
			};

			spi1: spi@fc000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc000000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart3: serial@fc008000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc008000 0x100>;
				clocks = <&uart3_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			i2c1: i2c@fc028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xfc028000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&twi1_clk>;
				status = "disabled";
			};

			pioA: gpio@fc038000 {
				compatible = "atmel,sama5d2-gpio";
				reg = <0xfc038000 0x600>;
				clocks = <&pioA_clk>;
				gpio-controller;
				#gpio-cells = <2>;
				u-boot,dm-pre-reloc;

				pinctrl {
					compatible = "atmel,sama5d2-pinctrl";
					u-boot,dm-pre-reloc;
				};
			};
		};
	};
};
Commit	Line	Data
2c4b2dd2 WY	1	#include "skeleton.dtsi"
	2
	3	/ {
	4	model = "Atmel SAMA5D2 family SoC";
	5	compatible = "atmel,sama5d2";
	6
	7	aliases {
	8	spi0 = &spi0;
	9	spi1 = &qspi0;
	10	i2c0 = &i2c0;
	11	i2c1 = &i2c1;
	12	};
	13
	14	clocks {
	15	slow_xtal: slow_xtal {
	16	compatible = "fixed-clock";
	17	#clock-cells = <0>;
	18	clock-frequency = <0>;
	19	};
	20
	21	main_xtal: main_xtal {
	22	compatible = "fixed-clock";
	23	#clock-cells = <0>;
	24	clock-frequency = <0>;
	25	};
	26	};
	27
	28	ahb {
	29	compatible = "simple-bus";
	30	#address-cells = <1>;
	31	#size-cells = <1>;
4529ee3b	32	u-boot,dm-pre-reloc;
2c4b2dd2 WY	33
	34	usb1: ohci@00400000 {
	35	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	36	reg = <0x00400000 0x100000>;
	37	clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
	38	clock-names = "ohci_clk", "hclk", "uhpck";
	39	status = "disabled";
	40	};
	41
	42	usb2: ehci@00500000 {
	43	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	44	reg = <0x00500000 0x100000>;
	45	clocks = <&utmi>, <&uhphs_clk>;
	46	clock-names = "usb_clk", "ehci_clk";
	47	status = "disabled";
	48	};
	49
	50	sdmmc0: sdio-host@a0000000 {
	51	compatible = "atmel,sama5d2-sdhci";
	52	reg = <0xa0000000 0x300>;
	53	clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
	54	clock-names = "hclock", "multclk", "baseclk";
	55	status = "disabled";
	56	};
	57
	58	sdmmc1: sdio-host@b0000000 {
	59	compatible = "atmel,sama5d2-sdhci";
	60	reg = <0xb0000000 0x300>;
	61	clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
	62	clock-names = "hclock", "multclk", "baseclk";
	63	status = "disabled";
	64	};
	65
	66	apb {
	67	compatible = "simple-bus";
	68	#address-cells = <1>;
	69	#size-cells = <1>;
4529ee3b	70	u-boot,dm-pre-reloc;
2c4b2dd2 WY	71
	72	pmc: pmc@f0014000 {
	73	compatible = "atmel,sama5d2-pmc", "syscon";
	74	reg = <0xf0014000 0x160>;
	75	#address-cells = <1>;
	76	#size-cells = <0>;
	77	#interrupt-cells = <1>;
4529ee3b	78	u-boot,dm-pre-reloc;
2c4b2dd2 WY	79
	80	main: mainck {
	81	compatible = "atmel,at91sam9x5-clk-main";
	82	#clock-cells = <0>;
4529ee3b	83	u-boot,dm-pre-reloc;
2c4b2dd2 WY	84	};
2c4b2dd2 WY	85
9e63c49a	86	plla: pllack@0 {
2c4b2dd2 WY	87	compatible = "atmel,sama5d3-clk-pll";
	88	#clock-cells = <0>;
	89	clocks = <&main>;
	90	reg = <0>;
	91	atmel,clk-input-range = <12000000 12000000>;
	92	#atmel,pll-clk-output-range-cells = <4>;
	93	atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
4529ee3b	94	u-boot,dm-pre-reloc;
2c4b2dd2 WY	95	};
	96
	97	plladiv: plladivck {
	98	compatible = "atmel,at91sam9x5-clk-plldiv";
	99	#clock-cells = <0>;
	100	clocks = <&plla>;
	101	};
	102
	103	audio_pll_frac: audiopll_fracck {
	104	compatible = "atmel,sama5d2-clk-audio-pll-frac";
	105	#clock-cells = <0>;
	106	clocks = <&main>;
	107	};
	108
	109	audio_pll_pad: audiopll_padck {
	110	compatible = "atmel,sama5d2-clk-audio-pll-pad";
	111	#clock-cells = <0>;
	112	clocks = <&audio_pll_frac>;
	113	};
	114
	115	audio_pll_pmc: audiopll_pmcck {
	116	compatible = "atmel,sama5d2-clk-audio-pll-pmc";
	117	#clock-cells = <0>;
	118	clocks = <&audio_pll_frac>;
	119	};
	120
	121	utmi: utmick {
	122	compatible = "atmel,at91sam9x5-clk-utmi";
	123	#clock-cells = <0>;
	124	clocks = <&main>;
56246d1e	125	regmap-sfr = <&sfr>;
4529ee3b	126	u-boot,dm-pre-reloc;
2c4b2dd2 WY	127	};
	128
	129	mck: masterck {
	130	compatible = "atmel,at91sam9x5-clk-master";
	131	#clock-cells = <0>;
	132	clocks = <&main>, <&plladiv>, <&utmi>;
	133	atmel,clk-output-range = <124000000 166000000>;
	134	atmel,clk-divisors = <1 2 4 3>;
4529ee3b	135	u-boot,dm-pre-reloc;
2c4b2dd2 WY	136	};
	137
	138	h32ck: h32mxck {
	139	#clock-cells = <0>;
	140	compatible = "atmel,sama5d4-clk-h32mx";
	141	clocks = <&mck>;
4529ee3b	142	u-boot,dm-pre-reloc;
2c4b2dd2 WY	143	};
	144
	145	usb: usbck {
	146	compatible = "atmel,at91sam9x5-clk-usb";
	147	#clock-cells = <0>;
	148	clocks = <&plladiv>, <&utmi>;
	149	};
	150
	151	prog: progck {
	152	compatible = "atmel,at91sam9x5-clk-programmable";
	153	#address-cells = <1>;
	154	#size-cells = <0>;
	155	interrupt-parent = <&pmc>;
	156	clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
	157
9e63c49a	158	prog0: prog@0 {
2c4b2dd2 WY	159	#clock-cells = <0>;
	160	reg = <0>;
	161	};
	162
9e63c49a	163	prog1: prog@1 {
2c4b2dd2 WY	164	#clock-cells = <0>;
	165	reg = <1>;
	166	};
	167
9e63c49a	168	prog2: prog@2 {
2c4b2dd2 WY	169	#clock-cells = <0>;
	170	reg = <2>;
	171	};
	172	};
	173
	174	systemck {
	175	compatible = "atmel,at91rm9200-clk-system";
	176	#address-cells = <1>;
	177	#size-cells = <0>;
	178
9e63c49a	179	ddrck: ddrck@2 {
2c4b2dd2 WY	180	#clock-cells = <0>;
	181	reg = <2>;
	182	clocks = <&mck>;
	183	};
	184
9e63c49a	185	lcdck: lcdck@3 {
2c4b2dd2 WY	186	#clock-cells = <0>;
	187	reg = <3>;
	188	clocks = <&mck>;
	189	};
	190
9e63c49a	191	uhpck: uhpck@6 {
2c4b2dd2 WY	192	#clock-cells = <0>;
	193	reg = <6>;
	194	clocks = <&usb>;
	195	};
	196
9e63c49a	197	udpck: udpck@7 {
2c4b2dd2 WY	198	#clock-cells = <0>;
	199	reg = <7>;
	200	clocks = <&usb>;
	201	};
	202
9e63c49a	203	pck0: pck0@8 {
2c4b2dd2 WY	204	#clock-cells = <0>;
	205	reg = <8>;
	206	clocks = <&prog0>;
	207	};
	208
9e63c49a	209	pck1: pck1@9 {
2c4b2dd2 WY	210	#clock-cells = <0>;
	211	reg = <9>;
	212	clocks = <&prog1>;
	213	};
	214
9e63c49a	215	pck2: pck2@10 {
2c4b2dd2 WY	216	#clock-cells = <0>;
	217	reg = <10>;
	218	clocks = <&prog2>;
	219	};
	220
9e63c49a	221	iscck: iscck@18 {
2c4b2dd2 WY	222	#clock-cells = <0>;
	223	reg = <18>;
	224	clocks = <&mck>;
	225	};
	226	};
	227
	228	periph32ck {
	229	compatible = "atmel,at91sam9x5-clk-peripheral";
	230	#address-cells = <1>;
	231	#size-cells = <0>;
	232	clocks = <&h32ck>;
4529ee3b	233	u-boot,dm-pre-reloc;
2c4b2dd2	234
9e63c49a	235	macb0_clk: macb0_clk@5 {
2c4b2dd2 WY	236	#clock-cells = <0>;
	237	reg = <5>;
	238	atmel,clk-output-range = <0 83000000>;
	239	};
	240
9e63c49a	241	tdes_clk: tdes_clk@11 {
2c4b2dd2 WY	242	#clock-cells = <0>;
	243	reg = <11>;
	244	atmel,clk-output-range = <0 83000000>;
	245	};
	246
9e63c49a	247	matrix1_clk: matrix1_clk@14 {
2c4b2dd2 WY	248	#clock-cells = <0>;
	249	reg = <14>;
	250	};
	251
9e63c49a	252	hsmc_clk: hsmc_clk@17 {
2c4b2dd2 WY	253	#clock-cells = <0>;
	254	reg = <17>;
	255	};
	256
9e63c49a	257	pioA_clk: pioA_clk@18 {
2c4b2dd2 WY	258	#clock-cells = <0>;
	259	reg = <18>;
	260	atmel,clk-output-range = <0 83000000>;
4529ee3b	261	u-boot,dm-pre-reloc;
2c4b2dd2 WY	262	};
2c4b2dd2 WY	263
9e63c49a	264	flx0_clk: flx0_clk@19 {
2c4b2dd2 WY	265	#clock-cells = <0>;
	266	reg = <19>;
	267	atmel,clk-output-range = <0 83000000>;
	268	};
	269
9e63c49a	270	flx1_clk: flx1_clk@20 {
2c4b2dd2 WY	271	#clock-cells = <0>;
	272	reg = <20>;
	273	atmel,clk-output-range = <0 83000000>;
	274	};
	275
9e63c49a	276	flx2_clk: flx2_clk@21 {
2c4b2dd2 WY	277	#clock-cells = <0>;
	278	reg = <21>;
	279	atmel,clk-output-range = <0 83000000>;
	280	};
	281
9e63c49a	282	flx3_clk: flx3_clk@22 {
2c4b2dd2 WY	283	#clock-cells = <0>;
	284	reg = <22>;
	285	atmel,clk-output-range = <0 83000000>;
	286	};
	287
9e63c49a	288	flx4_clk: flx4_clk@23 {
2c4b2dd2 WY	289	#clock-cells = <0>;
	290	reg = <23>;
	291	atmel,clk-output-range = <0 83000000>;
	292	};
	293
9e63c49a	294	uart0_clk: uart0_clk@24 {
2c4b2dd2 WY	295	#clock-cells = <0>;
	296	reg = <24>;
	297	atmel,clk-output-range = <0 83000000>;
	298	};
	299
9e63c49a	300	uart1_clk: uart1_clk@25 {
2c4b2dd2 WY	301	#clock-cells = <0>;
	302	reg = <25>;
	303	atmel,clk-output-range = <0 83000000>;
4529ee3b	304	u-boot,dm-pre-reloc;
2c4b2dd2 WY	305	};
2c4b2dd2 WY	306
9e63c49a	307	uart2_clk: uart2_clk@26 {
2c4b2dd2 WY	308	#clock-cells = <0>;
	309	reg = <26>;
	310	atmel,clk-output-range = <0 83000000>;
	311	};
	312
9e63c49a	313	uart3_clk: uart3_clk@27 {
2c4b2dd2 WY	314	#clock-cells = <0>;
	315	reg = <27>;
	316	atmel,clk-output-range = <0 83000000>;
	317	};
	318
9e63c49a	319	uart4_clk: uart4_clk@28 {
2c4b2dd2 WY	320	#clock-cells = <0>;
	321	reg = <28>;
	322	atmel,clk-output-range = <0 83000000>;
	323	};
	324
9e63c49a	325	twi0_clk: twi0_clk@29 {
2c4b2dd2 WY	326	reg = <29>;
	327	#clock-cells = <0>;
	328	atmel,clk-output-range = <0 83000000>;
	329	};
	330
9e63c49a	331	twi1_clk: twi1_clk@30 {
2c4b2dd2 WY	332	#clock-cells = <0>;
	333	reg = <30>;
	334	atmel,clk-output-range = <0 83000000>;
	335	};
	336
9e63c49a	337	spi0_clk: spi0_clk@33 {
2c4b2dd2 WY	338	#clock-cells = <0>;
	339	reg = <33>;
	340	atmel,clk-output-range = <0 83000000>;
4529ee3b	341	u-boot,dm-pre-reloc;
2c4b2dd2 WY	342	};
2c4b2dd2 WY	343
9e63c49a	344	spi1_clk: spi1_clk@34 {
2c4b2dd2 WY	345	#clock-cells = <0>;
	346	reg = <34>;
	347	atmel,clk-output-range = <0 83000000>;
	348	};
	349
9e63c49a	350	tcb0_clk: tcb0_clk@35 {
2c4b2dd2 WY	351	#clock-cells = <0>;
	352	reg = <35>;
	353	atmel,clk-output-range = <0 83000000>;
	354	};
	355
9e63c49a	356	tcb1_clk: tcb1_clk@36 {
2c4b2dd2 WY	357	#clock-cells = <0>;
	358	reg = <36>;
	359	atmel,clk-output-range = <0 83000000>;
	360	};
	361
9e63c49a	362	pwm_clk: pwm_clk@38 {
2c4b2dd2 WY	363	#clock-cells = <0>;
	364	reg = <38>;
	365	atmel,clk-output-range = <0 83000000>;
	366	};
	367
9e63c49a	368	adc_clk: adc_clk@40 {
2c4b2dd2 WY	369	#clock-cells = <0>;
	370	reg = <40>;
	371	atmel,clk-output-range = <0 83000000>;
	372	};
	373
9e63c49a	374	uhphs_clk: uhphs_clk@41 {
2c4b2dd2 WY	375	#clock-cells = <0>;
	376	reg = <41>;
	377	atmel,clk-output-range = <0 83000000>;
	378	};
	379
9e63c49a	380	udphs_clk: udphs_clk@42 {
2c4b2dd2 WY	381	#clock-cells = <0>;
	382	reg = <42>;
	383	atmel,clk-output-range = <0 83000000>;
	384	};
	385
9e63c49a	386	ssc0_clk: ssc0_clk@43 {
2c4b2dd2 WY	387	#clock-cells = <0>;
	388	reg = <43>;
	389	atmel,clk-output-range = <0 83000000>;
	390	};
	391
9e63c49a	392	ssc1_clk: ssc1_clk@44 {
2c4b2dd2 WY	393	#clock-cells = <0>;
	394	reg = <44>;
	395	atmel,clk-output-range = <0 83000000>;
	396	};
	397
9e63c49a	398	trng_clk: trng_clk@47 {
2c4b2dd2 WY	399	#clock-cells = <0>;
	400	reg = <47>;
	401	atmel,clk-output-range = <0 83000000>;
	402	};
	403
9e63c49a	404	pdmic_clk: pdmic_clk@48 {
2c4b2dd2 WY	405	#clock-cells = <0>;
	406	reg = <48>;
	407	atmel,clk-output-range = <0 83000000>;
	408	};
	409
9e63c49a	410	i2s0_clk: i2s0_clk@54 {
2c4b2dd2 WY	411	#clock-cells = <0>;
	412	reg = <54>;
	413	atmel,clk-output-range = <0 83000000>;
	414	};
	415
9e63c49a	416	i2s1_clk: i2s1_clk@55 {
2c4b2dd2 WY	417	#clock-cells = <0>;
	418	reg = <55>;
	419	atmel,clk-output-range = <0 83000000>;
	420	};
	421
9e63c49a	422	can0_clk: can0_clk@56 {
2c4b2dd2 WY	423	#clock-cells = <0>;
	424	reg = <56>;
	425	atmel,clk-output-range = <0 83000000>;
	426	};
	427
9e63c49a	428	can1_clk: can1_clk@57 {
2c4b2dd2 WY	429	#clock-cells = <0>;
	430	reg = <57>;
	431	atmel,clk-output-range = <0 83000000>;
	432	};
	433
9e63c49a	434	classd_clk: classd_clk@59 {
2c4b2dd2 WY	435	#clock-cells = <0>;
	436	reg = <59>;
	437	atmel,clk-output-range = <0 83000000>;
	438	};
	439	};
	440
	441	periph64ck {
	442	compatible = "atmel,at91sam9x5-clk-peripheral";
	443	#address-cells = <1>;
	444	#size-cells = <0>;
	445	clocks = <&mck>;
4529ee3b	446	u-boot,dm-pre-reloc;
2c4b2dd2	447
9e63c49a	448	dma0_clk: dma0_clk@6 {
2c4b2dd2 WY	449	#clock-cells = <0>;
	450	reg = <6>;
	451	};
	452
9e63c49a	453	dma1_clk: dma1_clk@7 {
2c4b2dd2 WY	454	#clock-cells = <0>;
	455	reg = <7>;
	456	};
	457
9e63c49a	458	aes_clk: aes_clk@9 {
2c4b2dd2 WY	459	#clock-cells = <0>;
	460	reg = <9>;
	461	};
	462
9e63c49a	463	aesb_clk: aesb_clk@10 {
2c4b2dd2 WY	464	#clock-cells = <0>;
	465	reg = <10>;
	466	};
	467
9e63c49a	468	sha_clk: sha_clk@12 {
2c4b2dd2 WY	469	#clock-cells = <0>;
	470	reg = <12>;
	471	};
	472
9e63c49a	473	mpddr_clk: mpddr_clk@13 {
2c4b2dd2 WY	474	#clock-cells = <0>;
	475	reg = <13>;
	476	};
	477
9e63c49a	478	matrix0_clk: matrix0_clk@15 {
2c4b2dd2 WY	479	#clock-cells = <0>;
	480	reg = <15>;
	481	};
	482
9e63c49a	483	sdmmc0_hclk: sdmmc0_hclk@31 {
2c4b2dd2 WY	484	#clock-cells = <0>;
2c4b2dd2 WY	485	reg = <31>;
4529ee3b	486	u-boot,dm-pre-reloc;
2c4b2dd2 WY	487	};
2c4b2dd2 WY	488
9e63c49a	489	sdmmc1_hclk: sdmmc1_hclk@32 {
2c4b2dd2 WY	490	#clock-cells = <0>;
2c4b2dd2 WY	491	reg = <32>;
4529ee3b	492	u-boot,dm-pre-reloc;
2c4b2dd2 WY	493	};
2c4b2dd2 WY	494
9e63c49a	495	lcdc_clk: lcdc_clk@45 {
2c4b2dd2 WY	496	#clock-cells = <0>;
	497	reg = <45>;
	498	};
	499
9e63c49a	500	isc_clk: isc_clk@46 {
2c4b2dd2 WY	501	#clock-cells = <0>;
	502	reg = <46>;
	503	};
	504
9e63c49a	505	qspi0_clk: qspi0_clk@52 {
2c4b2dd2 WY	506	#clock-cells = <0>;
2c4b2dd2 WY	507	reg = <52>;
ce4054bf	508	u-boot,dm-pre-reloc;
2c4b2dd2 WY	509	};
2c4b2dd2 WY	510
9e63c49a	511	qspi1_clk: qspi1_clk@53 {
2c4b2dd2 WY	512	#clock-cells = <0>;
2c4b2dd2 WY	513	reg = <53>;
ce4054bf	514	u-boot,dm-pre-reloc;
2c4b2dd2 WY	515	};
	516	};
	517
	518	gck {
	519	compatible = "atmel,sama5d2-clk-generated";
	520	#address-cells = <1>;
	521	#size-cells = <0>;
	522	interrupt-parent = <&pmc>;
	523	clocks = <&main>, <&plla>, <&utmi>, <&mck>;
4529ee3b	524	u-boot,dm-pre-reloc;
2c4b2dd2	525
9e63c49a	526	sdmmc0_gclk: sdmmc0_gclk@31 {
2c4b2dd2 WY	527	#clock-cells = <0>;
2c4b2dd2 WY	528	reg = <31>;
4529ee3b	529	u-boot,dm-pre-reloc;
2c4b2dd2 WY	530	};
2c4b2dd2 WY	531
9e63c49a	532	sdmmc1_gclk: sdmmc1_gclk@32 {
2c4b2dd2 WY	533	#clock-cells = <0>;
2c4b2dd2 WY	534	reg = <32>;
4529ee3b	535	u-boot,dm-pre-reloc;
2c4b2dd2 WY	536	};
2c4b2dd2 WY	537
9e63c49a	538	tcb0_gclk: tcb0_gclk@35 {
2c4b2dd2 WY	539	#clock-cells = <0>;
	540	reg = <35>;
	541	atmel,clk-output-range = <0 83000000>;
	542	};
	543
9e63c49a	544	tcb1_gclk: tcb1_gclk@36 {
2c4b2dd2 WY	545	#clock-cells = <0>;
	546	reg = <36>;
	547	atmel,clk-output-range = <0 83000000>;
	548	};
	549
9e63c49a	550	pwm_gclk: pwm_gclk@38 {
2c4b2dd2 WY	551	#clock-cells = <0>;
	552	reg = <38>;
	553	atmel,clk-output-range = <0 83000000>;
	554	};
	555
9e63c49a	556	pdmic_gclk: pdmic_gclk@48 {
2c4b2dd2 WY	557	#clock-cells = <0>;
	558	reg = <48>;
	559	};
	560
9e63c49a	561	i2s0_gclk: i2s0_gclk@54 {
2c4b2dd2 WY	562	#clock-cells = <0>;
	563	reg = <54>;
	564	};
	565
9e63c49a	566	i2s1_gclk: i2s1_gclk@55 {
2c4b2dd2 WY	567	#clock-cells = <0>;
	568	reg = <55>;
	569	};
	570
9e63c49a	571	can0_gclk: can0_gclk@56 {
2c4b2dd2 WY	572	#clock-cells = <0>;
	573	reg = <56>;
	574	atmel,clk-output-range = <0 80000000>;
	575	};
	576
9e63c49a	577	can1_gclk: can1_gclk@57 {
2c4b2dd2 WY	578	#clock-cells = <0>;
	579	reg = <57>;
	580	atmel,clk-output-range = <0 80000000>;
	581	};
	582
9e63c49a	583	classd_gclk: classd_gclk@59 {
2c4b2dd2 WY	584	#clock-cells = <0>;
	585	reg = <59>;
	586	atmel,clk-output-range = <0 100000000>;
	587	};
	588	};
	589	};
	590
	591	qspi0: spi@f0020000 {
	592	compatible = "atmel,sama5d2-qspi";
	593	reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
	594	reg-names = "qspi_base", "qspi_mmap";
	595	#address-cells = <1>;
	596	#size-cells = <0>;
	597	clocks = <&qspi0_clk>;
	598	status = "disabled";
	599	};
	600
ce4054bf WY	601	qspi1: spi@f0024000 {
	602	compatible = "atmel,sama5d2-qspi";
	603	reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
	604	reg-names = "qspi_base", "qspi_mmap";
	605	#address-cells = <1>;
	606	#size-cells = <0>;
	607	clocks = <&qspi1_clk>;
	608	status = "disabled";
	609	};
	610
2c4b2dd2 WY	611	spi0: spi@f8000000 {
	612	compatible = "atmel,at91rm9200-spi";
	613	reg = <0xf8000000 0x100>;
	614	clocks = <&spi0_clk>;
	615	clock-names = "spi_clk";
	616	#address-cells = <1>;
	617	#size-cells = <0>;
	618	status = "disabled";
	619	};
	620
	621	macb0: ethernet@f8008000 {
	622	compatible = "cdns,macb";
	623	reg = <0xf8008000 0x1000>;
	624	#address-cells = <1>;
	625	#size-cells = <0>;
	626	clocks = <&macb0_clk>, <&macb0_clk>;
	627	clock-names = "hclk", "pclk";
	628	status = "disabled";
	629	};
	630
	631	uart1: serial@f8020000 {
	632	compatible = "atmel,at91sam9260-usart";
	633	reg = <0xf8020000 0x100>;
20bb165c WY	634	clocks = <&uart1_clk>;
20bb165c WY	635	clock-names = "usart";
2c4b2dd2 WY	636	status = "disabled";
	637	};
	638
	639	i2c0: i2c@f8028000 {
	640	compatible = "atmel,sama5d2-i2c";
	641	reg = <0xf8028000 0x100>;
	642	#address-cells = <1>;
	643	#size-cells = <0>;
	644	clocks = <&twi0_clk>;
	645	status = "disabled";
	646	};
	647
fc6adebb WY	648	rstc@f8048000 {
	649	compatible = "atmel,sama5d3-rstc";
	650	reg = <0xf8048000 0x10>;
	651	clocks = <&clk32k>;
	652	};
	653
	654	shdwc@f8048010 {
	655	compatible = "atmel,sama5d2-shdwc";
	656	reg = <0xf8048010 0x10>;
	657	clocks = <&clk32k>;
	658	#address-cells = <1>;
	659	#size-cells = <0>;
	660	atmel,wakeup-rtc-timer;
	661	};
	662
	663	pit: timer@f8048030 {
	664	compatible = "atmel,at91sam9260-pit";
	665	reg = <0xf8048030 0x10>;
	666	clocks = <&h32ck>;
	667	};
	668
	669	watchdog@f8048040 {
	670	compatible = "atmel,sama5d4-wdt";
	671	reg = <0xf8048040 0x10>;
	672	clocks = <&clk32k>;
	673	status = "disabled";
	674	};
	675
56246d1e WY	676	sfr: sfr@f8030000 {
	677	compatible = "atmel,sama5d2-sfr", "syscon";
	678	reg = <0xf8030000 0x98>;
	679	};
	680
2c4b2dd2 WY	681	sckc@f8048050 {
	682	compatible = "atmel,at91sam9x5-sckc";
	683	reg = <0xf8048050 0x4>;
	684
	685	slow_rc_osc: slow_rc_osc {
	686	compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
	687	#clock-cells = <0>;
	688	clock-frequency = <32768>;
	689	clock-accuracy = <250000000>;
	690	atmel,startup-time-usec = <75>;
	691	};
	692
	693	slow_osc: slow_osc {
	694	compatible = "atmel,at91sam9x5-clk-slow-osc";
	695	#clock-cells = <0>;
	696	clocks = <&slow_xtal>;
	697	atmel,startup-time-usec = <1200000>;
	698	};
	699
	700	clk32k: slowck {
	701	compatible = "atmel,at91sam9x5-clk-slow";
	702	#clock-cells = <0>;
	703	clocks = <&slow_rc_osc &slow_osc>;
	704	};
	705	};
	706
	707	spi1: spi@fc000000 {
	708	compatible = "atmel,at91rm9200-spi";
	709	reg = <0xfc000000 0x100>;
	710	#address-cells = <1>;
	711	#size-cells = <0>;
	712	status = "disabled";
	713	};
	714
ce4054bf WY	715	uart3: serial@fc008000 {
	716	compatible = "atmel,at91sam9260-usart";
	717	reg = <0xfc008000 0x100>;
	718	clocks = <&uart3_clk>;
	719	clock-names = "usart";
	720	status = "disabled";
	721	};
	722
2c4b2dd2 WY	723	i2c1: i2c@fc028000 {
	724	compatible = "atmel,sama5d2-i2c";
	725	reg = <0xfc028000 0x100>;
	726	#address-cells = <1>;
	727	#size-cells = <0>;
	728	clocks = <&twi1_clk>;
	729	status = "disabled";
	730	};
	731
	732	pioA: gpio@fc038000 {
	733	compatible = "atmel,sama5d2-gpio";
	734	reg = <0xfc038000 0x600>;
	735	clocks = <&pioA_clk>;
	736	gpio-controller;
	737	#gpio-cells = <2>;
4529ee3b	738	u-boot,dm-pre-reloc;
2c4b2dd2 WY	739
	740	pinctrl {
	741	compatible = "atmel,sama5d2-pinctrl";
4529ee3b	742	u-boot,dm-pre-reloc;
2c4b2dd2 WY	743	};
	744	};
	745	};
	746	};
	747	};