[people/ms/u-boot.git] / arch / arm / dts / sama5d2.dtsi

#include "skeleton.dtsi"

/ {
	model = "Atmel SAMA5D2 family SoC";
	compatible = "atmel,sama5d2";

	aliases {
		spi0 = &spi0;
		spi1 = &qspi0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		u-boot,dm-pre-reloc;

		usb1: ohci@00400000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00400000 0x100000>;
			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb2: ehci@00500000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00500000 0x100000>;
			clocks = <&utmi>, <&uhphs_clk>;
			clock-names = "usb_clk", "ehci_clk";
			status = "disabled";
		};

		sdmmc0: sdio-host@a0000000 {
			compatible = "atmel,sama5d2-sdhci";
			reg = <0xa0000000 0x300>;
			clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
			clock-names = "hclock", "multclk", "baseclk";
			status = "disabled";
		};

		sdmmc1: sdio-host@b0000000 {
			compatible = "atmel,sama5d2-sdhci";
			reg = <0xb0000000 0x300>;
			clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
			clock-names = "hclock", "multclk", "baseclk";
			status = "disabled";
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			u-boot,dm-pre-reloc;

			pmc: pmc@f0014000 {
				compatible = "atmel,sama5d2-pmc", "syscon";
				reg = <0xf0014000 0x160>;
				#address-cells = <1>;
				#size-cells = <0>;
				#interrupt-cells = <1>;
				u-boot,dm-pre-reloc;

				main: mainck {
					compatible = "atmel,at91sam9x5-clk-main";
					#clock-cells = <0>;
					u-boot,dm-pre-reloc;
				};

				plla: pllack@0 {
					compatible = "atmel,sama5d3-clk-pll";
					#clock-cells = <0>;
					clocks = <&main>;
					reg = <0>;
					atmel,clk-input-range = <12000000 12000000>;
					#atmel,pll-clk-output-range-cells = <4>;
					atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
					u-boot,dm-pre-reloc;
				};

				plladiv: plladivck {
					compatible = "atmel,at91sam9x5-clk-plldiv";
					#clock-cells = <0>;
					clocks = <&plla>;
				};

				audio_pll_frac: audiopll_fracck {
					compatible = "atmel,sama5d2-clk-audio-pll-frac";
					#clock-cells = <0>;
					clocks = <&main>;
				};

				audio_pll_pad: audiopll_padck {
					compatible = "atmel,sama5d2-clk-audio-pll-pad";
					#clock-cells = <0>;
					clocks = <&audio_pll_frac>;
				};

				audio_pll_pmc: audiopll_pmcck {
					compatible = "atmel,sama5d2-clk-audio-pll-pmc";
					#clock-cells = <0>;
					clocks = <&audio_pll_frac>;
				};

				utmi: utmick {
					compatible = "atmel,at91sam9x5-clk-utmi";
					#clock-cells = <0>;
					clocks = <&main>;
					u-boot,dm-pre-reloc;
				};

				mck: masterck {
					compatible = "atmel,at91sam9x5-clk-master";
					#clock-cells = <0>;
					clocks = <&main>, <&plladiv>, <&utmi>;
					atmel,clk-output-range = <124000000 166000000>;
					atmel,clk-divisors = <1 2 4 3>;
					u-boot,dm-pre-reloc;
				};

				h32ck: h32mxck {
					#clock-cells = <0>;
					compatible = "atmel,sama5d4-clk-h32mx";
					clocks = <&mck>;
					u-boot,dm-pre-reloc;
				};

				usb: usbck {
					compatible = "atmel,at91sam9x5-clk-usb";
					#clock-cells = <0>;
					clocks = <&plladiv>, <&utmi>;
				};

				prog: progck {
					compatible = "atmel,at91sam9x5-clk-programmable";
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&pmc>;
					clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;

					prog0: prog@0 {
						#clock-cells = <0>;
						reg = <0>;
					};

					prog1: prog@1 {
						#clock-cells = <0>;
						reg = <1>;
					};

					prog2: prog@2 {
						#clock-cells = <0>;
						reg = <2>;
					};
				};

				systemck {
					compatible = "atmel,at91rm9200-clk-system";
					#address-cells = <1>;
					#size-cells = <0>;

					ddrck: ddrck@2 {
						#clock-cells = <0>;
						reg = <2>;
						clocks = <&mck>;
					};

					lcdck: lcdck@3 {
						#clock-cells = <0>;
						reg = <3>;
						clocks = <&mck>;
					};

					uhpck: uhpck@6 {
						#clock-cells = <0>;
						reg = <6>;
						clocks = <&usb>;
					};

					udpck: udpck@7 {
						#clock-cells = <0>;
						reg = <7>;
						clocks = <&usb>;
					};

					pck0: pck0@8 {
						#clock-cells = <0>;
						reg = <8>;
						clocks = <&prog0>;
					};

					pck1: pck1@9 {
						#clock-cells = <0>;
						reg = <9>;
						clocks = <&prog1>;
					};

					pck2: pck2@10 {
						#clock-cells = <0>;
						reg = <10>;
						clocks = <&prog2>;
					};

					iscck: iscck@18 {
						#clock-cells = <0>;
						reg = <18>;
						clocks = <&mck>;
					};
				};

				periph32ck {
					compatible = "atmel,at91sam9x5-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&h32ck>;
					u-boot,dm-pre-reloc;

					macb0_clk: macb0_clk@5 {
						#clock-cells = <0>;
						reg = <5>;
						atmel,clk-output-range = <0 83000000>;
					};

					tdes_clk: tdes_clk@11 {
						#clock-cells = <0>;
						reg = <11>;
						atmel,clk-output-range = <0 83000000>;
					};

					matrix1_clk: matrix1_clk@14 {
						#clock-cells = <0>;
						reg = <14>;
					};

					hsmc_clk: hsmc_clk@17 {
						#clock-cells = <0>;
						reg = <17>;
					};

					pioA_clk: pioA_clk@18 {
						#clock-cells = <0>;
						reg = <18>;
						atmel,clk-output-range = <0 83000000>;
						u-boot,dm-pre-reloc;
					};

					flx0_clk: flx0_clk@19 {
						#clock-cells = <0>;
						reg = <19>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx1_clk: flx1_clk@20 {
						#clock-cells = <0>;
						reg = <20>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx2_clk: flx2_clk@21 {
						#clock-cells = <0>;
						reg = <21>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx3_clk: flx3_clk@22 {
						#clock-cells = <0>;
						reg = <22>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx4_clk: flx4_clk@23 {
						#clock-cells = <0>;
						reg = <23>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart0_clk: uart0_clk@24 {
						#clock-cells = <0>;
						reg = <24>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart1_clk: uart1_clk@25 {
						#clock-cells = <0>;
						reg = <25>;
						atmel,clk-output-range = <0 83000000>;
						u-boot,dm-pre-reloc;
					};

					uart2_clk: uart2_clk@26 {
						#clock-cells = <0>;
						reg = <26>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart3_clk: uart3_clk@27 {
						#clock-cells = <0>;
						reg = <27>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart4_clk: uart4_clk@28 {
						#clock-cells = <0>;
						reg = <28>;
						atmel,clk-output-range = <0 83000000>;
					};

					twi0_clk: twi0_clk@29 {
						reg = <29>;
						#clock-cells = <0>;
						atmel,clk-output-range = <0 83000000>;
					};

					twi1_clk: twi1_clk@30 {
						#clock-cells = <0>;
						reg = <30>;
						atmel,clk-output-range = <0 83000000>;
					};

					spi0_clk: spi0_clk@33 {
						#clock-cells = <0>;
						reg = <33>;
						atmel,clk-output-range = <0 83000000>;
						u-boot,dm-pre-reloc;
					};

					spi1_clk: spi1_clk@34 {
						#clock-cells = <0>;
						reg = <34>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb0_clk: tcb0_clk@35 {
						#clock-cells = <0>;
						reg = <35>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb1_clk: tcb1_clk@36 {
						#clock-cells = <0>;
						reg = <36>;
						atmel,clk-output-range = <0 83000000>;
					};

					pwm_clk: pwm_clk@38 {
						#clock-cells = <0>;
						reg = <38>;
						atmel,clk-output-range = <0 83000000>;
					};

					adc_clk: adc_clk@40 {
						#clock-cells = <0>;
						reg = <40>;
						atmel,clk-output-range = <0 83000000>;
					};

					uhphs_clk: uhphs_clk@41 {
						#clock-cells = <0>;
						reg = <41>;
						atmel,clk-output-range = <0 83000000>;
					};

					udphs_clk: udphs_clk@42 {
						#clock-cells = <0>;
						reg = <42>;
						atmel,clk-output-range = <0 83000000>;
					};

					ssc0_clk: ssc0_clk@43 {
						#clock-cells = <0>;
						reg = <43>;
						atmel,clk-output-range = <0 83000000>;
					};

					ssc1_clk: ssc1_clk@44 {
						#clock-cells = <0>;
						reg = <44>;
						atmel,clk-output-range = <0 83000000>;
					};

					trng_clk: trng_clk@47 {
						#clock-cells = <0>;
						reg = <47>;
						atmel,clk-output-range = <0 83000000>;
					};

					pdmic_clk: pdmic_clk@48 {
						#clock-cells = <0>;
						reg = <48>;
						atmel,clk-output-range = <0 83000000>;
					};

					i2s0_clk: i2s0_clk@54 {
						#clock-cells = <0>;
						reg = <54>;
						atmel,clk-output-range = <0 83000000>;
					};

					i2s1_clk: i2s1_clk@55 {
						#clock-cells = <0>;
						reg = <55>;
						atmel,clk-output-range = <0 83000000>;
					};

					can0_clk: can0_clk@56 {
						#clock-cells = <0>;
						reg = <56>;
						atmel,clk-output-range = <0 83000000>;
					};

					can1_clk: can1_clk@57 {
						#clock-cells = <0>;
						reg = <57>;
						atmel,clk-output-range = <0 83000000>;
					};

					classd_clk: classd_clk@59 {
						#clock-cells = <0>;
						reg = <59>;
						atmel,clk-output-range = <0 83000000>;
					};
				};

				periph64ck {
					compatible = "atmel,at91sam9x5-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&mck>;
					u-boot,dm-pre-reloc;

					dma0_clk: dma0_clk@6 {
						#clock-cells = <0>;
						reg = <6>;
					};

					dma1_clk: dma1_clk@7 {
						#clock-cells = <0>;
						reg = <7>;
					};

					aes_clk: aes_clk@9 {
						#clock-cells = <0>;
						reg = <9>;
					};

					aesb_clk: aesb_clk@10 {
						#clock-cells = <0>;
						reg = <10>;
					};

					sha_clk: sha_clk@12 {
						#clock-cells = <0>;
						reg = <12>;
					};

					mpddr_clk: mpddr_clk@13 {
						#clock-cells = <0>;
						reg = <13>;
					};

					matrix0_clk: matrix0_clk@15 {
						#clock-cells = <0>;
						reg = <15>;
					};

					sdmmc0_hclk: sdmmc0_hclk@31 {
						#clock-cells = <0>;
						reg = <31>;
						u-boot,dm-pre-reloc;
					};

					sdmmc1_hclk: sdmmc1_hclk@32 {
						#clock-cells = <0>;
						reg = <32>;
						u-boot,dm-pre-reloc;
					};

					lcdc_clk: lcdc_clk@45 {
						#clock-cells = <0>;
						reg = <45>;
					};

					isc_clk: isc_clk@46 {
						#clock-cells = <0>;
						reg = <46>;
					};

					qspi0_clk: qspi0_clk@52 {
						#clock-cells = <0>;
						reg = <52>;
					};

					qspi1_clk: qspi1_clk@53 {
						#clock-cells = <0>;
						reg = <53>;
					};
				};

				gck {
					compatible = "atmel,sama5d2-clk-generated";
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&pmc>;
					clocks = <&main>, <&plla>, <&utmi>, <&mck>;
					u-boot,dm-pre-reloc;

					sdmmc0_gclk: sdmmc0_gclk@31 {
						#clock-cells = <0>;
						reg = <31>;
						u-boot,dm-pre-reloc;
					};

					sdmmc1_gclk: sdmmc1_gclk@32 {
						#clock-cells = <0>;
						reg = <32>;
						u-boot,dm-pre-reloc;
					};

					tcb0_gclk: tcb0_gclk@35 {
						#clock-cells = <0>;
						reg = <35>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb1_gclk: tcb1_gclk@36 {
						#clock-cells = <0>;
						reg = <36>;
						atmel,clk-output-range = <0 83000000>;
					};

					pwm_gclk: pwm_gclk@38 {
						#clock-cells = <0>;
						reg = <38>;
						atmel,clk-output-range = <0 83000000>;
					};

					pdmic_gclk: pdmic_gclk@48 {
						#clock-cells = <0>;
						reg = <48>;
					};

					i2s0_gclk: i2s0_gclk@54 {
						#clock-cells = <0>;
						reg = <54>;
					};

					i2s1_gclk: i2s1_gclk@55 {
						#clock-cells = <0>;
						reg = <55>;
					};

					can0_gclk: can0_gclk@56 {
						#clock-cells = <0>;
						reg = <56>;
						atmel,clk-output-range = <0 80000000>;
					};

					can1_gclk: can1_gclk@57 {
						#clock-cells = <0>;
						reg = <57>;
						atmel,clk-output-range = <0 80000000>;
					};

					classd_gclk: classd_gclk@59 {
						#clock-cells = <0>;
						reg = <59>;
						atmel,clk-output-range = <0 100000000>;
					};
				};
			};

			qspi0: spi@f0020000 {
				compatible = "atmel,sama5d2-qspi";
				reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
				reg-names = "qspi_base", "qspi_mmap";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&qspi0_clk>;
				status = "disabled";
			};

			spi0: spi@f8000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf8000000 0x100>;
				clocks = <&spi0_clk>;
				clock-names = "spi_clk";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			macb0: ethernet@f8008000 {
				compatible = "cdns,macb";
				reg = <0xf8008000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&macb0_clk>, <&macb0_clk>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			uart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x100>;
				clocks = <&uart1_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			i2c0: i2c@f8028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xf8028000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&twi0_clk>;
				status = "disabled";
			};

			rstc@f8048000 {
				compatible = "atmel,sama5d3-rstc";
				reg = <0xf8048000 0x10>;
				clocks = <&clk32k>;
			};

			shdwc@f8048010 {
				compatible = "atmel,sama5d2-shdwc";
				reg = <0xf8048010 0x10>;
				clocks = <&clk32k>;
				#address-cells = <1>;
				#size-cells = <0>;
				atmel,wakeup-rtc-timer;
			};

			pit: timer@f8048030 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xf8048030 0x10>;
				clocks = <&h32ck>;
			};

			watchdog@f8048040 {
				compatible = "atmel,sama5d4-wdt";
				reg = <0xf8048040 0x10>;
				clocks = <&clk32k>;
				status = "disabled";
			};

			sckc@f8048050 {
				compatible = "atmel,at91sam9x5-sckc";
				reg = <0xf8048050 0x4>;

				slow_rc_osc: slow_rc_osc {
					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
					#clock-cells = <0>;
					clock-frequency = <32768>;
					clock-accuracy = <250000000>;
					atmel,startup-time-usec = <75>;
				};

				slow_osc: slow_osc {
					compatible = "atmel,at91sam9x5-clk-slow-osc";
					#clock-cells = <0>;
					clocks = <&slow_xtal>;
					atmel,startup-time-usec = <1200000>;
				};

				clk32k: slowck {
					compatible = "atmel,at91sam9x5-clk-slow";
					#clock-cells = <0>;
					clocks = <&slow_rc_osc &slow_osc>;
				};
			};

			spi1: spi@fc000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc000000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@fc028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xfc028000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&twi1_clk>;
				status = "disabled";
			};

			pioA: gpio@fc038000 {
				compatible = "atmel,sama5d2-gpio";
				reg = <0xfc038000 0x600>;
				clocks = <&pioA_clk>;
				gpio-controller;
				#gpio-cells = <2>;
				u-boot,dm-pre-reloc;

				pinctrl {
					compatible = "atmel,sama5d2-pinctrl";
					u-boot,dm-pre-reloc;
				};
			};
		};
	};
};
Commit	Line	Data
2c4b2dd2 WY	1	#include "skeleton.dtsi"
	2
	3	/ {
	4	model = "Atmel SAMA5D2 family SoC";
	5	compatible = "atmel,sama5d2";
	6
	7	aliases {
	8	spi0 = &spi0;
	9	spi1 = &qspi0;
	10	i2c0 = &i2c0;
	11	i2c1 = &i2c1;
	12	};
	13
	14	clocks {
	15	slow_xtal: slow_xtal {
	16	compatible = "fixed-clock";
	17	#clock-cells = <0>;
	18	clock-frequency = <0>;
	19	};
	20
	21	main_xtal: main_xtal {
	22	compatible = "fixed-clock";
	23	#clock-cells = <0>;
	24	clock-frequency = <0>;
	25	};
	26	};
	27
	28	ahb {
	29	compatible = "simple-bus";
	30	#address-cells = <1>;
	31	#size-cells = <1>;
4529ee3b	32	u-boot,dm-pre-reloc;
2c4b2dd2 WY	33
	34	usb1: ohci@00400000 {
	35	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	36	reg = <0x00400000 0x100000>;
	37	clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
	38	clock-names = "ohci_clk", "hclk", "uhpck";
	39	status = "disabled";
	40	};
	41
	42	usb2: ehci@00500000 {
	43	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	44	reg = <0x00500000 0x100000>;
	45	clocks = <&utmi>, <&uhphs_clk>;
	46	clock-names = "usb_clk", "ehci_clk";
	47	status = "disabled";
	48	};
	49
	50	sdmmc0: sdio-host@a0000000 {
	51	compatible = "atmel,sama5d2-sdhci";
	52	reg = <0xa0000000 0x300>;
	53	clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
	54	clock-names = "hclock", "multclk", "baseclk";
	55	status = "disabled";
	56	};
	57
	58	sdmmc1: sdio-host@b0000000 {
	59	compatible = "atmel,sama5d2-sdhci";
	60	reg = <0xb0000000 0x300>;
	61	clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
	62	clock-names = "hclock", "multclk", "baseclk";
	63	status = "disabled";
	64	};
	65
	66	apb {
	67	compatible = "simple-bus";
	68	#address-cells = <1>;
	69	#size-cells = <1>;
4529ee3b	70	u-boot,dm-pre-reloc;
2c4b2dd2 WY	71
	72	pmc: pmc@f0014000 {
	73	compatible = "atmel,sama5d2-pmc", "syscon";
	74	reg = <0xf0014000 0x160>;
	75	#address-cells = <1>;
	76	#size-cells = <0>;
	77	#interrupt-cells = <1>;
4529ee3b	78	u-boot,dm-pre-reloc;
2c4b2dd2 WY	79
	80	main: mainck {
	81	compatible = "atmel,at91sam9x5-clk-main";
	82	#clock-cells = <0>;
4529ee3b	83	u-boot,dm-pre-reloc;
2c4b2dd2 WY	84	};
2c4b2dd2 WY	85
9e63c49a	86	plla: pllack@0 {
2c4b2dd2 WY	87	compatible = "atmel,sama5d3-clk-pll";
	88	#clock-cells = <0>;
	89	clocks = <&main>;
	90	reg = <0>;
	91	atmel,clk-input-range = <12000000 12000000>;
	92	#atmel,pll-clk-output-range-cells = <4>;
	93	atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
4529ee3b	94	u-boot,dm-pre-reloc;
2c4b2dd2 WY	95	};
	96
	97	plladiv: plladivck {
	98	compatible = "atmel,at91sam9x5-clk-plldiv";
	99	#clock-cells = <0>;
	100	clocks = <&plla>;
	101	};
	102
	103	audio_pll_frac: audiopll_fracck {
	104	compatible = "atmel,sama5d2-clk-audio-pll-frac";
	105	#clock-cells = <0>;
	106	clocks = <&main>;
	107	};
	108
	109	audio_pll_pad: audiopll_padck {
	110	compatible = "atmel,sama5d2-clk-audio-pll-pad";
	111	#clock-cells = <0>;
	112	clocks = <&audio_pll_frac>;
	113	};
	114
	115	audio_pll_pmc: audiopll_pmcck {
	116	compatible = "atmel,sama5d2-clk-audio-pll-pmc";
	117	#clock-cells = <0>;
	118	clocks = <&audio_pll_frac>;
	119	};
	120
	121	utmi: utmick {
	122	compatible = "atmel,at91sam9x5-clk-utmi";
	123	#clock-cells = <0>;
	124	clocks = <&main>;
4529ee3b	125	u-boot,dm-pre-reloc;
2c4b2dd2 WY	126	};
	127
	128	mck: masterck {
	129	compatible = "atmel,at91sam9x5-clk-master";
	130	#clock-cells = <0>;
	131	clocks = <&main>, <&plladiv>, <&utmi>;
	132	atmel,clk-output-range = <124000000 166000000>;
	133	atmel,clk-divisors = <1 2 4 3>;
4529ee3b	134	u-boot,dm-pre-reloc;
2c4b2dd2 WY	135	};
	136
	137	h32ck: h32mxck {
	138	#clock-cells = <0>;
	139	compatible = "atmel,sama5d4-clk-h32mx";
	140	clocks = <&mck>;
4529ee3b	141	u-boot,dm-pre-reloc;
2c4b2dd2 WY	142	};
	143
	144	usb: usbck {
	145	compatible = "atmel,at91sam9x5-clk-usb";
	146	#clock-cells = <0>;
	147	clocks = <&plladiv>, <&utmi>;
	148	};
	149
	150	prog: progck {
	151	compatible = "atmel,at91sam9x5-clk-programmable";
	152	#address-cells = <1>;
	153	#size-cells = <0>;
	154	interrupt-parent = <&pmc>;
	155	clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
	156
9e63c49a	157	prog0: prog@0 {
2c4b2dd2 WY	158	#clock-cells = <0>;
	159	reg = <0>;
	160	};
	161
9e63c49a	162	prog1: prog@1 {
2c4b2dd2 WY	163	#clock-cells = <0>;
	164	reg = <1>;
	165	};
	166
9e63c49a	167	prog2: prog@2 {
2c4b2dd2 WY	168	#clock-cells = <0>;
	169	reg = <2>;
	170	};
	171	};
	172
	173	systemck {
	174	compatible = "atmel,at91rm9200-clk-system";
	175	#address-cells = <1>;
	176	#size-cells = <0>;
	177
9e63c49a	178	ddrck: ddrck@2 {
2c4b2dd2 WY	179	#clock-cells = <0>;
	180	reg = <2>;
	181	clocks = <&mck>;
	182	};
	183
9e63c49a	184	lcdck: lcdck@3 {
2c4b2dd2 WY	185	#clock-cells = <0>;
	186	reg = <3>;
	187	clocks = <&mck>;
	188	};
	189
9e63c49a	190	uhpck: uhpck@6 {
2c4b2dd2 WY	191	#clock-cells = <0>;
	192	reg = <6>;
	193	clocks = <&usb>;
	194	};
	195
9e63c49a	196	udpck: udpck@7 {
2c4b2dd2 WY	197	#clock-cells = <0>;
	198	reg = <7>;
	199	clocks = <&usb>;
	200	};
	201
9e63c49a	202	pck0: pck0@8 {
2c4b2dd2 WY	203	#clock-cells = <0>;
	204	reg = <8>;
	205	clocks = <&prog0>;
	206	};
	207
9e63c49a	208	pck1: pck1@9 {
2c4b2dd2 WY	209	#clock-cells = <0>;
	210	reg = <9>;
	211	clocks = <&prog1>;
	212	};
	213
9e63c49a	214	pck2: pck2@10 {
2c4b2dd2 WY	215	#clock-cells = <0>;
	216	reg = <10>;
	217	clocks = <&prog2>;
	218	};
	219
9e63c49a	220	iscck: iscck@18 {
2c4b2dd2 WY	221	#clock-cells = <0>;
	222	reg = <18>;
	223	clocks = <&mck>;
	224	};
	225	};
	226
	227	periph32ck {
	228	compatible = "atmel,at91sam9x5-clk-peripheral";
	229	#address-cells = <1>;
	230	#size-cells = <0>;
	231	clocks = <&h32ck>;
4529ee3b	232	u-boot,dm-pre-reloc;
2c4b2dd2	233
9e63c49a	234	macb0_clk: macb0_clk@5 {
2c4b2dd2 WY	235	#clock-cells = <0>;
	236	reg = <5>;
	237	atmel,clk-output-range = <0 83000000>;
	238	};
	239
9e63c49a	240	tdes_clk: tdes_clk@11 {
2c4b2dd2 WY	241	#clock-cells = <0>;
	242	reg = <11>;
	243	atmel,clk-output-range = <0 83000000>;
	244	};
	245
9e63c49a	246	matrix1_clk: matrix1_clk@14 {
2c4b2dd2 WY	247	#clock-cells = <0>;
	248	reg = <14>;
	249	};
	250
9e63c49a	251	hsmc_clk: hsmc_clk@17 {
2c4b2dd2 WY	252	#clock-cells = <0>;
	253	reg = <17>;
	254	};
	255
9e63c49a	256	pioA_clk: pioA_clk@18 {
2c4b2dd2 WY	257	#clock-cells = <0>;
	258	reg = <18>;
	259	atmel,clk-output-range = <0 83000000>;
4529ee3b	260	u-boot,dm-pre-reloc;
2c4b2dd2 WY	261	};
2c4b2dd2 WY	262
9e63c49a	263	flx0_clk: flx0_clk@19 {
2c4b2dd2 WY	264	#clock-cells = <0>;
	265	reg = <19>;
	266	atmel,clk-output-range = <0 83000000>;
	267	};
	268
9e63c49a	269	flx1_clk: flx1_clk@20 {
2c4b2dd2 WY	270	#clock-cells = <0>;
	271	reg = <20>;
	272	atmel,clk-output-range = <0 83000000>;
	273	};
	274
9e63c49a	275	flx2_clk: flx2_clk@21 {
2c4b2dd2 WY	276	#clock-cells = <0>;
	277	reg = <21>;
	278	atmel,clk-output-range = <0 83000000>;
	279	};
	280
9e63c49a	281	flx3_clk: flx3_clk@22 {
2c4b2dd2 WY	282	#clock-cells = <0>;
	283	reg = <22>;
	284	atmel,clk-output-range = <0 83000000>;
	285	};
	286
9e63c49a	287	flx4_clk: flx4_clk@23 {
2c4b2dd2 WY	288	#clock-cells = <0>;
	289	reg = <23>;
	290	atmel,clk-output-range = <0 83000000>;
	291	};
	292
9e63c49a	293	uart0_clk: uart0_clk@24 {
2c4b2dd2 WY	294	#clock-cells = <0>;
	295	reg = <24>;
	296	atmel,clk-output-range = <0 83000000>;
	297	};
	298
9e63c49a	299	uart1_clk: uart1_clk@25 {
2c4b2dd2 WY	300	#clock-cells = <0>;
	301	reg = <25>;
	302	atmel,clk-output-range = <0 83000000>;
4529ee3b	303	u-boot,dm-pre-reloc;
2c4b2dd2 WY	304	};
2c4b2dd2 WY	305
9e63c49a	306	uart2_clk: uart2_clk@26 {
2c4b2dd2 WY	307	#clock-cells = <0>;
	308	reg = <26>;
	309	atmel,clk-output-range = <0 83000000>;
	310	};
	311
9e63c49a	312	uart3_clk: uart3_clk@27 {
2c4b2dd2 WY	313	#clock-cells = <0>;
	314	reg = <27>;
	315	atmel,clk-output-range = <0 83000000>;
	316	};
	317
9e63c49a	318	uart4_clk: uart4_clk@28 {
2c4b2dd2 WY	319	#clock-cells = <0>;
	320	reg = <28>;
	321	atmel,clk-output-range = <0 83000000>;
	322	};
	323
9e63c49a	324	twi0_clk: twi0_clk@29 {
2c4b2dd2 WY	325	reg = <29>;
	326	#clock-cells = <0>;
	327	atmel,clk-output-range = <0 83000000>;
	328	};
	329
9e63c49a	330	twi1_clk: twi1_clk@30 {
2c4b2dd2 WY	331	#clock-cells = <0>;
	332	reg = <30>;
	333	atmel,clk-output-range = <0 83000000>;
	334	};
	335
9e63c49a	336	spi0_clk: spi0_clk@33 {
2c4b2dd2 WY	337	#clock-cells = <0>;
	338	reg = <33>;
	339	atmel,clk-output-range = <0 83000000>;
4529ee3b	340	u-boot,dm-pre-reloc;
2c4b2dd2 WY	341	};
2c4b2dd2 WY	342
9e63c49a	343	spi1_clk: spi1_clk@34 {
2c4b2dd2 WY	344	#clock-cells = <0>;
	345	reg = <34>;
	346	atmel,clk-output-range = <0 83000000>;
	347	};
	348
9e63c49a	349	tcb0_clk: tcb0_clk@35 {
2c4b2dd2 WY	350	#clock-cells = <0>;
	351	reg = <35>;
	352	atmel,clk-output-range = <0 83000000>;
	353	};
	354
9e63c49a	355	tcb1_clk: tcb1_clk@36 {
2c4b2dd2 WY	356	#clock-cells = <0>;
	357	reg = <36>;
	358	atmel,clk-output-range = <0 83000000>;
	359	};
	360
9e63c49a	361	pwm_clk: pwm_clk@38 {
2c4b2dd2 WY	362	#clock-cells = <0>;
	363	reg = <38>;
	364	atmel,clk-output-range = <0 83000000>;
	365	};
	366
9e63c49a	367	adc_clk: adc_clk@40 {
2c4b2dd2 WY	368	#clock-cells = <0>;
	369	reg = <40>;
	370	atmel,clk-output-range = <0 83000000>;
	371	};
	372
9e63c49a	373	uhphs_clk: uhphs_clk@41 {
2c4b2dd2 WY	374	#clock-cells = <0>;
	375	reg = <41>;
	376	atmel,clk-output-range = <0 83000000>;
	377	};
	378
9e63c49a	379	udphs_clk: udphs_clk@42 {
2c4b2dd2 WY	380	#clock-cells = <0>;
	381	reg = <42>;
	382	atmel,clk-output-range = <0 83000000>;
	383	};
	384
9e63c49a	385	ssc0_clk: ssc0_clk@43 {
2c4b2dd2 WY	386	#clock-cells = <0>;
	387	reg = <43>;
	388	atmel,clk-output-range = <0 83000000>;
	389	};
	390
9e63c49a	391	ssc1_clk: ssc1_clk@44 {
2c4b2dd2 WY	392	#clock-cells = <0>;
	393	reg = <44>;
	394	atmel,clk-output-range = <0 83000000>;
	395	};
	396
9e63c49a	397	trng_clk: trng_clk@47 {
2c4b2dd2 WY	398	#clock-cells = <0>;
	399	reg = <47>;
	400	atmel,clk-output-range = <0 83000000>;
	401	};
	402
9e63c49a	403	pdmic_clk: pdmic_clk@48 {
2c4b2dd2 WY	404	#clock-cells = <0>;
	405	reg = <48>;
	406	atmel,clk-output-range = <0 83000000>;
	407	};
	408
9e63c49a	409	i2s0_clk: i2s0_clk@54 {
2c4b2dd2 WY	410	#clock-cells = <0>;
	411	reg = <54>;
	412	atmel,clk-output-range = <0 83000000>;
	413	};
	414
9e63c49a	415	i2s1_clk: i2s1_clk@55 {
2c4b2dd2 WY	416	#clock-cells = <0>;
	417	reg = <55>;
	418	atmel,clk-output-range = <0 83000000>;
	419	};
	420
9e63c49a	421	can0_clk: can0_clk@56 {
2c4b2dd2 WY	422	#clock-cells = <0>;
	423	reg = <56>;
	424	atmel,clk-output-range = <0 83000000>;
	425	};
	426
9e63c49a	427	can1_clk: can1_clk@57 {
2c4b2dd2 WY	428	#clock-cells = <0>;
	429	reg = <57>;
	430	atmel,clk-output-range = <0 83000000>;
	431	};
	432
9e63c49a	433	classd_clk: classd_clk@59 {
2c4b2dd2 WY	434	#clock-cells = <0>;
	435	reg = <59>;
	436	atmel,clk-output-range = <0 83000000>;
	437	};
	438	};
	439
	440	periph64ck {
	441	compatible = "atmel,at91sam9x5-clk-peripheral";
	442	#address-cells = <1>;
	443	#size-cells = <0>;
	444	clocks = <&mck>;
4529ee3b	445	u-boot,dm-pre-reloc;
2c4b2dd2	446
9e63c49a	447	dma0_clk: dma0_clk@6 {
2c4b2dd2 WY	448	#clock-cells = <0>;
	449	reg = <6>;
	450	};
	451
9e63c49a	452	dma1_clk: dma1_clk@7 {
2c4b2dd2 WY	453	#clock-cells = <0>;
	454	reg = <7>;
	455	};
	456
9e63c49a	457	aes_clk: aes_clk@9 {
2c4b2dd2 WY	458	#clock-cells = <0>;
	459	reg = <9>;
	460	};
	461
9e63c49a	462	aesb_clk: aesb_clk@10 {
2c4b2dd2 WY	463	#clock-cells = <0>;
	464	reg = <10>;
	465	};
	466
9e63c49a	467	sha_clk: sha_clk@12 {
2c4b2dd2 WY	468	#clock-cells = <0>;
	469	reg = <12>;
	470	};
	471
9e63c49a	472	mpddr_clk: mpddr_clk@13 {
2c4b2dd2 WY	473	#clock-cells = <0>;
	474	reg = <13>;
	475	};
	476
9e63c49a	477	matrix0_clk: matrix0_clk@15 {
2c4b2dd2 WY	478	#clock-cells = <0>;
	479	reg = <15>;
	480	};
	481
9e63c49a	482	sdmmc0_hclk: sdmmc0_hclk@31 {
2c4b2dd2 WY	483	#clock-cells = <0>;
2c4b2dd2 WY	484	reg = <31>;
4529ee3b	485	u-boot,dm-pre-reloc;
2c4b2dd2 WY	486	};
2c4b2dd2 WY	487
9e63c49a	488	sdmmc1_hclk: sdmmc1_hclk@32 {
2c4b2dd2 WY	489	#clock-cells = <0>;
2c4b2dd2 WY	490	reg = <32>;
4529ee3b	491	u-boot,dm-pre-reloc;
2c4b2dd2 WY	492	};
2c4b2dd2 WY	493
9e63c49a	494	lcdc_clk: lcdc_clk@45 {
2c4b2dd2 WY	495	#clock-cells = <0>;
	496	reg = <45>;
	497	};
	498
9e63c49a	499	isc_clk: isc_clk@46 {
2c4b2dd2 WY	500	#clock-cells = <0>;
	501	reg = <46>;
	502	};
	503
9e63c49a	504	qspi0_clk: qspi0_clk@52 {
2c4b2dd2 WY	505	#clock-cells = <0>;
	506	reg = <52>;
	507	};
	508
9e63c49a	509	qspi1_clk: qspi1_clk@53 {
2c4b2dd2 WY	510	#clock-cells = <0>;
	511	reg = <53>;
	512	};
	513	};
	514
	515	gck {
	516	compatible = "atmel,sama5d2-clk-generated";
	517	#address-cells = <1>;
	518	#size-cells = <0>;
	519	interrupt-parent = <&pmc>;
	520	clocks = <&main>, <&plla>, <&utmi>, <&mck>;
4529ee3b	521	u-boot,dm-pre-reloc;
2c4b2dd2	522
9e63c49a	523	sdmmc0_gclk: sdmmc0_gclk@31 {
2c4b2dd2 WY	524	#clock-cells = <0>;
2c4b2dd2 WY	525	reg = <31>;
4529ee3b	526	u-boot,dm-pre-reloc;
2c4b2dd2 WY	527	};
2c4b2dd2 WY	528
9e63c49a	529	sdmmc1_gclk: sdmmc1_gclk@32 {
2c4b2dd2 WY	530	#clock-cells = <0>;
2c4b2dd2 WY	531	reg = <32>;
4529ee3b	532	u-boot,dm-pre-reloc;
2c4b2dd2 WY	533	};
2c4b2dd2 WY	534
9e63c49a	535	tcb0_gclk: tcb0_gclk@35 {
2c4b2dd2 WY	536	#clock-cells = <0>;
	537	reg = <35>;
	538	atmel,clk-output-range = <0 83000000>;
	539	};
	540
9e63c49a	541	tcb1_gclk: tcb1_gclk@36 {
2c4b2dd2 WY	542	#clock-cells = <0>;
	543	reg = <36>;
	544	atmel,clk-output-range = <0 83000000>;
	545	};
	546
9e63c49a	547	pwm_gclk: pwm_gclk@38 {
2c4b2dd2 WY	548	#clock-cells = <0>;
	549	reg = <38>;
	550	atmel,clk-output-range = <0 83000000>;
	551	};
	552
9e63c49a	553	pdmic_gclk: pdmic_gclk@48 {
2c4b2dd2 WY	554	#clock-cells = <0>;
	555	reg = <48>;
	556	};
	557
9e63c49a	558	i2s0_gclk: i2s0_gclk@54 {
2c4b2dd2 WY	559	#clock-cells = <0>;
	560	reg = <54>;
	561	};
	562
9e63c49a	563	i2s1_gclk: i2s1_gclk@55 {
2c4b2dd2 WY	564	#clock-cells = <0>;
	565	reg = <55>;
	566	};
	567
9e63c49a	568	can0_gclk: can0_gclk@56 {
2c4b2dd2 WY	569	#clock-cells = <0>;
	570	reg = <56>;
	571	atmel,clk-output-range = <0 80000000>;
	572	};
	573
9e63c49a	574	can1_gclk: can1_gclk@57 {
2c4b2dd2 WY	575	#clock-cells = <0>;
	576	reg = <57>;
	577	atmel,clk-output-range = <0 80000000>;
	578	};
	579
9e63c49a	580	classd_gclk: classd_gclk@59 {
2c4b2dd2 WY	581	#clock-cells = <0>;
	582	reg = <59>;
	583	atmel,clk-output-range = <0 100000000>;
	584	};
	585	};
	586	};
	587
	588	qspi0: spi@f0020000 {
	589	compatible = "atmel,sama5d2-qspi";
	590	reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
	591	reg-names = "qspi_base", "qspi_mmap";
	592	#address-cells = <1>;
	593	#size-cells = <0>;
	594	clocks = <&qspi0_clk>;
	595	status = "disabled";
	596	};
	597
	598	spi0: spi@f8000000 {
	599	compatible = "atmel,at91rm9200-spi";
	600	reg = <0xf8000000 0x100>;
	601	clocks = <&spi0_clk>;
	602	clock-names = "spi_clk";
	603	#address-cells = <1>;
	604	#size-cells = <0>;
	605	status = "disabled";
	606	};
	607
	608	macb0: ethernet@f8008000 {
	609	compatible = "cdns,macb";
	610	reg = <0xf8008000 0x1000>;
	611	#address-cells = <1>;
	612	#size-cells = <0>;
	613	clocks = <&macb0_clk>, <&macb0_clk>;
	614	clock-names = "hclk", "pclk";
	615	status = "disabled";
	616	};
	617
	618	uart1: serial@f8020000 {
	619	compatible = "atmel,at91sam9260-usart";
	620	reg = <0xf8020000 0x100>;
20bb165c WY	621	clocks = <&uart1_clk>;
20bb165c WY	622	clock-names = "usart";
2c4b2dd2 WY	623	status = "disabled";
	624	};
	625
	626	i2c0: i2c@f8028000 {
	627	compatible = "atmel,sama5d2-i2c";
	628	reg = <0xf8028000 0x100>;
	629	#address-cells = <1>;
	630	#size-cells = <0>;
	631	clocks = <&twi0_clk>;
	632	status = "disabled";
	633	};
	634
fc6adebb WY	635	rstc@f8048000 {
	636	compatible = "atmel,sama5d3-rstc";
	637	reg = <0xf8048000 0x10>;
	638	clocks = <&clk32k>;
	639	};
	640
	641	shdwc@f8048010 {
	642	compatible = "atmel,sama5d2-shdwc";
	643	reg = <0xf8048010 0x10>;
	644	clocks = <&clk32k>;
	645	#address-cells = <1>;
	646	#size-cells = <0>;
	647	atmel,wakeup-rtc-timer;
	648	};
	649
	650	pit: timer@f8048030 {
	651	compatible = "atmel,at91sam9260-pit";
	652	reg = <0xf8048030 0x10>;
	653	clocks = <&h32ck>;
	654	};
	655
	656	watchdog@f8048040 {
	657	compatible = "atmel,sama5d4-wdt";
	658	reg = <0xf8048040 0x10>;
	659	clocks = <&clk32k>;
	660	status = "disabled";
	661	};
	662
2c4b2dd2 WY	663	sckc@f8048050 {
	664	compatible = "atmel,at91sam9x5-sckc";
	665	reg = <0xf8048050 0x4>;
	666
	667	slow_rc_osc: slow_rc_osc {
	668	compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
	669	#clock-cells = <0>;
	670	clock-frequency = <32768>;
	671	clock-accuracy = <250000000>;
	672	atmel,startup-time-usec = <75>;
	673	};
	674
	675	slow_osc: slow_osc {
	676	compatible = "atmel,at91sam9x5-clk-slow-osc";
	677	#clock-cells = <0>;
	678	clocks = <&slow_xtal>;
	679	atmel,startup-time-usec = <1200000>;
	680	};
	681
	682	clk32k: slowck {
	683	compatible = "atmel,at91sam9x5-clk-slow";
	684	#clock-cells = <0>;
	685	clocks = <&slow_rc_osc &slow_osc>;
	686	};
	687	};
	688
	689	spi1: spi@fc000000 {
	690	compatible = "atmel,at91rm9200-spi";
	691	reg = <0xfc000000 0x100>;
	692	#address-cells = <1>;
	693	#size-cells = <0>;
	694	status = "disabled";
	695	};
	696
	697	i2c1: i2c@fc028000 {
	698	compatible = "atmel,sama5d2-i2c";
	699	reg = <0xfc028000 0x100>;
	700	#address-cells = <1>;
	701	#size-cells = <0>;
	702	clocks = <&twi1_clk>;
	703	status = "disabled";
	704	};
	705
	706	pioA: gpio@fc038000 {
	707	compatible = "atmel,sama5d2-gpio";
	708	reg = <0xfc038000 0x600>;
	709	clocks = <&pioA_clk>;
	710	gpio-controller;
	711	#gpio-cells = <2>;
4529ee3b	712	u-boot,dm-pre-reloc;
2c4b2dd2 WY	713
	714	pinctrl {
	715	compatible = "atmel,sama5d2-pinctrl";
4529ee3b	716	u-boot,dm-pre-reloc;
2c4b2dd2 WY	717	};
	718	};
	719	};
	720	};
	721	};