[people/ms/u-boot.git] / arch / arm / dts / socfpga_cyclone5_sr1500.dts

/*
 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "SoCFPGA Cyclone V SR1500";
	compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	aliases {
		/*
		 * This allows the ethaddr uboot environment variable
		 * contents to be added to the gmac1 device tree blob.
		 */
		ethernet0 = &gmac1;
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	soc {
		u-boot,dm-pre-reloc;
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	speed-mode = <0>;
};

&i2c1 {
	status = "okay";
	speed-mode = <0>;
};

&mmc0 {
	status = "okay";
	bus-width = <8>;
	u-boot,dm-pre-reloc;
};

&uart0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&watchdog0 {
	status = "okay";
};

&qspi {
	status = "okay";
	u-boot,dm-pre-reloc;

	flash0: n25q00@0 {
		u-boot,dm-pre-reloc;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q00", "spi-flash";
		reg = <0>;      /* chip select */
		spi-max-frequency = <100000000>;
		m25p,fast-read;
		page-size = <256>;
		block-size = <16>; /* 2^16, 64KB */
		read-delay = <4>;  /* delay value in read data capture register */
		tshsl-ns = <50>;
		tsd2d-ns = <50>;
		tchsh-ns = <4>;
		tslch-ns = <4>;
	};
};
Commit	Line	Data
ae9996c8 SR	1	/*
	2	* Copyright (C) 2015 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include "socfpga_cyclone5.dtsi"
	8
	9	/ {
	10	model = "SoCFPGA Cyclone V SR1500";
	11	compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
	12
	13	chosen {
	14	bootargs = "console=ttyS0,115200";
	15	};
	16
	17	aliases {
	18	/*
84f841c5	19	* This allows the ethaddr uboot environment variable
ae9996c8 SR	20	* contents to be added to the gmac1 device tree blob.
	21	*/
	22	ethernet0 = &gmac1;
	23	};
	24
	25	memory@0 {
	26	name = "memory";
	27	device_type = "memory";
	28	reg = <0x0 0x40000000>; /* 1GB */
	29	};
	30
	31	soc {
	32	u-boot,dm-pre-reloc;
	33	};
	34	};
	35
	36	&gmac1 {
	37	status = "okay";
	38	phy-mode = "rgmii";
	39	};
	40
	41	&gpio0 {
	42	status = "okay";
	43	};
	44
	45	&gpio1 {
	46	status = "okay";
	47	};
	48
	49	&gpio2 {
	50	status = "okay";
	51	};
	52
	53	&i2c0 {
	54	status = "okay";
	55	speed-mode = <0>;
	56	};
	57
	58	&i2c1 {
	59	status = "okay";
	60	speed-mode = <0>;
	61	};
	62
	63	&mmc0 {
	64	status = "okay";
	65	bus-width = <8>;
	66	u-boot,dm-pre-reloc;
	67	};
	68
	69	&uart0 {
	70	status = "okay";
	71	};
	72
	73	&usb1 {
	74	status = "okay";
	75	};
	76
	77	&watchdog0 {
	78	status = "okay";
	79	};
	80
	81	&qspi {
	82	status = "okay";
	83	u-boot,dm-pre-reloc;
84
85	flash0: n25q00@0 {
86	u-boot,dm-pre-reloc;
87	#address-cells = <1>;
88	#size-cells = <1>;
89	compatible = "n25q00", "spi-flash";
90	reg = <0>; /* chip select */
93d9fc26	91	spi-max-frequency = <100000000>;
ae9996c8 SR	92	m25p,fast-read;
	93	page-size = <256>;
	94	block-size = <16>; /* 2^16, 64KB */
	95	read-delay = <4>; /* delay value in read data capture register */
	96	tshsl-ns = <50>;
	97	tsd2d-ns = <50>;
	98	tchsh-ns = <4>;
	99	tslch-ns = <4>;
	100	};
	101	};