[people/ms/u-boot.git] / arch / arm / dts / stm32f746-disco.dts

/*
 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
 *
 * Based on:
 * stm32f469-disco.dts from Linux
 * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "stm32f746.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>

/ {
	model = "STMicroelectronics STM32F746-DISCO board";
	compatible = "st,stm32f746-disco", "st,stm32f746";

	chosen {
		bootargs = "root=/dev/ram rdinit=/linuxrc";
		stdout-path = "serial0:115200n8";
	};

	memory {
		reg = <0xC0000000 0x800000>;
	};

	aliases {
		serial0 = &usart1;
		spi0 = &qspi;
		/* Aliases for gpios so as to use sequence */
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		gpio9 = &gpioj;
		gpio10 = &gpiok;
	};

	led1 {
		compatible = "st,led1";
		led-gpio = <&gpioi 1 0>;
	};

	button1 {
		compatible = "st,button1";
		button-gpio = <&gpioi 11 0>;
	};
};

&clk_hse {
	clock-frequency = <25000000>;
};

&pinctrl {
	usart1_pins_a: usart1@0	{
		pins1 {
		       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
				bias-disable;
				drive-push-pull;
				slew-rate = <2>;
		};
		pins2 {
			pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
			bias-disable;
		};
	};

	ethernet_mii: mii@0 {
	      pins {
		      pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
			     <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
			     <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
			     <STM32F746_PA2_FUNC_ETH_MDIO>,
			     <STM32F746_PC1_FUNC_ETH_MDC>,
			     <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
			     <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
			     <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
			     <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
		      slew-rate = <2>;
	      };
	};

	qspi_pins: qspi@0 {
		pins {
			pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
			       <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
			       <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
			       <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
			       <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
			       <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
			slew-rate = <2>;
		};
	};

	fmc_pins: fmc@0 {
		pins {
			pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
				 <STM32F746_PD9_FUNC_FMC_D14>,
				 <STM32F746_PD8_FUNC_FMC_D13>,
				 <STM32F746_PE15_FUNC_FMC_D12>,
				 <STM32F746_PE14_FUNC_FMC_D11>,
				 <STM32F746_PE13_FUNC_FMC_D10>,
				 <STM32F746_PE12_FUNC_FMC_D9>,
				 <STM32F746_PE11_FUNC_FMC_D8>,
				 <STM32F746_PE10_FUNC_FMC_D7>,
				 <STM32F746_PE9_FUNC_FMC_D6>,
				 <STM32F746_PE8_FUNC_FMC_D5>,
				 <STM32F746_PE7_FUNC_FMC_D4>,
				 <STM32F746_PD1_FUNC_FMC_D3>,
				 <STM32F746_PD0_FUNC_FMC_D2>,
				 <STM32F746_PD15_FUNC_FMC_D1>,
				 <STM32F746_PD14_FUNC_FMC_D0>,

				 <STM32F746_PE1_FUNC_FMC_NBL1>,
				 <STM32F746_PE0_FUNC_FMC_NBL0>,

				 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
				 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,

				 <STM32F746_PG1_FUNC_FMC_A11>,
				 <STM32F746_PG0_FUNC_FMC_A10>,
				 <STM32F746_PF15_FUNC_FMC_A9>,
				 <STM32F746_PF14_FUNC_FMC_A8>,
				 <STM32F746_PF13_FUNC_FMC_A7>,
				 <STM32F746_PF12_FUNC_FMC_A6>,
				 <STM32F746_PF5_FUNC_FMC_A5>,
				 <STM32F746_PF4_FUNC_FMC_A4>,
				 <STM32F746_PF3_FUNC_FMC_A3>,
				 <STM32F746_PF2_FUNC_FMC_A2>,
				 <STM32F746_PF1_FUNC_FMC_A1>,
				 <STM32F746_PF0_FUNC_FMC_A0>,

				 <STM32F746_PH3_FUNC_FMC_SDNE0>,
				 <STM32F746_PH5_FUNC_FMC_SDNWE>,
				 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
				 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
				 <STM32F746_PC3_FUNC_FMC_SDCKE0>,
				 <STM32F746_PG8_FUNC_FMC_SDCLK>;
			  slew-rate = <2>;
		};
	};
};

&usart1 {
	pinctrl-0 = <&usart1_pins_a>;
	pinctrl-names = "default";
	status = "okay";
};

&fmc {
	pinctrl-0 = <&fmc_pins>;
	pinctrl-names = "default";
	status = "okay";

	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
	bank1: bank@0 {
	       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
	       				    CAS_3 SDCLK_2 RD_BURST_EN
					    RD_PIPE_DL_0>;
	       st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
	       				   TRP_2 TRCD_2>;
		/* refcount = (64msec/total_row_sdram)*freq - 20 */
	       st,sdram-refcount = < 1542 >;
       };
};

&mac {
	status = "okay";
	pinctrl-0 = <&ethernet_mii>;
	phy-mode = "rmii";
	phy-handle = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&qspi {
	pinctrl-0 = <&qspi_pins>;
	status = "okay";

	qflash0: n25q128a {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "micron,n25q128a13", "spi-flash";
			spi-max-frequency = <108000000>;
			spi-tx-bus-width = <1>;
			spi-rx-bus-width = <1>;
			memory-map = <0x90000000 0x1000000>;
			reg = <0>;
	};
};
Commit	Line	Data
b1a8de7e MK	1	/*
b1a8de7e MK	2	* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
fd198ee1	3	* Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
b1a8de7e MK	4	*
	5	* Based on:
	6	* stm32f469-disco.dts from Linux
	7	* Copyright 2016 - Lee Jones <lee.jones@linaro.org>
	8	*
	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of the
	17	* License, or (at your option) any later version.
	18	*
	19	* This file is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* Or, alternatively,
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use,
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
	46	*/
	47
	48	/dts-v1/;
	49	#include "stm32f746.dtsi"
6c9a1003	50	#include <dt-bindings/memory/stm32-sdram.h>
b1a8de7e MK	51
	52	/ {
	53	model = "STMicroelectronics STM32F746-DISCO board";
	54	compatible = "st,stm32f746-disco", "st,stm32f746";
	55
	56	chosen {
	57	bootargs = "root=/dev/ram rdinit=/linuxrc";
	58	stdout-path = "serial0:115200n8";
	59	};
	60
	61	memory {
	62	reg = <0xC0000000 0x800000>;
	63	};
	64
	65	aliases {
84bfdc17	66	serial0 = &usart1;
b1a8de7e	67	spi0 = &qspi;
d33a6a2f VM	68	/* Aliases for gpios so as to use sequence */
	69	gpio0 = &gpioa;
	70	gpio1 = &gpiob;
	71	gpio2 = &gpioc;
	72	gpio3 = &gpiod;
	73	gpio4 = &gpioe;
	74	gpio5 = &gpiof;
	75	gpio6 = &gpiog;
	76	gpio7 = &gpioh;
	77	gpio8 = &gpioi;
	78	gpio9 = &gpioj;
	79	gpio10 = &gpiok;
b1a8de7e	80	};
2f80a9f7 VM	81
	82	led1 {
	83	compatible = "st,led1";
	84	led-gpio = <&gpioi 1 0>;
	85	};
	86
	87	button1 {
	88	compatible = "st,button1";
	89	button-gpio = <&gpioi 11 0>;
	90	};
b1a8de7e MK	91	};
b1a8de7e MK	92
84bfdc17 VM	93	&clk_hse {
	94	clock-frequency = <25000000>;
	95	};
	96
bd4a985f VM	97	&pinctrl {
	98	usart1_pins_a: usart1@0 {
	99	pins1 {
	100	pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
	101	bias-disable;
	102	drive-push-pull;
	103	slew-rate = <2>;
	104	};
	105	pins2 {
	106	pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
	107	bias-disable;
	108	};
	109	};
	110
	111	ethernet_mii: mii@0 {
	112	pins {
	113	pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
	114	<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
	115	<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
	116	<STM32F746_PA2_FUNC_ETH_MDIO>,
	117	<STM32F746_PC1_FUNC_ETH_MDC>,
	118	<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
	119	<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
	120	<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
	121	<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
	122	slew-rate = <2>;
	123	};
	124	};
	125
	126	qspi_pins: qspi@0 {
	127	pins {
	128	pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
	129	<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
	130	<STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
	131	<STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
	132	<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
	133	<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
	134	slew-rate = <2>;
	135	};
	136	};
	137
	138	fmc_pins: fmc@0 {
	139	pins {
	140	pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
	141	<STM32F746_PD9_FUNC_FMC_D14>,
	142	<STM32F746_PD8_FUNC_FMC_D13>,
	143	<STM32F746_PE15_FUNC_FMC_D12>,
	144	<STM32F746_PE14_FUNC_FMC_D11>,
	145	<STM32F746_PE13_FUNC_FMC_D10>,
	146	<STM32F746_PE12_FUNC_FMC_D9>,
	147	<STM32F746_PE11_FUNC_FMC_D8>,
	148	<STM32F746_PE10_FUNC_FMC_D7>,
	149	<STM32F746_PE9_FUNC_FMC_D6>,
	150	<STM32F746_PE8_FUNC_FMC_D5>,
	151	<STM32F746_PE7_FUNC_FMC_D4>,
	152	<STM32F746_PD1_FUNC_FMC_D3>,
	153	<STM32F746_PD0_FUNC_FMC_D2>,
	154	<STM32F746_PD15_FUNC_FMC_D1>,
	155	<STM32F746_PD14_FUNC_FMC_D0>,
	156
	157	<STM32F746_PE1_FUNC_FMC_NBL1>,
	158	<STM32F746_PE0_FUNC_FMC_NBL0>,
	159
	160	<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
161	<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
162
163	<STM32F746_PG1_FUNC_FMC_A11>,
164	<STM32F746_PG0_FUNC_FMC_A10>,
165	<STM32F746_PF15_FUNC_FMC_A9>,
166	<STM32F746_PF14_FUNC_FMC_A8>,
167	<STM32F746_PF13_FUNC_FMC_A7>,
168	<STM32F746_PF12_FUNC_FMC_A6>,
169	<STM32F746_PF5_FUNC_FMC_A5>,
170	<STM32F746_PF4_FUNC_FMC_A4>,
171	<STM32F746_PF3_FUNC_FMC_A3>,
172	<STM32F746_PF2_FUNC_FMC_A2>,
173	<STM32F746_PF1_FUNC_FMC_A1>,
174	<STM32F746_PF0_FUNC_FMC_A0>,
175
176	<STM32F746_PH3_FUNC_FMC_SDNE0>,
177	<STM32F746_PH5_FUNC_FMC_SDNWE>,
178	<STM32F746_PF11_FUNC_FMC_SDNRAS>,
179	<STM32F746_PG15_FUNC_FMC_SDNCAS>,
180	<STM32F746_PC3_FUNC_FMC_SDCKE0>,
181	<STM32F746_PG8_FUNC_FMC_SDCLK>;
182	slew-rate = <2>;
183	};
184	};
185	};
186
e34e19fe VM	187	&usart1 {
	188	pinctrl-0 = <&usart1_pins_a>;
	189	pinctrl-names = "default";
	190	status = "okay";
	191	};
	192
fd198ee1 VM	193	&fmc {
	194	pinctrl-0 = <&fmc_pins>;
	195	pinctrl-names = "default";
	196	status = "okay";
6c9a1003	197
bfea69ad	198	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
6c9a1003	199	bank1: bank@0 {
bfea69ad VM	200	st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
	201	CAS_3 SDCLK_2 RD_BURST_EN
	202	RD_PIPE_DL_0>;
	203	st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
	204	TRP_2 TRCD_2>;
	205	/* refcount = (64msec/total_row_sdram)freq - 20 /
	206	st,sdram-refcount = < 1542 >;
6c9a1003	207	};
fd198ee1 VM	208	};
fd198ee1 VM	209
b1a8de7e MK	210	&mac {
b1a8de7e MK	211	status = "okay";
c428a958	212	pinctrl-0 = <&ethernet_mii>;
b1a8de7e MK	213	phy-mode = "rmii";
	214	phy-handle = <&phy0>;
	215
	216	mdio0 {
	217	#address-cells = <1>;
	218	#size-cells = <0>;
	219	compatible = "snps,dwmac-mdio";
	220	phy0: ethernet-phy@0 {
	221	reg = <0>;
	222	};
	223	};
	224	};
	225
	226	&qspi {
e245f1a5	227	pinctrl-0 = <&qspi_pins>;
b1a8de7e MK	228	status = "okay";
	229
	230	qflash0: n25q128a {
	231	#address-cells = <1>;
	232	#size-cells = <1>;
	233	compatible = "micron,n25q128a13", "spi-flash";
	234	spi-max-frequency = <108000000>;
	235	spi-tx-bus-width = <1>;
	236	spi-rx-bus-width = <1>;
	237	memory-map = <0x90000000 0x1000000>;
	238	reg = <0>;
	239	};
	240	};