[people/ms/u-boot.git] / arch / arm / dts / stm32f746.dtsi

/*
 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
 *
 * Based on:
 * stm32f429.dtsi from Linux
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
};

	soc {
		u-boot,dm-pre-reloc;
		mac: ethernet@40028000 {
			compatible = "st,stm32-dwmac";
			reg = <0x40028000 0x8000>;
			reg-names = "stmmaceth";
			interrupts = <61>, <62>;
			interrupt-names = "macirq", "eth_wake_irq";
			snps,pbl = <8>;
			snps,mixed-burst;
			dma-ranges;
			status = "disabled";
		};

		fmc: fmc@A0000000 {
			compatible = "st,stm32-fmc";
			reg = <0xA0000000 0x1000>;
			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
			u-boot,dm-pre-reloc;
		};

		qspi: quadspi@A0001000 {
			compatible = "st,stm32-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <92>;
			spi-max-frequency = <108000000>;
			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
			status = "disabled";
		};
		usart1: serial@40011000 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
			status = "disabled";
			u-boot,dm-pre-reloc;
		};

		pwrcfg: power-config@58024800 {
			compatible = "syscon";
			reg = <0x40007000 0x400>;
		};

		rcc: rcc@40023810 {
			#reset-cells = <1>;
			#clock-cells = <2>;
			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>;
			st,syscfg = <&pwrcfg>;
			u-boot,dm-pre-reloc;
		};

		pinctrl: pin-controller {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32f746-pinctrl";
			ranges = <0 0x40020000 0x3000>;
			u-boot,dm-pre-reloc;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x0 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
				st,bank-name = "GPIOA";
				u-boot,dm-pre-reloc;
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
				st,bank-name = "GPIOB";
				u-boot,dm-pre-reloc;
			};


			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
				st,bank-name = "GPIOC";
				u-boot,dm-pre-reloc;
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
				st,bank-name = "GPIOD";
				u-boot,dm-pre-reloc;
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
				st,bank-name = "GPIOE";
				u-boot,dm-pre-reloc;
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
				st,bank-name = "GPIOF";
				u-boot,dm-pre-reloc;
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
				st,bank-name = "GPIOG";
				u-boot,dm-pre-reloc;
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
				st,bank-name = "GPIOH";
				u-boot,dm-pre-reloc;
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
				st,bank-name = "GPIOI";
				u-boot,dm-pre-reloc;
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
				st,bank-name = "GPIOJ";
				u-boot,dm-pre-reloc;
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
				st,bank-name = "GPIOK";
				u-boot,dm-pre-reloc;
			};

		};
	};
};

&systick {
	status = "okay";
};
Commit	Line	Data
b1a8de7e MK	1	/*
b1a8de7e MK	2	* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
fd198ee1	3	* Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
b1a8de7e MK	4	*
	5	* Based on:
	6	* stm32f429.dtsi from Linux
	7	* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
	8	*
	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of the
	17	* License, or (at your option) any later version.
	18	*
	19	* This file is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* Or, alternatively,
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use,
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
	46	*/
	47
	48	#include "armv7-m.dtsi"
	49	#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
fa87abb6 PC	50	#include <dt-bindings/clock/stm32fx-clock.h>
fa87abb6 PC	51	#include <dt-bindings/mfd/stm32f7-rcc.h>
b1a8de7e MK	52
b1a8de7e MK	53	/ {
84bfdc17 VM	54	clocks {
	55	clk_hse: clk-hse {
	56	#clock-cells = <0>;
	57	compatible = "fixed-clock";
	58	clock-frequency = <0>;
	59	};
	60	};
	61
b1a8de7e	62	soc {
84bfdc17	63	u-boot,dm-pre-reloc;
b1a8de7e MK	64	mac: ethernet@40028000 {
	65	compatible = "st,stm32-dwmac";
	66	reg = <0x40028000 0x8000>;
	67	reg-names = "stmmaceth";
	68	interrupts = <61>, <62>;
	69	interrupt-names = "macirq", "eth_wake_irq";
	70	snps,pbl = <8>;
	71	snps,mixed-burst;
	72	dma-ranges;
	73	status = "disabled";
	74	};
	75
fd198ee1 VM	76	fmc: fmc@A0000000 {
	77	compatible = "st,stm32-fmc";
	78	reg = <0xA0000000 0x1000>;
fa87abb6	79	clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
fd198ee1 VM	80	u-boot,dm-pre-reloc;
	81	};
	82
b1a8de7e MK	83	qspi: quadspi@A0001000 {
	84	compatible = "st,stm32-qspi";
	85	#address-cells = <1>;
	86	#size-cells = <0>;
	87	reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
	88	reg-names = "QuadSPI", "QuadSPI-memory";
	89	interrupts = <92>;
	90	spi-max-frequency = <108000000>;
fa87abb6	91	clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
b1a8de7e MK	92	status = "disabled";
b1a8de7e MK	93	};
84bfdc17	94	usart1: serial@40011000 {
1113ad49	95	compatible = "st,stm32f7-usart", "st,stm32f7-uart";
84bfdc17 VM	96	reg = <0x40011000 0x400>;
84bfdc17 VM	97	interrupts = <37>;
fa87abb6	98	clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
84bfdc17 VM	99	status = "disabled";
	100	u-boot,dm-pre-reloc;
	101	};
d3651aac PC	102
	103	pwrcfg: power-config@58024800 {
	104	compatible = "syscon";
	105	reg = <0x40007000 0x400>;
	106	};
	107
84bfdc17 VM	108	rcc: rcc@40023810 {
	109	#reset-cells = <1>;
	110	#clock-cells = <2>;
1555903c	111	compatible = "st,stm32f746-rcc", "st,stm32-rcc";
84bfdc17 VM	112	reg = <0x40023800 0x400>;
84bfdc17 VM	113	clocks = <&clk_hse>;
d3651aac	114	st,syscfg = <&pwrcfg>;
84bfdc17 VM	115	u-boot,dm-pre-reloc;
	116	};
	117
da4e17f2 VM	118	pinctrl: pin-controller {
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	compatible = "st,stm32f746-pinctrl";
	122	ranges = <0 0x40020000 0x3000>;
	123	u-boot,dm-pre-reloc;
	124	pins-are-numbered;
e34e19fe	125
d33a6a2f VM	126	gpioa: gpio@40020000 {
	127	gpio-controller;
	128	#gpio-cells = <2>;
	129	compatible = "st,stm32-gpio";
	130	reg = <0x0 0x400>;
fa87abb6	131	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
d33a6a2f VM	132	st,bank-name = "GPIOA";
	133	u-boot,dm-pre-reloc;
	134	};
	135
	136	gpiob: gpio@40020400 {
	137	gpio-controller;
	138	#gpio-cells = <2>;
	139	compatible = "st,stm32-gpio";
	140	reg = <0x400 0x400>;
fa87abb6	141	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
d33a6a2f VM	142	st,bank-name = "GPIOB";
	143	u-boot,dm-pre-reloc;
	144	};
	145
	146
	147	gpioc: gpio@40020800 {
	148	gpio-controller;
	149	#gpio-cells = <2>;
	150	compatible = "st,stm32-gpio";
	151	reg = <0x800 0x400>;
fa87abb6	152	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
d33a6a2f VM	153	st,bank-name = "GPIOC";
	154	u-boot,dm-pre-reloc;
	155	};
	156
	157	gpiod: gpio@40020c00 {
	158	gpio-controller;
	159	#gpio-cells = <2>;
	160	compatible = "st,stm32-gpio";
	161	reg = <0xc00 0x400>;
fa87abb6	162	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
d33a6a2f VM	163	st,bank-name = "GPIOD";
	164	u-boot,dm-pre-reloc;
	165	};
	166
	167	gpioe: gpio@40021000 {
	168	gpio-controller;
	169	#gpio-cells = <2>;
	170	compatible = "st,stm32-gpio";
	171	reg = <0x1000 0x400>;
fa87abb6	172	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
d33a6a2f VM	173	st,bank-name = "GPIOE";
	174	u-boot,dm-pre-reloc;
	175	};
	176
	177	gpiof: gpio@40021400 {
	178	gpio-controller;
	179	#gpio-cells = <2>;
	180	compatible = "st,stm32-gpio";
	181	reg = <0x1400 0x400>;
fa87abb6	182	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
d33a6a2f VM	183	st,bank-name = "GPIOF";
	184	u-boot,dm-pre-reloc;
	185	};
	186
	187	gpiog: gpio@40021800 {
	188	gpio-controller;
	189	#gpio-cells = <2>;
	190	compatible = "st,stm32-gpio";
	191	reg = <0x1800 0x400>;
fa87abb6	192	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
d33a6a2f VM	193	st,bank-name = "GPIOG";
	194	u-boot,dm-pre-reloc;
	195	};
	196
	197	gpioh: gpio@40021c00 {
	198	gpio-controller;
	199	#gpio-cells = <2>;
	200	compatible = "st,stm32-gpio";
	201	reg = <0x1c00 0x400>;
fa87abb6	202	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
d33a6a2f VM	203	st,bank-name = "GPIOH";
	204	u-boot,dm-pre-reloc;
	205	};
	206
	207	gpioi: gpio@40022000 {
	208	gpio-controller;
	209	#gpio-cells = <2>;
	210	compatible = "st,stm32-gpio";
	211	reg = <0x2000 0x400>;
fa87abb6	212	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
d33a6a2f VM	213	st,bank-name = "GPIOI";
	214	u-boot,dm-pre-reloc;
	215	};
	216
	217	gpioj: gpio@40022400 {
	218	gpio-controller;
	219	#gpio-cells = <2>;
	220	compatible = "st,stm32-gpio";
	221	reg = <0x2400 0x400>;
fa87abb6	222	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
d33a6a2f VM	223	st,bank-name = "GPIOJ";
	224	u-boot,dm-pre-reloc;
	225	};
	226
	227	gpiok: gpio@40022800 {
	228	gpio-controller;
	229	#gpio-cells = <2>;
	230	compatible = "st,stm32-gpio";
	231	reg = <0x2800 0x400>;
fa87abb6	232	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
d33a6a2f VM	233	st,bank-name = "GPIOK";
	234	u-boot,dm-pre-reloc;
	235	};
	236
da4e17f2	237	};
b1a8de7e MK	238	};
	239	};
	240
	241	&systick {
	242	status = "okay";
	243	};