[people/ms/u-boot.git] / arch / arm / dts / sun50i-a64.dtsi

/*
 * Copyright (C) 2016 ARM Ltd.
 * based on the Allwinner H3 dtsi:
 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <3>;
			enable-method = "psci";
		};
	};

	osc24M: osc24M_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "osc24M";
	};

	osc32k: osc32k_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "osc32k";
	};

	iosc: internal-osc-clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-accuracy = <300000000>;
		clock-output-names = "iosc";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mmc0: mmc@1c0f000 {
			compatible = "allwinner,sun50i-a64-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
			clock-names = "ahb", "mmc";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <150000000>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@1c10000 {
			compatible = "allwinner,sun50i-a64-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
			clock-names = "ahb", "mmc";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <150000000>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@1c11000 {
			compatible = "allwinner,sun50i-a64-emmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
			clock-names = "ahb", "mmc";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <200000000>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_otg: usb@01c19000 {
			compatible = "allwinner,sun8i-a33-musb";
			reg = <0x01c19000 0x0400>;
			clocks = <&ccu CLK_BUS_OTG>;
			resets = <&ccu RST_BUS_OTG>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			status = "disabled";
		};

		usbphy: phy@01c19400 {
			compatible = "allwinner,sun50i-a64-usb-phy";
			reg = <0x01c19400 0x14>,
			      <0x01c1a800 0x4>,
			      <0x01c1b800 0x4>;
			reg-names = "phy_ctrl",
				    "pmu0",
				    "pmu1";
			clocks = <&ccu CLK_USB_PHY0>,
				 <&ccu CLK_USB_PHY1>;
			clock-names = "usb0_phy",
				      "usb1_phy";
			resets = <&ccu RST_USB_PHY0>,
				 <&ccu RST_USB_PHY1>;
			reset-names = "usb0_reset",
				      "usb1_reset";
			status = "disabled";
			#phy-cells = <1>;
		};

		ehci0: usb@01c1a000 {
			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
			reg = <0x01c1a000 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>,
				 <&ccu CLK_BUS_EHCI0>,
				 <&ccu CLK_USB_OHCI0>;
			resets = <&ccu RST_BUS_OHCI0>,
				 <&ccu RST_BUS_EHCI0>;
			status = "disabled";
		};

		ohci0: usb@01c1a400 {
			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
			reg = <0x01c1a400 0x100>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>,
				 <&ccu CLK_USB_OHCI0>;
			resets = <&ccu RST_BUS_OHCI0>;
			status = "disabled";
		};

		ehci1: usb@01c1b000 {
			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
			reg = <0x01c1b000 0x100>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI1>,
				 <&ccu CLK_BUS_EHCI1>,
				 <&ccu CLK_USB_OHCI1>;
			resets = <&ccu RST_BUS_OHCI1>,
				 <&ccu RST_BUS_EHCI1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci1: usb@01c1b400 {
			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
			reg = <0x01c1b400 0x100>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI1>,
				 <&ccu CLK_USB_OHCI1>;
			resets = <&ccu RST_BUS_OHCI1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ccu: clock@01c20000 {
			compatible = "allwinner,sun50i-a64-ccu";
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pio: pinctrl@1c20800 {
			compatible = "allwinner,sun50i-a64-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu 58>;
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;

			i2c1_pins: i2c1_pins {
				pins = "PH2", "PH3";
				function = "i2c1";
			};

			mmc0_pins: mmc0-pins {
				pins = "PF0", "PF1", "PF2", "PF3",
				       "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc1_pins: mmc1-pins {
				pins = "PG0", "PG1", "PG2", "PG3",
				       "PG4", "PG5";
				function = "mmc1";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc2_pins: mmc2-pins {
				pins = "PC1", "PC5", "PC6", "PC8", "PC9",
				       "PC10","PC11", "PC12", "PC13",
				       "PC14", "PC15", "PC16";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			uart0_pins_a: uart0@0 {
				pins = "PB8", "PB9";
				function = "uart0";
			};

			uart1_pins: uart1_pins {
				pins = "PG6", "PG7";
				function = "uart1";
			};

			uart1_rts_cts_pins: uart1_rts_cts_pins {
				pins = "PG8", "PG9";
				function = "uart1";
			};
		};

		uart0: serial@1c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu 67>;
			resets = <&ccu 46>;
			status = "disabled";
		};

		uart1: serial@1c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu 68>;
			resets = <&ccu 47>;
			status = "disabled";
		};

		uart2: serial@1c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu 69>;
			resets = <&ccu 48>;
			status = "disabled";
		};

		uart3: serial@1c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu 70>;
			resets = <&ccu 49>;
			status = "disabled";
		};

		uart4: serial@1c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu 71>;
			resets = <&ccu 50>;
			status = "disabled";
		};

		i2c0: i2c@1c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu 63>;
			resets = <&ccu 42>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@1c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu 64>;
			resets = <&ccu 43>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@1c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu 65>;
			resets = <&ccu 44>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gic: interrupt-controller@1c81000 {
			compatible = "arm,gic-400";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x2000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		rtc: rtc@1f00000 {
			compatible = "allwinner,sun6i-a31-rtc";
			reg = <0x01f00000 0x54>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		};

		r_ccu: clock@1f01400 {
			compatible = "allwinner,sun50i-a64-r-ccu";
			reg = <0x01f01400 0x100>;
			clocks = <&osc24M>, <&osc32k>, <&iosc>;
			clock-names = "hosc", "losc", "iosc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		r_pio: pinctrl@01f02c00 {
			compatible = "allwinner,sun50i-a64-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};
Commit	Line	Data
d96ebc46 SS	1	/*
	2	* Copyright (C) 2016 ARM Ltd.
	3	* based on the Allwinner H3 dtsi:
c1fd2441	4	* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
d96ebc46 SS	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
f98852bf	45	#include <dt-bindings/clock/sun50i-a64-ccu.h>
d96ebc46	46	#include <dt-bindings/interrupt-controller/arm-gic.h>
f98852bf	47	#include <dt-bindings/reset/sun50i-a64-ccu.h>
d96ebc46 SS	48
d96ebc46 SS	49	/ {
d96ebc46 SS	50	interrupt-parent = <&gic>;
	51	#address-cells = <1>;
	52	#size-cells = <1>;
	53
d96ebc46 SS	54	cpus {
	55	#address-cells = <1>;
	56	#size-cells = <0>;
	57
f98852bf	58	cpu0: cpu@0 {
d96ebc46 SS	59	compatible = "arm,cortex-a53", "arm,armv8";
	60	device_type = "cpu";
	61	reg = <0>;
	62	enable-method = "psci";
	63	};
	64
f98852bf	65	cpu1: cpu@1 {
d96ebc46 SS	66	compatible = "arm,cortex-a53", "arm,armv8";
	67	device_type = "cpu";
	68	reg = <1>;
	69	enable-method = "psci";
	70	};
	71
f98852bf	72	cpu2: cpu@2 {
d96ebc46 SS	73	compatible = "arm,cortex-a53", "arm,armv8";
	74	device_type = "cpu";
	75	reg = <2>;
	76	enable-method = "psci";
	77	};
	78
f98852bf	79	cpu3: cpu@3 {
d96ebc46 SS	80	compatible = "arm,cortex-a53", "arm,armv8";
	81	device_type = "cpu";
	82	reg = <3>;
	83	enable-method = "psci";
	84	};
	85	};
	86
f98852bf AP	87	osc24M: osc24M_clk {
	88	#clock-cells = <0>;
	89	compatible = "fixed-clock";
	90	clock-frequency = <24000000>;
	91	clock-output-names = "osc24M";
	92	};
	93
	94	osc32k: osc32k_clk {
	95	#clock-cells = <0>;
	96	compatible = "fixed-clock";
	97	clock-frequency = <32768>;
	98	clock-output-names = "osc32k";
d96ebc46 SS	99	};
d96ebc46 SS	100
f98852bf AP	101	iosc: internal-osc-clk {
	102	#clock-cells = <0>;
	103	compatible = "fixed-clock";
	104	clock-frequency = <16000000>;
	105	clock-accuracy = <300000000>;
	106	clock-output-names = "iosc";
d96ebc46 SS	107	};
d96ebc46 SS	108
f98852bf AP	109	psci {
	110	compatible = "arm,psci-0.2";
	111	method = "smc";
c1fd2441 AP	112	};
c1fd2441 AP	113
d96ebc46 SS	114	timer {
	115	compatible = "arm,armv8-timer";
	116	interrupts = <GIC_PPI 13
	117	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	118	<GIC_PPI 14
	119	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	120	<GIC_PPI 11
	121	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	122	<GIC_PPI 10
	123	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	124	};
	125
d96ebc46 SS	126	soc {
	127	compatible = "simple-bus";
	128	#address-cells = <1>;
	129	#size-cells = <1>;
	130	ranges;
	131
c1fd2441	132	mmc0: mmc@1c0f000 {
f98852bf	133	compatible = "allwinner,sun50i-a64-mmc";
d96ebc46	134	reg = <0x01c0f000 0x1000>;
f98852bf AP	135	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
	136	clock-names = "ahb", "mmc";
	137	resets = <&ccu RST_BUS_MMC0>;
d96ebc46 SS	138	reset-names = "ahb";
d96ebc46 SS	139	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
f98852bf	140	max-frequency = <150000000>;
d96ebc46 SS	141	status = "disabled";
	142	#address-cells = <1>;
	143	#size-cells = <0>;
	144	};
	145
c1fd2441	146	mmc1: mmc@1c10000 {
f98852bf	147	compatible = "allwinner,sun50i-a64-mmc";
d96ebc46	148	reg = <0x01c10000 0x1000>;
f98852bf AP	149	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
	150	clock-names = "ahb", "mmc";
	151	resets = <&ccu RST_BUS_MMC1>;
d96ebc46 SS	152	reset-names = "ahb";
d96ebc46 SS	153	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
f98852bf	154	max-frequency = <150000000>;
d96ebc46 SS	155	status = "disabled";
	156	#address-cells = <1>;
	157	#size-cells = <0>;
	158	};
	159
c1fd2441	160	mmc2: mmc@1c11000 {
f98852bf	161	compatible = "allwinner,sun50i-a64-emmc";
d96ebc46	162	reg = <0x01c11000 0x1000>;
f98852bf AP	163	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
	164	clock-names = "ahb", "mmc";
	165	resets = <&ccu RST_BUS_MMC2>;
d96ebc46 SS	166	reset-names = "ahb";
d96ebc46 SS	167	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
f98852bf	168	max-frequency = <200000000>;
d96ebc46 SS	169	status = "disabled";
	170	#address-cells = <1>;
	171	#size-cells = <0>;
	172	};
	173
f98852bf AP	174	usb_otg: usb@01c19000 {
	175	compatible = "allwinner,sun8i-a33-musb";
	176	reg = <0x01c19000 0x0400>;
	177	clocks = <&ccu CLK_BUS_OTG>;
	178	resets = <&ccu RST_BUS_OTG>;
	179	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	180	interrupt-names = "mc";
	181	phys = <&usbphy 0>;
	182	phy-names = "usb";
	183	extcon = <&usbphy 0>;
	184	status = "disabled";
	185	};
	186
	187	usbphy: phy@01c19400 {
	188	compatible = "allwinner,sun50i-a64-usb-phy";
	189	reg = <0x01c19400 0x14>,
	190	<0x01c1a800 0x4>,
	191	<0x01c1b800 0x4>;
	192	reg-names = "phy_ctrl",
	193	"pmu0",
	194	"pmu1";
	195	clocks = <&ccu CLK_USB_PHY0>,
	196	<&ccu CLK_USB_PHY1>;
	197	clock-names = "usb0_phy",
	198	"usb1_phy";
	199	resets = <&ccu RST_USB_PHY0>,
	200	<&ccu RST_USB_PHY1>;
	201	reset-names = "usb0_reset",
	202	"usb1_reset";
	203	status = "disabled";
	204	#phy-cells = <1>;
	205	};
	206
7e4bef71 JT	207	ehci0: usb@01c1a000 {
	208	compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
	209	reg = <0x01c1a000 0x100>;
	210	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	211	clocks = <&ccu CLK_BUS_OHCI0>,
	212	<&ccu CLK_BUS_EHCI0>,
	213	<&ccu CLK_USB_OHCI0>;
	214	resets = <&ccu RST_BUS_OHCI0>,
	215	<&ccu RST_BUS_EHCI0>;
	216	status = "disabled";
	217	};
	218
	219	ohci0: usb@01c1a400 {
	220	compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
	221	reg = <0x01c1a400 0x100>;
	222	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	223	clocks = <&ccu CLK_BUS_OHCI0>,
	224	<&ccu CLK_USB_OHCI0>;
	225	resets = <&ccu RST_BUS_OHCI0>;
	226	status = "disabled";
	227	};
	228
f98852bf AP	229	ehci1: usb@01c1b000 {
	230	compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
	231	reg = <0x01c1b000 0x100>;
	232	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	233	clocks = <&ccu CLK_BUS_OHCI1>,
	234	<&ccu CLK_BUS_EHCI1>,
	235	<&ccu CLK_USB_OHCI1>;
	236	resets = <&ccu RST_BUS_OHCI1>,
	237	<&ccu RST_BUS_EHCI1>;
	238	phys = <&usbphy 1>;
	239	phy-names = "usb";
	240	status = "disabled";
	241	};
	242
	243	ohci1: usb@01c1b400 {
	244	compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
	245	reg = <0x01c1b400 0x100>;
	246	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	247	clocks = <&ccu CLK_BUS_OHCI1>,
	248	<&ccu CLK_USB_OHCI1>;
	249	resets = <&ccu RST_BUS_OHCI1>;
	250	phys = <&usbphy 1>;
	251	phy-names = "usb";
	252	status = "disabled";
	253	};
	254
	255	ccu: clock@01c20000 {
	256	compatible = "allwinner,sun50i-a64-ccu";
	257	reg = <0x01c20000 0x400>;
	258	clocks = <&osc24M>, <&osc32k>;
	259	clock-names = "hosc", "losc";
	260	#clock-cells = <1>;
	261	#reset-cells = <1>;
	262	};
	263
c1fd2441 AP	264	pio: pinctrl@1c20800 {
c1fd2441 AP	265	compatible = "allwinner,sun50i-a64-pinctrl";
d96ebc46 SS	266	reg = <0x01c20800 0x400>;
	267	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	268	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	269	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
f98852bf	270	clocks = <&ccu 58>;
d96ebc46 SS	271	gpio-controller;
	272	#gpio-cells = <3>;
	273	interrupt-controller;
f98852bf	274	#interrupt-cells = <3>;
c1fd2441	275
f98852bf AP	276	i2c1_pins: i2c1_pins {
	277	pins = "PH2", "PH3";
	278	function = "i2c1";
d96ebc46 SS	279	};
d96ebc46 SS	280
f98852bf AP	281	mmc0_pins: mmc0-pins {
	282	pins = "PF0", "PF1", "PF2", "PF3",
	283	"PF4", "PF5";
	284	function = "mmc0";
	285	drive-strength = <30>;
	286	bias-pull-up;
d96ebc46	287	};
c1fd2441	288
f98852bf AP	289	mmc1_pins: mmc1-pins {
	290	pins = "PG0", "PG1", "PG2", "PG3",
	291	"PG4", "PG5";
	292	function = "mmc1";
	293	drive-strength = <30>;
	294	bias-pull-up;
c1fd2441 AP	295	};
c1fd2441 AP	296
f98852bf AP	297	mmc2_pins: mmc2-pins {
	298	pins = "PC1", "PC5", "PC6", "PC8", "PC9",
	299	"PC10","PC11", "PC12", "PC13",
	300	"PC14", "PC15", "PC16";
	301	function = "mmc2";
	302	drive-strength = <30>;
	303	bias-pull-up;
c1fd2441 AP	304	};
c1fd2441 AP	305
f98852bf AP	306	uart0_pins_a: uart0@0 {
	307	pins = "PB8", "PB9";
	308	function = "uart0";
c1fd2441	309	};
a29710c5	310
f98852bf AP	311	uart1_pins: uart1_pins {
	312	pins = "PG6", "PG7";
	313	function = "uart1";
a29710c5 AST	314	};
a29710c5 AST	315
f98852bf AP	316	uart1_rts_cts_pins: uart1_rts_cts_pins {
	317	pins = "PG8", "PG9";
	318	function = "uart1";
a29710c5	319	};
d96ebc46 SS	320	};
d96ebc46 SS	321
c1fd2441	322	uart0: serial@1c28000 {
d96ebc46 SS	323	compatible = "snps,dw-apb-uart";
	324	reg = <0x01c28000 0x400>;
	325	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	326	reg-shift = <2>;
	327	reg-io-width = <4>;
f98852bf AP	328	clocks = <&ccu 67>;
f98852bf AP	329	resets = <&ccu 46>;
d96ebc46 SS	330	status = "disabled";
	331	};
	332
c1fd2441	333	uart1: serial@1c28400 {
d96ebc46 SS	334	compatible = "snps,dw-apb-uart";
	335	reg = <0x01c28400 0x400>;
	336	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	337	reg-shift = <2>;
	338	reg-io-width = <4>;
f98852bf AP	339	clocks = <&ccu 68>;
f98852bf AP	340	resets = <&ccu 47>;
d96ebc46 SS	341	status = "disabled";
	342	};
	343
c1fd2441	344	uart2: serial@1c28800 {
d96ebc46 SS	345	compatible = "snps,dw-apb-uart";
	346	reg = <0x01c28800 0x400>;
	347	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	348	reg-shift = <2>;
	349	reg-io-width = <4>;
f98852bf AP	350	clocks = <&ccu 69>;
f98852bf AP	351	resets = <&ccu 48>;
d96ebc46 SS	352	status = "disabled";
	353	};
	354
c1fd2441	355	uart3: serial@1c28c00 {
d96ebc46 SS	356	compatible = "snps,dw-apb-uart";
	357	reg = <0x01c28c00 0x400>;
	358	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	359	reg-shift = <2>;
	360	reg-io-width = <4>;
f98852bf AP	361	clocks = <&ccu 70>;
f98852bf AP	362	resets = <&ccu 49>;
d96ebc46 SS	363	status = "disabled";
	364	};
	365
c1fd2441	366	uart4: serial@1c29000 {
d96ebc46 SS	367	compatible = "snps,dw-apb-uart";
	368	reg = <0x01c29000 0x400>;
	369	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	370	reg-shift = <2>;
	371	reg-io-width = <4>;
f98852bf AP	372	clocks = <&ccu 71>;
f98852bf AP	373	resets = <&ccu 50>;
d96ebc46 SS	374	status = "disabled";
	375	};
	376
c1fd2441 AP	377	i2c0: i2c@1c2ac00 {
	378	compatible = "allwinner,sun6i-a31-i2c";
	379	reg = <0x01c2ac00 0x400>;
	380	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
f98852bf AP	381	clocks = <&ccu 63>;
f98852bf AP	382	resets = <&ccu 42>;
c1fd2441 AP	383	status = "disabled";
	384	#address-cells = <1>;
	385	#size-cells = <0>;
	386	};
d96ebc46	387
c1fd2441 AP	388	i2c1: i2c@1c2b000 {
	389	compatible = "allwinner,sun6i-a31-i2c";
	390	reg = <0x01c2b000 0x400>;
	391	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
f98852bf AP	392	clocks = <&ccu 64>;
f98852bf AP	393	resets = <&ccu 43>;
c1fd2441 AP	394	status = "disabled";
	395	#address-cells = <1>;
	396	#size-cells = <0>;
	397	};
	398
	399	i2c2: i2c@1c2b400 {
	400	compatible = "allwinner,sun6i-a31-i2c";
	401	reg = <0x01c2b400 0x400>;
	402	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
f98852bf AP	403	clocks = <&ccu 65>;
f98852bf AP	404	resets = <&ccu 44>;
c1fd2441 AP	405	status = "disabled";
	406	#address-cells = <1>;
	407	#size-cells = <0>;
	408	};
a29710c5	409
f98852bf AP	410	gic: interrupt-controller@1c81000 {
	411	compatible = "arm,gic-400";
	412	reg = <0x01c81000 0x1000>,
	413	<0x01c82000 0x2000>,
	414	<0x01c84000 0x2000>,
	415	<0x01c86000 0x2000>;
	416	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	417	interrupt-controller;
	418	#interrupt-cells = <3>;
a29710c5	419	};
9d6c9d98	420
f98852bf AP	421	rtc: rtc@1f00000 {
	422	compatible = "allwinner,sun6i-a31-rtc";
	423	reg = <0x01f00000 0x54>;
	424	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	425	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
9d6c9d98 AST	426	};
9d6c9d98 AST	427
f98852bf AP	428	r_ccu: clock@1f01400 {
	429	compatible = "allwinner,sun50i-a64-r-ccu";
	430	reg = <0x01f01400 0x100>;
	431	clocks = <&osc24M>, <&osc32k>, <&iosc>;
	432	clock-names = "hosc", "losc", "iosc";
	433	#clock-cells = <1>;
	434	#reset-cells = <1>;
9d6c9d98 AST	435	};
9d6c9d98 AST	436
f98852bf AP	437	r_pio: pinctrl@01f02c00 {
	438	compatible = "allwinner,sun50i-a64-r-pinctrl";
	439	reg = <0x01f02c00 0x400>;
	440	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	441	clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
	442	clock-names = "apb", "hosc", "losc";
	443	gpio-controller;
	444	#gpio-cells = <3>;
	445	interrupt-controller;
	446	#interrupt-cells = <3>;
9d6c9d98	447	};
d96ebc46 SS	448	};
d96ebc46 SS	449	};