[people/ms/u-boot.git] / arch / arm / dts / uniphier-ld11.dtsi

/*
 * Device Tree Source for UniPhier LD11 SoC
 *
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/memreserve/ 0x80000000 0x02000000;

/ {
	compatible = "socionext,uniphier-ld11";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x000>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x001>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};
	};

	cluster0_opp: opp_table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-245000000 {
			opp-hz = /bits/ 64 <245000000>;
			clock-latency-ns = <300>;
		};
		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-490000000 {
			opp-hz = /bits/ 64 <490000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-653334000 {
			opp-hz = /bits/ 64 <653334000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-980000000 {
			opp-hz = /bits/ 64 <980000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>,
			     <1 14 4>,
			     <1 11 4>,
			     <1 10 4>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			clock-frequency = <58820000>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			clock-frequency = <58820000>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			clock-frequency = <58820000>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			clock-frequency = <58820000>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 43 0 0>,
				      <&pinctrl 51 0 0>,
				      <&pinctrl 96 0 0>,
				      <&pinctrl 160 0 0>,
				      <&pinctrl 184 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1",
						  "gpio_range2",
						  "gpio_range3",
						  "gpio_range4",
						  "gpio_range5";
			ngpios = <200>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
						     <21 217 3>;
		};

		adamv@57920000 {
			compatible = "socionext,uniphier-ld11-adamv",
				     "simple-mfd", "syscon";
			reg = <0x57920000 0x1000>;

			adamv_rst: reset {
				compatible = "socionext,uniphier-ld11-adamv-reset";
				#reset-cells = <1>;
			};
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			clocks = <&peri_clk 6>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			clock-frequency = <100000>;
		};

		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4>;
			clocks = <&peri_clk 8>;
			clock-frequency = <100000>;
		};

		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-ld11-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_rst: reset {
				compatible = "socionext,uniphier-ld11-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-ld11-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-ld11-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-ld11-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a000000 {
			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
			reg = <0x5a000000 0x400>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc_1v8>;
			clocks = <&sys_clk 4>;
			bus-width = <8>;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			cdns,phy-input-delay-legacy = <4>;
			cdns,phy-input-delay-mmc-highspeed = <2>;
			cdns,phy-input-delay-mmc-ddr = <3>;
			cdns,phy-dll-delay-sdclk = <21>;
			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <0 243 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
				 <&mio_rst 12>;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <0 244 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
				 <&mio_rst 13>;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <0 245 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
				 <&mio_rst 14>;
		};

		mioctrl@5b3e0000 {
			compatible = "socionext,uniphier-ld11-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x5b3e0000 0x800>;

			mio_clk: clock {
				compatible = "socionext,uniphier-ld11-mio-clock";
				#clock-cells = <1>;
			};

			mio_rst: reset {
				compatible = "socionext,uniphier-ld11-mio-reset";
				#reset-cells = <1>;
				resets = <&sys_rst 7>;
			};
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-ld11-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-ld11-pinctrl";
			};
		};

		aidet: aidet@5fc20000 {
			compatible = "socionext,uniphier-ld11-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gic: interrupt-controller@5fe00000 {
			compatible = "arm,gic-v3";
			reg = <0x5fe00000 0x10000>,	/* GICD */
			      <0x5fe40000 0x80000>;	/* GICR */
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 4>;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-ld11-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-ld11-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-ld11-reset";
				#reset-cells = <1>;
			};

			watchdog {
				compatible = "socionext,uniphier-wdt";
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clocks = <&sys_clk 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"
Commit	Line	Data
fc26b7b9	1	/*
52159d27	2	* Device Tree Source for UniPhier LD11 SoC
fc26b7b9	3	*
c4adc50e MY	4	* Copyright (C) 2016 Socionext Inc.
c4adc50e MY	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
fc26b7b9	6	*
d9403001	7	* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
fc26b7b9 MY	8	*/
fc26b7b9 MY	9
d9403001	10	/memreserve/ 0x80000000 0x02000000;
c4adc50e	11
fc26b7b9	12	/ {
52159d27	13	compatible = "socionext,uniphier-ld11";
fc26b7b9 MY	14	#address-cells = <2>;
	15	#size-cells = <2>;
	16	interrupt-parent = <&gic>;
	17
	18	cpus {
	19	#address-cells = <2>;
	20	#size-cells = <0>;
	21
c4adc50e MY	22	cpu-map {
	23	cluster0 {
	24	core0 {
	25	cpu = <&cpu0>;
	26	};
	27	core1 {
	28	cpu = <&cpu1>;
	29	};
	30	};
	31	};
	32
	33	cpu0: cpu@0 {
fc26b7b9 MY	34	device_type = "cpu";
	35	compatible = "arm,cortex-a53", "arm,armv8";
	36	reg = <0 0x000>;
cd62214d MY	37	clocks = <&sys_clk 33>;
	38	enable-method = "psci";
	39	operating-points-v2 = <&cluster0_opp>;
fc26b7b9 MY	40	};
fc26b7b9 MY	41
c4adc50e	42	cpu1: cpu@1 {
fc26b7b9 MY	43	device_type = "cpu";
	44	compatible = "arm,cortex-a53", "arm,armv8";
	45	reg = <0 0x001>;
cd62214d MY	46	clocks = <&sys_clk 33>;
	47	enable-method = "psci";
	48	operating-points-v2 = <&cluster0_opp>;
fc26b7b9 MY	49	};
	50	};
	51
cd62214d MY	52	cluster0_opp: opp_table {
	53	compatible = "operating-points-v2";
	54	opp-shared;
	55
4e7f8de4	56	opp-245000000 {
cd62214d MY	57	opp-hz = /bits/ 64 <245000000>;
	58	clock-latency-ns = <300>;
	59	};
4e7f8de4	60	opp-250000000 {
cd62214d MY	61	opp-hz = /bits/ 64 <250000000>;
	62	clock-latency-ns = <300>;
	63	};
4e7f8de4	64	opp-490000000 {
cd62214d MY	65	opp-hz = /bits/ 64 <490000000>;
	66	clock-latency-ns = <300>;
	67	};
4e7f8de4	68	opp-500000000 {
cd62214d MY	69	opp-hz = /bits/ 64 <500000000>;
	70	clock-latency-ns = <300>;
	71	};
4e7f8de4	72	opp-653334000 {
cd62214d MY	73	opp-hz = /bits/ 64 <653334000>;
	74	clock-latency-ns = <300>;
	75	};
4e7f8de4	76	opp-666667000 {
cd62214d MY	77	opp-hz = /bits/ 64 <666667000>;
	78	clock-latency-ns = <300>;
	79	};
4e7f8de4	80	opp-980000000 {
cd62214d MY	81	opp-hz = /bits/ 64 <980000000>;
	82	clock-latency-ns = <300>;
	83	};
	84	};
	85
	86	psci {
	87	compatible = "arm,psci-1.0";
	88	method = "smc";
	89	};
	90
fc26b7b9	91	clocks {
c4adc50e MY	92	refclk: ref {
	93	compatible = "fixed-clock";
	94	#clock-cells = <0>;
	95	clock-frequency = <25000000>;
	96	};
fc26b7b9 MY	97	};
	98
	99	timer {
	100	compatible = "arm,armv8-timer";
35343a26 MY	101	interrupts = <1 13 4>,
	102	<1 14 4>,
	103	<1 11 4>,
	104	<1 10 4>;
fc26b7b9 MY	105	};
fc26b7b9 MY	106
7ad79c12	107	soc@0 {
fc26b7b9 MY	108	compatible = "simple-bus";
	109	#address-cells = <1>;
	110	#size-cells = <1>;
	111	ranges = <0 0 0 0xffffffff>;
	112
	113	serial0: serial@54006800 {
	114	compatible = "socionext,uniphier-uart";
	115	status = "disabled";
	116	reg = <0x54006800 0x40>;
	117	interrupts = <0 33 4>;
	118	pinctrl-names = "default";
	119	pinctrl-0 = <&pinctrl_uart0>;
35343a26	120	clocks = <&peri_clk 0>;
f1494981	121	clock-frequency = <58820000>;
fc26b7b9 MY	122	};
	123
	124	serial1: serial@54006900 {
	125	compatible = "socionext,uniphier-uart";
	126	status = "disabled";
	127	reg = <0x54006900 0x40>;
	128	interrupts = <0 35 4>;
	129	pinctrl-names = "default";
	130	pinctrl-0 = <&pinctrl_uart1>;
35343a26	131	clocks = <&peri_clk 1>;
f1494981	132	clock-frequency = <58820000>;
fc26b7b9 MY	133	};
	134
	135	serial2: serial@54006a00 {
	136	compatible = "socionext,uniphier-uart";
	137	status = "disabled";
	138	reg = <0x54006a00 0x40>;
	139	interrupts = <0 37 4>;
	140	pinctrl-names = "default";
	141	pinctrl-0 = <&pinctrl_uart2>;
35343a26	142	clocks = <&peri_clk 2>;
f1494981	143	clock-frequency = <58820000>;
fc26b7b9 MY	144	};
	145
	146	serial3: serial@54006b00 {
	147	compatible = "socionext,uniphier-uart";
	148	status = "disabled";
	149	reg = <0x54006b00 0x40>;
	150	interrupts = <0 177 4>;
	151	pinctrl-names = "default";
	152	pinctrl-0 = <&pinctrl_uart3>;
35343a26	153	clocks = <&peri_clk 3>;
f1494981	154	clock-frequency = <58820000>;
fc26b7b9 MY	155	};
fc26b7b9 MY	156
0f72b74b MY	157	gpio: gpio@55000000 {
	158	compatible = "socionext,uniphier-gpio";
	159	reg = <0x55000000 0x200>;
	160	interrupt-parent = <&aidet>;
	161	interrupt-controller;
	162	#interrupt-cells = <2>;
	163	gpio-controller;
	164	#gpio-cells = <2>;
	165	gpio-ranges = <&pinctrl 0 0 0>,
	166	<&pinctrl 43 0 0>,
	167	<&pinctrl 51 0 0>,
	168	<&pinctrl 96 0 0>,
	169	<&pinctrl 160 0 0>,
	170	<&pinctrl 184 0 0>;
	171	gpio-ranges-group-names = "gpio_range0",
	172	"gpio_range1",
	173	"gpio_range2",
	174	"gpio_range3",
	175	"gpio_range4",
	176	"gpio_range5";
	177	ngpios = <200>;
27287487 MY	178	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
	179	<21 217 3>;
	180	};
	181
	182	adamv@57920000 {
	183	compatible = "socionext,uniphier-ld11-adamv",
	184	"simple-mfd", "syscon";
	185	reg = <0x57920000 0x1000>;
	186
	187	adamv_rst: reset {
	188	compatible = "socionext,uniphier-ld11-adamv-reset";
	189	#reset-cells = <1>;
	190	};
0f72b74b MY	191	};
0f72b74b MY	192
fc26b7b9 MY	193	i2c0: i2c@58780000 {
	194	compatible = "socionext,uniphier-fi2c";
	195	status = "disabled";
	196	reg = <0x58780000 0x80>;
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	interrupts = <0 41 4>;
	200	pinctrl-names = "default";
	201	pinctrl-0 = <&pinctrl_i2c0>;
cd62214d	202	clocks = <&peri_clk 4>;
fc26b7b9 MY	203	clock-frequency = <100000>;
	204	};
	205
	206	i2c1: i2c@58781000 {
	207	compatible = "socionext,uniphier-fi2c";
	208	status = "disabled";
	209	reg = <0x58781000 0x80>;
	210	#address-cells = <1>;
	211	#size-cells = <0>;
	212	interrupts = <0 42 4>;
	213	pinctrl-names = "default";
	214	pinctrl-0 = <&pinctrl_i2c1>;
cd62214d	215	clocks = <&peri_clk 5>;
fc26b7b9 MY	216	clock-frequency = <100000>;
	217	};
	218
	219	i2c2: i2c@58782000 {
	220	compatible = "socionext,uniphier-fi2c";
	221	reg = <0x58782000 0x80>;
	222	#address-cells = <1>;
	223	#size-cells = <0>;
	224	interrupts = <0 43 4>;
cd62214d	225	clocks = <&peri_clk 6>;
fc26b7b9 MY	226	clock-frequency = <400000>;
	227	};
	228
	229	i2c3: i2c@58783000 {
	230	compatible = "socionext,uniphier-fi2c";
	231	status = "disabled";
	232	reg = <0x58783000 0x80>;
	233	#address-cells = <1>;
	234	#size-cells = <0>;
	235	interrupts = <0 44 4>;
	236	pinctrl-names = "default";
	237	pinctrl-0 = <&pinctrl_i2c3>;
cd62214d	238	clocks = <&peri_clk 7>;
fc26b7b9 MY	239	clock-frequency = <100000>;
	240	};
	241
	242	i2c4: i2c@58784000 {
	243	compatible = "socionext,uniphier-fi2c";
	244	status = "disabled";
	245	reg = <0x58784000 0x80>;
	246	#address-cells = <1>;
	247	#size-cells = <0>;
	248	interrupts = <0 45 4>;
	249	pinctrl-names = "default";
	250	pinctrl-0 = <&pinctrl_i2c4>;
cd62214d	251	clocks = <&peri_clk 8>;
fc26b7b9 MY	252	clock-frequency = <100000>;
	253	};
	254
	255	i2c5: i2c@58785000 {
	256	compatible = "socionext,uniphier-fi2c";
	257	reg = <0x58785000 0x80>;
	258	#address-cells = <1>;
	259	#size-cells = <0>;
	260	interrupts = <0 25 4>;
cd62214d	261	clocks = <&peri_clk 9>;
fc26b7b9 MY	262	clock-frequency = <400000>;
	263	};
	264
	265	system_bus: system-bus@58c00000 {
	266	compatible = "socionext,uniphier-system-bus";
	267	status = "disabled";
	268	reg = <0x58c00000 0x400>;
	269	#address-cells = <2>;
	270	#size-cells = <1>;
c4adc50e MY	271	pinctrl-names = "default";
c4adc50e MY	272	pinctrl-0 = <&pinctrl_system_bus>;
fc26b7b9 MY	273	};
fc26b7b9 MY	274
abb6ac25	275	smpctrl@59801000 {
fc26b7b9 MY	276	compatible = "socionext,uniphier-smpctrl";
	277	reg = <0x59801000 0x400>;
	278	};
	279
cd62214d MY	280	sdctrl@59810000 {
	281	compatible = "socionext,uniphier-ld11-sdctrl",
	282	"simple-mfd", "syscon";
	283	reg = <0x59810000 0x400>;
	284
	285	sd_rst: reset {
	286	compatible = "socionext,uniphier-ld11-sd-reset";
	287	#reset-cells = <1>;
	288	};
	289	};
	290
35343a26	291	perictrl@59820000 {
cd62214d	292	compatible = "socionext,uniphier-ld11-perictrl",
35343a26 MY	293	"simple-mfd", "syscon";
	294	reg = <0x59820000 0x200>;
	295
	296	peri_clk: clock {
	297	compatible = "socionext,uniphier-ld11-peri-clock";
	298	#clock-cells = <1>;
	299	};
	300
	301	peri_rst: reset {
	302	compatible = "socionext,uniphier-ld11-peri-reset";
	303	#reset-cells = <1>;
	304	};
	305	};
	306
cd62214d	307	emmc: sdhc@5a000000 {
7a6139c9	308	compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
cd62214d MY	309	reg = <0x5a000000 0x400>;
	310	interrupts = <0 78 4>;
	311	pinctrl-names = "default";
	312	pinctrl-0 = <&pinctrl_emmc_1v8>;
	313	clocks = <&sys_clk 4>;
	314	bus-width = <8>;
	315	mmc-ddr-1_8v;
	316	mmc-hs200-1_8v;
4e7f8de4 MY	317	cdns,phy-input-delay-legacy = <4>;
	318	cdns,phy-input-delay-mmc-highspeed = <2>;
	319	cdns,phy-input-delay-mmc-ddr = <3>;
	320	cdns,phy-dll-delay-sdclk = <21>;
	321	cdns,phy-dll-delay-sdclk-hsmmc = <21>;
cd62214d MY	322	};
cd62214d MY	323
d7e103c0 MY	324	usb0: usb@5a800100 {
	325	compatible = "socionext,uniphier-ehci", "generic-ehci";
	326	status = "disabled";
	327	reg = <0x5a800100 0x100>;
	328	interrupts = <0 243 4>;
	329	pinctrl-names = "default";
	330	pinctrl-0 = <&pinctrl_usb0>;
52159d27 MY	331	clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
	332	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
	333	<&mio_rst 12>;
d7e103c0 MY	334	};
	335
	336	usb1: usb@5a810100 {
	337	compatible = "socionext,uniphier-ehci", "generic-ehci";
	338	status = "disabled";
	339	reg = <0x5a810100 0x100>;
	340	interrupts = <0 244 4>;
	341	pinctrl-names = "default";
	342	pinctrl-0 = <&pinctrl_usb1>;
52159d27 MY	343	clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
	344	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
	345	<&mio_rst 13>;
d7e103c0 MY	346	};
	347
	348	usb2: usb@5a820100 {
	349	compatible = "socionext,uniphier-ehci", "generic-ehci";
	350	status = "disabled";
	351	reg = <0x5a820100 0x100>;
	352	interrupts = <0 245 4>;
	353	pinctrl-names = "default";
	354	pinctrl-0 = <&pinctrl_usb2>;
52159d27 MY	355	clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
	356	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
	357	<&mio_rst 14>;
d7e103c0 MY	358	};
d7e103c0 MY	359
35343a26	360	mioctrl@5b3e0000 {
7317a940	361	compatible = "socionext,uniphier-ld11-mioctrl",
35343a26	362	"simple-mfd", "syscon";
d7e103c0	363	reg = <0x5b3e0000 0x800>;
35343a26 MY	364
	365	mio_clk: clock {
	366	compatible = "socionext,uniphier-ld11-mio-clock";
	367	#clock-cells = <1>;
	368	};
	369
	370	mio_rst: reset {
	371	compatible = "socionext,uniphier-ld11-mio-reset";
	372	#reset-cells = <1>;
	373	resets = <&sys_rst 7>;
	374	};
d7e103c0 MY	375	};
d7e103c0 MY	376
c4adc50e	377	soc-glue@5f800000 {
cd62214d	378	compatible = "socionext,uniphier-ld11-soc-glue",
35343a26	379	"simple-mfd", "syscon";
c4adc50e	380	reg = <0x5f800000 0x2000>;
c4adc50e MY	381
	382	pinctrl: pinctrl {
	383	compatible = "socionext,uniphier-ld11-pinctrl";
c4adc50e	384	};
fc26b7b9 MY	385	};
fc26b7b9 MY	386
6c9e46ef MY	387	aidet: aidet@5fc20000 {
6c9e46ef MY	388	compatible = "socionext,uniphier-ld11-aidet";
1013aef3	389	reg = <0x5fc20000 0x200>;
6c9e46ef MY	390	interrupt-controller;
6c9e46ef MY	391	#interrupt-cells = <2>;
1013aef3 MY	392	};
1013aef3 MY	393
fc26b7b9 MY	394	gic: interrupt-controller@5fe00000 {
	395	compatible = "arm,gic-v3";
	396	reg = <0x5fe00000 0x10000>, /* GICD */
	397	<0x5fe40000 0x80000>; /* GICR */
	398	interrupt-controller;
	399	#interrupt-cells = <3>;
	400	interrupts = <1 9 4>;
	401	};
35343a26 MY	402
	403	sysctrl@61840000 {
	404	compatible = "socionext,uniphier-ld11-sysctrl",
	405	"simple-mfd", "syscon";
cd62214d	406	reg = <0x61840000 0x10000>;
35343a26 MY	407
	408	sys_clk: clock {
	409	compatible = "socionext,uniphier-ld11-clock";
	410	#clock-cells = <1>;
	411	};
	412
	413	sys_rst: reset {
	414	compatible = "socionext,uniphier-ld11-reset";
	415	#reset-cells = <1>;
	416	};
6c9e46ef MY	417
	418	watchdog {
	419	compatible = "socionext,uniphier-wdt";
	420	};
35343a26	421	};
cd62214d MY	422
cd62214d MY	423	nand: nand@68000000 {
4e7f8de4	424	compatible = "socionext,uniphier-denali-nand-v5b";
cd62214d MY	425	status = "disabled";
	426	reg-names = "nand_data", "denali_reg";
	427	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	428	interrupts = <0 65 4>;
	429	pinctrl-names = "default";
	430	pinctrl-0 = <&pinctrl_nand>;
	431	clocks = <&sys_clk 2>;
cd62214d	432	};
fc26b7b9 MY	433	};
	434	};
	435
6c9e46ef	436	#include "uniphier-pinctrl.dtsi"