[people/ms/u-boot.git] / arch / arm / dts / uniphier-pxs2.dtsi

/*
 * Device Tree Source for UniPhier PXs2 SoC
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/ {
	compatible = "socionext,uniphier-pxs2";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};
	};

	cpu_opp: opp_table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			clock-latency-ns = <300>;
		};
		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			clock-latency-ns = <300>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <300>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			clock-latency-ns = <300>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			clock-latency-ns = <300>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <300>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <300>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;
		u-boot,dm-pre-reloc;

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
			cache-unified;
			cache-size = <(1280 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			clock-frequency = <88900000>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			clock-frequency = <88900000>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			clock-frequency = <88900000>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			clock-frequency = <88900000>;
		};

		port0x: gpio@55000008 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000008 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port1x: gpio@55000010 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000010 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port2x: gpio@55000018 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000018 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port3x: gpio@55000020 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000020 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port4: gpio@55000028 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000028 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port5x: gpio@55000030 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000030 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port6x: gpio@55000038 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000038 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port7x: gpio@55000040 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000040 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port8x: gpio@55000048 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000048 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port9x: gpio@55000050 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000050 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port10x: gpio@55000058 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000058 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port12x: gpio@55000068 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000068 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port13x: gpio@55000070 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000070 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port14x: gpio@55000078 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000078 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port15x: gpio@55000080 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000080 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port16x: gpio@55000088 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000088 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port17x: gpio@550000a0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000a0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port18x: gpio@550000a8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000a8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port19x: gpio@550000b0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000b0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port20x: gpio@550000b8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000b8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port21x: gpio@550000c0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000c0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port22x: gpio@550000c8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000c8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port23x: gpio@550000d0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000d0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port24x: gpio@550000d8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000d8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port25x: gpio@550000e0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000e0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port26x: gpio@550000e8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000e8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port27x: gpio@550000f0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000f0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port28x: gpio@550000f8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000f8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			clocks = <&peri_clk 8>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for STM */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&peri_clk 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pxs2-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;
			u-boot,dm-pre-reloc;

			sd_clk: clock {
				compatible = "socionext,uniphier-pxs2-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pxs2-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pxs2-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pxs2-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pxs2-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a000000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a000000 0x800>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sd_clk 1>;
			reset-names = "host";
			resets = <&sd_rst 1>;
			bus-width = <8>;
			non-removable;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			no-3-3-v;
		};

		sd: sdhc@5a400000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a400000 0x800>;
			interrupts = <0 76 4>;
			pinctrl-names = "default", "1.8v";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_1v8>;
			clocks = <&sd_clk 0>;
			reset-names = "host";
			resets = <&sd_rst 0>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-pxs2-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;
			u-boot,dm-pre-reloc;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pxs2-pinctrl";
				u-boot,dm-pre-reloc;
			};
		};

		aidet: aidet@5fc20000 {
			compatible = "socionext,uniphier-pxs2-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pxs2-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pxs2-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pxs2-reset";
				#reset-cells = <1>;
			};
		};

		usb0: usb@65b00000 {
			compatible = "socionext,uniphier-pxs2-dwc3";
			status = "disabled";
			reg = <0x65b00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
			dwc3@65a00000 {
				compatible = "snps,dwc3";
				reg = <0x65a00000 0x10000>;
				interrupts = <0 134 4>;
				dr_mode = "host";
				tx-fifo-resize;
			};
		};

		usb1: usb@65d00000 {
			compatible = "socionext,uniphier-pxs2-dwc3";
			status = "disabled";
			reg = <0x65d00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
			dwc3@65c00000 {
				compatible = "snps,dwc3";
				reg = <0x65c00000 0x10000>;
				interrupts = <0 137 4>;
				dr_mode = "host";
				tx-fifo-resize;
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand2cs>;
			clocks = <&sys_clk 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"
Commit	Line	Data
f875bbb4	1	/*
52159d27	2	* Device Tree Source for UniPhier PXs2 SoC
f875bbb4	3	*
52159d27 MY	4	* Copyright (C) 2015-2016 Socionext Inc.
52159d27 MY	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
f875bbb4	6	*
d9403001	7	* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
f875bbb4 MY	8	*/
f875bbb4 MY	9
f875bbb4	10	/ {
52159d27	11	compatible = "socionext,uniphier-pxs2";
f16eda96 MY	12	#address-cells = <1>;
f16eda96 MY	13	#size-cells = <1>;
f875bbb4 MY	14
	15	cpus {
	16	#address-cells = <1>;
	17	#size-cells = <0>;
f875bbb4 MY	18
	19	cpu@0 {
	20	device_type = "cpu";
	21	compatible = "arm,cortex-a9";
	22	reg = <0>;
cd62214d	23	clocks = <&sys_clk 32>;
52159d27	24	enable-method = "psci";
4e1f81d4	25	next-level-cache = <&l2>;
cd62214d	26	operating-points-v2 = <&cpu_opp>;
f875bbb4 MY	27	};
	28
	29	cpu@1 {
	30	device_type = "cpu";
	31	compatible = "arm,cortex-a9";
	32	reg = <1>;
cd62214d	33	clocks = <&sys_clk 32>;
52159d27	34	enable-method = "psci";
4e1f81d4	35	next-level-cache = <&l2>;
cd62214d	36	operating-points-v2 = <&cpu_opp>;
f875bbb4 MY	37	};
	38
	39	cpu@2 {
	40	device_type = "cpu";
	41	compatible = "arm,cortex-a9";
	42	reg = <2>;
cd62214d	43	clocks = <&sys_clk 32>;
52159d27	44	enable-method = "psci";
4e1f81d4	45	next-level-cache = <&l2>;
cd62214d	46	operating-points-v2 = <&cpu_opp>;
f875bbb4 MY	47	};
	48
	49	cpu@3 {
	50	device_type = "cpu";
	51	compatible = "arm,cortex-a9";
	52	reg = <3>;
cd62214d	53	clocks = <&sys_clk 32>;
52159d27	54	enable-method = "psci";
4e1f81d4	55	next-level-cache = <&l2>;
cd62214d	56	operating-points-v2 = <&cpu_opp>;
f875bbb4 MY	57	};
	58	};
	59
cd62214d MY	60	cpu_opp: opp_table {
	61	compatible = "operating-points-v2";
	62	opp-shared;
	63
4e7f8de4	64	opp-100000000 {
cd62214d MY	65	opp-hz = /bits/ 64 <100000000>;
	66	clock-latency-ns = <300>;
	67	};
4e7f8de4	68	opp-150000000 {
cd62214d MY	69	opp-hz = /bits/ 64 <150000000>;
	70	clock-latency-ns = <300>;
	71	};
4e7f8de4	72	opp-200000000 {
cd62214d MY	73	opp-hz = /bits/ 64 <200000000>;
	74	clock-latency-ns = <300>;
	75	};
4e7f8de4	76	opp-300000000 {
cd62214d MY	77	opp-hz = /bits/ 64 <300000000>;
	78	clock-latency-ns = <300>;
	79	};
4e7f8de4	80	opp-400000000 {
cd62214d MY	81	opp-hz = /bits/ 64 <400000000>;
	82	clock-latency-ns = <300>;
	83	};
4e7f8de4	84	opp-600000000 {
cd62214d MY	85	opp-hz = /bits/ 64 <600000000>;
	86	clock-latency-ns = <300>;
	87	};
4e7f8de4	88	opp-800000000 {
cd62214d MY	89	opp-hz = /bits/ 64 <800000000>;
	90	clock-latency-ns = <300>;
	91	};
4e7f8de4	92	opp-1200000000 {
cd62214d MY	93	opp-hz = /bits/ 64 <1200000000>;
	94	clock-latency-ns = <300>;
	95	};
	96	};
	97
	98	psci {
	99	compatible = "arm,psci-0.2";
	100	method = "smc";
	101	};
	102
f875bbb4	103	clocks {
cd62214d MY	104	refclk: ref {
	105	compatible = "fixed-clock";
	106	#clock-cells = <0>;
	107	clock-frequency = <25000000>;
	108	};
	109
f875bbb4 MY	110	arm_timer_clk: arm_timer_clk {
	111	#clock-cells = <0>;
	112	compatible = "fixed-clock";
	113	clock-frequency = <50000000>;
	114	};
f875bbb4 MY	115	};
f875bbb4 MY	116
cd62214d MY	117	soc {
	118	compatible = "simple-bus";
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	ranges;
	122	interrupt-parent = <&intc>;
	123	u-boot,dm-pre-reloc;
	124
	125	l2: l2-cache@500c0000 {
	126	compatible = "socionext,uniphier-system-cache";
	127	reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
	128	<0x506c0000 0x400>;
	129	interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
	130	cache-unified;
	131	cache-size = <(1280 * 1024)>;
	132	cache-sets = <512>;
	133	cache-line-size = <128>;
	134	cache-level = <2>;
	135	};
595dc1e1	136
cd62214d MY	137	serial0: serial@54006800 {
	138	compatible = "socionext,uniphier-uart";
	139	status = "disabled";
	140	reg = <0x54006800 0x40>;
	141	interrupts = <0 33 4>;
	142	pinctrl-names = "default";
	143	pinctrl-0 = <&pinctrl_uart0>;
	144	clocks = <&peri_clk 0>;
	145	clock-frequency = <88900000>;
	146	};
595dc1e1	147
cd62214d MY	148	serial1: serial@54006900 {
	149	compatible = "socionext,uniphier-uart";
	150	status = "disabled";
	151	reg = <0x54006900 0x40>;
	152	interrupts = <0 35 4>;
	153	pinctrl-names = "default";
	154	pinctrl-0 = <&pinctrl_uart1>;
	155	clocks = <&peri_clk 1>;
	156	clock-frequency = <88900000>;
	157	};
595dc1e1	158
cd62214d MY	159	serial2: serial@54006a00 {
	160	compatible = "socionext,uniphier-uart";
	161	status = "disabled";
	162	reg = <0x54006a00 0x40>;
	163	interrupts = <0 37 4>;
	164	pinctrl-names = "default";
	165	pinctrl-0 = <&pinctrl_uart2>;
	166	clocks = <&peri_clk 2>;
	167	clock-frequency = <88900000>;
	168	};
595dc1e1	169
cd62214d MY	170	serial3: serial@54006b00 {
	171	compatible = "socionext,uniphier-uart";
	172	status = "disabled";
	173	reg = <0x54006b00 0x40>;
	174	interrupts = <0 177 4>;
	175	pinctrl-names = "default";
	176	pinctrl-0 = <&pinctrl_uart3>;
	177	clocks = <&peri_clk 3>;
	178	clock-frequency = <88900000>;
	179	};
595dc1e1	180
cd62214d MY	181	port0x: gpio@55000008 {
	182	compatible = "socionext,uniphier-gpio";
	183	reg = <0x55000008 0x8>;
	184	gpio-controller;
	185	#gpio-cells = <2>;
	186	};
595dc1e1	187
cd62214d MY	188	port1x: gpio@55000010 {
	189	compatible = "socionext,uniphier-gpio";
	190	reg = <0x55000010 0x8>;
	191	gpio-controller;
	192	#gpio-cells = <2>;
	193	};
595dc1e1	194
cd62214d MY	195	port2x: gpio@55000018 {
	196	compatible = "socionext,uniphier-gpio";
	197	reg = <0x55000018 0x8>;
	198	gpio-controller;
	199	#gpio-cells = <2>;
	200	};
595dc1e1	201
cd62214d MY	202	port3x: gpio@55000020 {
	203	compatible = "socionext,uniphier-gpio";
	204	reg = <0x55000020 0x8>;
	205	gpio-controller;
	206	#gpio-cells = <2>;
	207	};
595dc1e1	208
cd62214d MY	209	port4: gpio@55000028 {
	210	compatible = "socionext,uniphier-gpio";
	211	reg = <0x55000028 0x8>;
	212	gpio-controller;
	213	#gpio-cells = <2>;
	214	};
595dc1e1	215
cd62214d MY	216	port5x: gpio@55000030 {
	217	compatible = "socionext,uniphier-gpio";
	218	reg = <0x55000030 0x8>;
	219	gpio-controller;
	220	#gpio-cells = <2>;
	221	};
595dc1e1	222
cd62214d MY	223	port6x: gpio@55000038 {
	224	compatible = "socionext,uniphier-gpio";
	225	reg = <0x55000038 0x8>;
	226	gpio-controller;
	227	#gpio-cells = <2>;
	228	};
595dc1e1	229
cd62214d MY	230	port7x: gpio@55000040 {
	231	compatible = "socionext,uniphier-gpio";
	232	reg = <0x55000040 0x8>;
	233	gpio-controller;
	234	#gpio-cells = <2>;
	235	};
595dc1e1	236
cd62214d MY	237	port8x: gpio@55000048 {
	238	compatible = "socionext,uniphier-gpio";
	239	reg = <0x55000048 0x8>;
	240	gpio-controller;
	241	#gpio-cells = <2>;
	242	};
595dc1e1	243
cd62214d MY	244	port9x: gpio@55000050 {
	245	compatible = "socionext,uniphier-gpio";
	246	reg = <0x55000050 0x8>;
	247	gpio-controller;
	248	#gpio-cells = <2>;
	249	};
595dc1e1	250
cd62214d MY	251	port10x: gpio@55000058 {
	252	compatible = "socionext,uniphier-gpio";
	253	reg = <0x55000058 0x8>;
	254	gpio-controller;
	255	#gpio-cells = <2>;
	256	};
595dc1e1	257
cd62214d MY	258	port12x: gpio@55000068 {
	259	compatible = "socionext,uniphier-gpio";
	260	reg = <0x55000068 0x8>;
	261	gpio-controller;
	262	#gpio-cells = <2>;
	263	};
595dc1e1	264
cd62214d MY	265	port13x: gpio@55000070 {
	266	compatible = "socionext,uniphier-gpio";
	267	reg = <0x55000070 0x8>;
	268	gpio-controller;
	269	#gpio-cells = <2>;
	270	};
595dc1e1	271
cd62214d MY	272	port14x: gpio@55000078 {
	273	compatible = "socionext,uniphier-gpio";
	274	reg = <0x55000078 0x8>;
	275	gpio-controller;
	276	#gpio-cells = <2>;
	277	};
595dc1e1	278
cd62214d MY	279	port15x: gpio@55000080 {
	280	compatible = "socionext,uniphier-gpio";
	281	reg = <0x55000080 0x8>;
	282	gpio-controller;
	283	#gpio-cells = <2>;
	284	};
595dc1e1	285
cd62214d MY	286	port16x: gpio@55000088 {
	287	compatible = "socionext,uniphier-gpio";
	288	reg = <0x55000088 0x8>;
	289	gpio-controller;
	290	#gpio-cells = <2>;
	291	};
595dc1e1	292
cd62214d MY	293	port17x: gpio@550000a0 {
	294	compatible = "socionext,uniphier-gpio";
	295	reg = <0x550000a0 0x8>;
	296	gpio-controller;
	297	#gpio-cells = <2>;
	298	};
595dc1e1	299
cd62214d MY	300	port18x: gpio@550000a8 {
	301	compatible = "socionext,uniphier-gpio";
	302	reg = <0x550000a8 0x8>;
	303	gpio-controller;
	304	#gpio-cells = <2>;
	305	};
595dc1e1	306
cd62214d MY	307	port19x: gpio@550000b0 {
	308	compatible = "socionext,uniphier-gpio";
	309	reg = <0x550000b0 0x8>;
	310	gpio-controller;
	311	#gpio-cells = <2>;
	312	};
595dc1e1	313
cd62214d MY	314	port20x: gpio@550000b8 {
	315	compatible = "socionext,uniphier-gpio";
	316	reg = <0x550000b8 0x8>;
	317	gpio-controller;
	318	#gpio-cells = <2>;
	319	};
595dc1e1	320
cd62214d MY	321	port21x: gpio@550000c0 {
	322	compatible = "socionext,uniphier-gpio";
	323	reg = <0x550000c0 0x8>;
	324	gpio-controller;
	325	#gpio-cells = <2>;
	326	};
595dc1e1	327
cd62214d MY	328	port22x: gpio@550000c8 {
	329	compatible = "socionext,uniphier-gpio";
	330	reg = <0x550000c8 0x8>;
	331	gpio-controller;
	332	#gpio-cells = <2>;
	333	};
595dc1e1	334
cd62214d MY	335	port23x: gpio@550000d0 {
	336	compatible = "socionext,uniphier-gpio";
	337	reg = <0x550000d0 0x8>;
	338	gpio-controller;
	339	#gpio-cells = <2>;
	340	};
595dc1e1	341
cd62214d MY	342	port24x: gpio@550000d8 {
	343	compatible = "socionext,uniphier-gpio";
	344	reg = <0x550000d8 0x8>;
	345	gpio-controller;
	346	#gpio-cells = <2>;
	347	};
4e1f81d4	348
cd62214d MY	349	port25x: gpio@550000e0 {
	350	compatible = "socionext,uniphier-gpio";
	351	reg = <0x550000e0 0x8>;
	352	gpio-controller;
	353	#gpio-cells = <2>;
	354	};
f875bbb4	355
cd62214d MY	356	port26x: gpio@550000e8 {
	357	compatible = "socionext,uniphier-gpio";
	358	reg = <0x550000e8 0x8>;
	359	gpio-controller;
	360	#gpio-cells = <2>;
	361	};
f875bbb4	362
cd62214d MY	363	port27x: gpio@550000f0 {
	364	compatible = "socionext,uniphier-gpio";
	365	reg = <0x550000f0 0x8>;
	366	gpio-controller;
	367	#gpio-cells = <2>;
	368	};
f875bbb4	369
cd62214d MY	370	port28x: gpio@550000f8 {
	371	compatible = "socionext,uniphier-gpio";
	372	reg = <0x550000f8 0x8>;
	373	gpio-controller;
	374	#gpio-cells = <2>;
	375	};
f875bbb4	376
cd62214d MY	377	i2c0: i2c@58780000 {
	378	compatible = "socionext,uniphier-fi2c";
	379	status = "disabled";
	380	reg = <0x58780000 0x80>;
	381	#address-cells = <1>;
	382	#size-cells = <0>;
	383	interrupts = <0 41 4>;
	384	pinctrl-names = "default";
	385	pinctrl-0 = <&pinctrl_i2c0>;
7317a940	386	clocks = <&peri_clk 4>;
cd62214d MY	387	clock-frequency = <100000>;
cd62214d MY	388	};
f875bbb4	389
cd62214d MY	390	i2c1: i2c@58781000 {
	391	compatible = "socionext,uniphier-fi2c";
	392	status = "disabled";
	393	reg = <0x58781000 0x80>;
	394	#address-cells = <1>;
	395	#size-cells = <0>;
	396	interrupts = <0 42 4>;
	397	pinctrl-names = "default";
	398	pinctrl-0 = <&pinctrl_i2c1>;
7317a940	399	clocks = <&peri_clk 5>;
cd62214d MY	400	clock-frequency = <100000>;
cd62214d MY	401	};
f875bbb4	402
cd62214d MY	403	i2c2: i2c@58782000 {
	404	compatible = "socionext,uniphier-fi2c";
	405	status = "disabled";
	406	reg = <0x58782000 0x80>;
	407	#address-cells = <1>;
	408	#size-cells = <0>;
	409	interrupts = <0 43 4>;
	410	pinctrl-names = "default";
	411	pinctrl-0 = <&pinctrl_i2c2>;
7317a940	412	clocks = <&peri_clk 6>;
cd62214d MY	413	clock-frequency = <100000>;
cd62214d MY	414	};
f875bbb4	415
cd62214d MY	416	i2c3: i2c@58783000 {
	417	compatible = "socionext,uniphier-fi2c";
	418	status = "disabled";
	419	reg = <0x58783000 0x80>;
	420	#address-cells = <1>;
	421	#size-cells = <0>;
	422	interrupts = <0 44 4>;
	423	pinctrl-names = "default";
	424	pinctrl-0 = <&pinctrl_i2c3>;
7317a940	425	clocks = <&peri_clk 7>;
cd62214d MY	426	clock-frequency = <100000>;
cd62214d MY	427	};
c7f94eec	428
cd62214d MY	429	/* chip-internal connection for DMD */
	430	i2c4: i2c@58784000 {
	431	compatible = "socionext,uniphier-fi2c";
	432	reg = <0x58784000 0x80>;
	433	#address-cells = <1>;
	434	#size-cells = <0>;
	435	interrupts = <0 45 4>;
7317a940	436	clocks = <&peri_clk 8>;
cd62214d MY	437	clock-frequency = <400000>;
cd62214d MY	438	};
c7f94eec	439
cd62214d MY	440	/* chip-internal connection for STM */
	441	i2c5: i2c@58785000 {
	442	compatible = "socionext,uniphier-fi2c";
	443	reg = <0x58785000 0x80>;
	444	#address-cells = <1>;
	445	#size-cells = <0>;
	446	interrupts = <0 25 4>;
7317a940	447	clocks = <&peri_clk 9>;
cd62214d MY	448	clock-frequency = <400000>;
cd62214d MY	449	};
1013aef3	450
cd62214d MY	451	/* chip-internal connection for HDMI */
	452	i2c6: i2c@58786000 {
	453	compatible = "socionext,uniphier-fi2c";
	454	reg = <0x58786000 0x80>;
	455	#address-cells = <1>;
	456	#size-cells = <0>;
	457	interrupts = <0 26 4>;
7317a940	458	clocks = <&peri_clk 10>;
cd62214d MY	459	clock-frequency = <400000>;
cd62214d MY	460	};
f875bbb4	461
cd62214d MY	462	system_bus: system-bus@58c00000 {
	463	compatible = "socionext,uniphier-system-bus";
	464	status = "disabled";
	465	reg = <0x58c00000 0x400>;
	466	#address-cells = <2>;
	467	#size-cells = <1>;
	468	pinctrl-names = "default";
	469	pinctrl-0 = <&pinctrl_system_bus>;
	470	};
f875bbb4	471
abb6ac25	472	smpctrl@59801000 {
cd62214d MY	473	compatible = "socionext,uniphier-smpctrl";
	474	reg = <0x59801000 0x400>;
	475	};
cc336095	476
cd62214d MY	477	sdctrl@59810000 {
	478	compatible = "socionext,uniphier-pxs2-sdctrl",
	479	"simple-mfd", "syscon";
6c9e46ef	480	reg = <0x59810000 0x400>;
cd62214d MY	481	u-boot,dm-pre-reloc;
	482
	483	sd_clk: clock {
	484	compatible = "socionext,uniphier-pxs2-sd-clock";
	485	#clock-cells = <1>;
	486	};
	487
	488	sd_rst: reset {
	489	compatible = "socionext,uniphier-pxs2-sd-reset";
	490	#reset-cells = <1>;
	491	};
	492	};
f875bbb4	493
cd62214d MY	494	perictrl@59820000 {
	495	compatible = "socionext,uniphier-pxs2-perictrl",
	496	"simple-mfd", "syscon";
	497	reg = <0x59820000 0x200>;
2610b136	498
cd62214d MY	499	peri_clk: clock {
	500	compatible = "socionext,uniphier-pxs2-peri-clock";
	501	#clock-cells = <1>;
	502	};
2610b136	503
cd62214d MY	504	peri_rst: reset {
	505	compatible = "socionext,uniphier-pxs2-peri-reset";
	506	#reset-cells = <1>;
	507	};
	508	};
f875bbb4	509
cd62214d MY	510	emmc: sdhc@5a000000 {
	511	compatible = "socionext,uniphier-sdhc";
	512	status = "disabled";
	513	reg = <0x5a000000 0x800>;
	514	interrupts = <0 78 4>;
	515	pinctrl-names = "default";
	516	pinctrl-0 = <&pinctrl_emmc>;
	517	clocks = <&sd_clk 1>;
	518	reset-names = "host";
	519	resets = <&sd_rst 1>;
	520	bus-width = <8>;
	521	non-removable;
	522	cap-mmc-highspeed;
	523	cap-mmc-hw-reset;
	524	no-3-3-v;
	525	};
35343a26	526
cd62214d MY	527	sd: sdhc@5a400000 {
	528	compatible = "socionext,uniphier-sdhc";
	529	status = "disabled";
	530	reg = <0x5a400000 0x800>;
	531	interrupts = <0 76 4>;
	532	pinctrl-names = "default", "1.8v";
	533	pinctrl-0 = <&pinctrl_sd>;
	534	pinctrl-1 = <&pinctrl_sd_1v8>;
	535	clocks = <&sd_clk 0>;
	536	reset-names = "host";
	537	resets = <&sd_rst 0>;
	538	bus-width = <4>;
	539	cap-sd-highspeed;
	540	sd-uhs-sdr12;
	541	sd-uhs-sdr25;
	542	sd-uhs-sdr50;
	543	};
35343a26	544
cd62214d MY	545	soc-glue@5f800000 {
	546	compatible = "socionext,uniphier-pxs2-soc-glue",
	547	"simple-mfd", "syscon";
	548	reg = <0x5f800000 0x2000>;
	549	u-boot,dm-pre-reloc;
aa37aba1	550
cd62214d MY	551	pinctrl: pinctrl {
	552	compatible = "socionext,uniphier-pxs2-pinctrl";
	553	u-boot,dm-pre-reloc;
	554	};
	555	};
9fbb2f7e	556
6c9e46ef MY	557	aidet: aidet@5fc20000 {
6c9e46ef MY	558	compatible = "socionext,uniphier-pxs2-aidet";
cd62214d	559	reg = <0x5fc20000 0x200>;
6c9e46ef MY	560	interrupt-controller;
6c9e46ef MY	561	#interrupt-cells = <2>;
cd62214d	562	};
233812a6	563
cd62214d MY	564	timer@60000200 {
	565	compatible = "arm,cortex-a9-global-timer";
	566	reg = <0x60000200 0x20>;
	567	interrupts = <1 11 0xf04>;
	568	clocks = <&arm_timer_clk>;
	569	};
	570
	571	timer@60000600 {
	572	compatible = "arm,cortex-a9-twd-timer";
	573	reg = <0x60000600 0x20>;
	574	interrupts = <1 13 0xf04>;
	575	clocks = <&arm_timer_clk>;
	576	};
	577
	578	intc: interrupt-controller@60001000 {
	579	compatible = "arm,cortex-a9-gic";
	580	reg = <0x60001000 0x1000>,
	581	<0x60000100 0x100>;
	582	#interrupt-cells = <3>;
	583	interrupt-controller;
	584	};
	585
	586	sysctrl@61840000 {
	587	compatible = "socionext,uniphier-pxs2-sysctrl",
	588	"simple-mfd", "syscon";
7317a940	589	reg = <0x61840000 0x10000>;
cd62214d MY	590
	591	sys_clk: clock {
	592	compatible = "socionext,uniphier-pxs2-clock";
	593	#clock-cells = <1>;
	594	};
35343a26	595
cd62214d MY	596	sys_rst: reset {
	597	compatible = "socionext,uniphier-pxs2-reset";
	598	#reset-cells = <1>;
	599	};
	600	};
	601
	602	usb0: usb@65b00000 {
	603	compatible = "socionext,uniphier-pxs2-dwc3";
	604	status = "disabled";
	605	reg = <0x65b00000 0x1000>;
	606	#address-cells = <1>;
	607	#size-cells = <1>;
	608	ranges;
	609	pinctrl-names = "default";
	610	pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
	611	dwc3@65a00000 {
	612	compatible = "snps,dwc3";
	613	reg = <0x65a00000 0x10000>;
	614	interrupts = <0 134 4>;
3444d1d4	615	dr_mode = "host";
cd62214d MY	616	tx-fifo-resize;
	617	};
	618	};
	619
	620	usb1: usb@65d00000 {
	621	compatible = "socionext,uniphier-pxs2-dwc3";
	622	status = "disabled";
	623	reg = <0x65d00000 0x1000>;
	624	#address-cells = <1>;
	625	#size-cells = <1>;
	626	ranges;
	627	pinctrl-names = "default";
	628	pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
	629	dwc3@65c00000 {
	630	compatible = "snps,dwc3";
	631	reg = <0x65c00000 0x10000>;
	632	interrupts = <0 137 4>;
3444d1d4	633	dr_mode = "host";
cd62214d MY	634	tx-fifo-resize;
	635	};
	636	};
	637
	638	nand: nand@68000000 {
4e7f8de4	639	compatible = "socionext,uniphier-denali-nand-v5b";
cd62214d MY	640	status = "disabled";
	641	reg-names = "nand_data", "denali_reg";
	642	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	643	interrupts = <0 65 4>;
	644	pinctrl-names = "default";
6c9e46ef	645	pinctrl-0 = <&pinctrl_nand2cs>;
cd62214d	646	clocks = <&sys_clk 2>;
cd62214d MY	647	};
cd62214d MY	648	};
233812a6	649	};
cd62214d	650
6c9e46ef	651	#include "uniphier-pinctrl.dtsi"