[people/ms/u-boot.git] / arch / arm / dts / uniphier-pxs2.dtsi

/*
 * Device Tree Source for UniPhier PXs2 SoC
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "socionext,uniphier-pxs2";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};
	};

	cpu_opp: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			clock-latency-ns = <300>;
		};
		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			clock-latency-ns = <300>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <300>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			clock-latency-ns = <300>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			clock-latency-ns = <300>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <300>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <300>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;	/* 250ms */
			polling-delay = <1000>;		/* 1000ms */
			thermal-sensors = <&pvtctl>;

			trips {
				cpu_crit: cpu-crit {
					temperature = <95000>;	/* 95C */
					hysteresis = <2000>;
					type = "critical";
				};
				cpu_alert: cpu-alert {
					temperature = <85000>;	/* 85C */
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map {
					trip = <&cpu_alert>;
					cooling-device = <&cpu0
					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
			cache-unified;
			cache-size = <(1280 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			clock-frequency = <88900000>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			clock-frequency = <88900000>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			clock-frequency = <88900000>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			clock-frequency = <88900000>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 96 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1";
			ngpios = <232>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
						     <21 217 3>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			clocks = <&peri_clk 8>;
			resets = <&peri_rst 8>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for STM */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			resets = <&peri_rst 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&peri_clk 10>;
			resets = <&peri_rst 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pxs2-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_clk: clock {
				compatible = "socionext,uniphier-pxs2-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pxs2-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pxs2-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pxs2-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pxs2-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a000000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a000000 0x800>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sd_clk 1>;
			reset-names = "host";
			resets = <&sd_rst 1>;
			bus-width = <8>;
			non-removable;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			no-3-3-v;
		};

		sd: sdhc@5a400000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a400000 0x800>;
			interrupts = <0 76 4>;
			pinctrl-names = "default", "1.8v";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_1v8>;
			clocks = <&sd_clk 0>;
			reset-names = "host";
			resets = <&sd_rst 0>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-pxs2-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pxs2-pinctrl";
			};
		};

		aidet: aidet@5fc20000 {
			compatible = "socionext,uniphier-pxs2-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pxs2-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pxs2-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pxs2-reset";
				#reset-cells = <1>;
			};

			pvtctl: pvtctl {
				compatible = "socionext,uniphier-pxs2-thermal";
				interrupts = <0 3 4>;
				#thermal-sensor-cells = <0>;
				socionext,tmod-calibration = <0x0f86 0x6844>;
			};
		};

		usb0: usb@65b00000 {
			compatible = "socionext,uniphier-pxs2-dwc3";
			status = "disabled";
			reg = <0x65b00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
			dwc3@65a00000 {
				compatible = "snps,dwc3";
				reg = <0x65a00000 0x10000>;
				interrupts = <0 134 4>;
				dr_mode = "host";
				tx-fifo-resize;
			};
		};

		usb1: usb@65d00000 {
			compatible = "socionext,uniphier-pxs2-dwc3";
			status = "disabled";
			reg = <0x65d00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
			dwc3@65c00000 {
				compatible = "snps,dwc3";
				reg = <0x65c00000 0x10000>;
				interrupts = <0 137 4>;
				dr_mode = "host";
				tx-fifo-resize;
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand2cs>;
			clocks = <&sys_clk 2>;
			resets = <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"
Commit	Line	Data
f875bbb4	1	/*
52159d27	2	* Device Tree Source for UniPhier PXs2 SoC
f875bbb4	3	*
52159d27 MY	4	* Copyright (C) 2015-2016 Socionext Inc.
52159d27 MY	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
f875bbb4	6	*
d9403001	7	* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
f875bbb4 MY	8	*/
f875bbb4 MY	9
b443fb42 MY	10	#include <dt-bindings/gpio/uniphier-gpio.h>
	11	#include <dt-bindings/thermal/thermal.h>
	12
f875bbb4	13	/ {
52159d27	14	compatible = "socionext,uniphier-pxs2";
f16eda96 MY	15	#address-cells = <1>;
f16eda96 MY	16	#size-cells = <1>;
f875bbb4 MY	17
	18	cpus {
	19	#address-cells = <1>;
	20	#size-cells = <0>;
f875bbb4	21
b443fb42	22	cpu0: cpu@0 {
f875bbb4 MY	23	device_type = "cpu";
	24	compatible = "arm,cortex-a9";
	25	reg = <0>;
cd62214d	26	clocks = <&sys_clk 32>;
52159d27	27	enable-method = "psci";
4e1f81d4	28	next-level-cache = <&l2>;
cd62214d	29	operating-points-v2 = <&cpu_opp>;
b443fb42	30	#cooling-cells = <2>;
f875bbb4 MY	31	};
f875bbb4 MY	32
b443fb42	33	cpu1: cpu@1 {
f875bbb4 MY	34	device_type = "cpu";
	35	compatible = "arm,cortex-a9";
	36	reg = <1>;
cd62214d	37	clocks = <&sys_clk 32>;
52159d27	38	enable-method = "psci";
4e1f81d4	39	next-level-cache = <&l2>;
cd62214d	40	operating-points-v2 = <&cpu_opp>;
f875bbb4 MY	41	};
f875bbb4 MY	42
b443fb42	43	cpu2: cpu@2 {
f875bbb4 MY	44	device_type = "cpu";
	45	compatible = "arm,cortex-a9";
	46	reg = <2>;
cd62214d	47	clocks = <&sys_clk 32>;
52159d27	48	enable-method = "psci";
4e1f81d4	49	next-level-cache = <&l2>;
cd62214d	50	operating-points-v2 = <&cpu_opp>;
f875bbb4 MY	51	};
f875bbb4 MY	52
b443fb42	53	cpu3: cpu@3 {
f875bbb4 MY	54	device_type = "cpu";
	55	compatible = "arm,cortex-a9";
	56	reg = <3>;
cd62214d	57	clocks = <&sys_clk 32>;
52159d27	58	enable-method = "psci";
4e1f81d4	59	next-level-cache = <&l2>;
cd62214d	60	operating-points-v2 = <&cpu_opp>;
f875bbb4 MY	61	};
	62	};
	63
b443fb42	64	cpu_opp: opp-table {
cd62214d MY	65	compatible = "operating-points-v2";
	66	opp-shared;
	67
4e7f8de4	68	opp-100000000 {
cd62214d MY	69	opp-hz = /bits/ 64 <100000000>;
	70	clock-latency-ns = <300>;
	71	};
4e7f8de4	72	opp-150000000 {
cd62214d MY	73	opp-hz = /bits/ 64 <150000000>;
	74	clock-latency-ns = <300>;
	75	};
4e7f8de4	76	opp-200000000 {
cd62214d MY	77	opp-hz = /bits/ 64 <200000000>;
	78	clock-latency-ns = <300>;
	79	};
4e7f8de4	80	opp-300000000 {
cd62214d MY	81	opp-hz = /bits/ 64 <300000000>;
	82	clock-latency-ns = <300>;
	83	};
4e7f8de4	84	opp-400000000 {
cd62214d MY	85	opp-hz = /bits/ 64 <400000000>;
	86	clock-latency-ns = <300>;
	87	};
4e7f8de4	88	opp-600000000 {
cd62214d MY	89	opp-hz = /bits/ 64 <600000000>;
	90	clock-latency-ns = <300>;
	91	};
4e7f8de4	92	opp-800000000 {
cd62214d MY	93	opp-hz = /bits/ 64 <800000000>;
	94	clock-latency-ns = <300>;
	95	};
4e7f8de4	96	opp-1200000000 {
cd62214d MY	97	opp-hz = /bits/ 64 <1200000000>;
	98	clock-latency-ns = <300>;
	99	};
	100	};
	101
	102	psci {
	103	compatible = "arm,psci-0.2";
	104	method = "smc";
	105	};
	106
f875bbb4	107	clocks {
cd62214d MY	108	refclk: ref {
	109	compatible = "fixed-clock";
	110	#clock-cells = <0>;
	111	clock-frequency = <25000000>;
	112	};
	113
b443fb42	114	arm_timer_clk: arm-timer {
f875bbb4 MY	115	#clock-cells = <0>;
	116	compatible = "fixed-clock";
	117	clock-frequency = <50000000>;
	118	};
f875bbb4 MY	119	};
f875bbb4 MY	120
b443fb42 MY	121	thermal-zones {
	122	cpu-thermal {
	123	polling-delay-passive = <250>; /* 250ms */
	124	polling-delay = <1000>; /* 1000ms */
	125	thermal-sensors = <&pvtctl>;
	126
	127	trips {
	128	cpu_crit: cpu-crit {
	129	temperature = <95000>; /* 95C */
	130	hysteresis = <2000>;
	131	type = "critical";
	132	};
	133	cpu_alert: cpu-alert {
	134	temperature = <85000>; /* 85C */
	135	hysteresis = <2000>;
	136	type = "passive";
	137	};
	138	};
	139
	140	cooling-maps {
	141	map {
	142	trip = <&cpu_alert>;
	143	cooling-device = <&cpu0
	144	THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	145	};
	146	};
	147	};
	148	};
	149
cd62214d MY	150	soc {
	151	compatible = "simple-bus";
	152	#address-cells = <1>;
	153	#size-cells = <1>;
	154	ranges;
	155	interrupt-parent = <&intc>;
cd62214d MY	156
	157	l2: l2-cache@500c0000 {
	158	compatible = "socionext,uniphier-system-cache";
	159	reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
	160	<0x506c0000 0x400>;
	161	interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
	162	cache-unified;
	163	cache-size = <(1280 * 1024)>;
	164	cache-sets = <512>;
	165	cache-line-size = <128>;
	166	cache-level = <2>;
	167	};
595dc1e1	168
cd62214d MY	169	serial0: serial@54006800 {
	170	compatible = "socionext,uniphier-uart";
	171	status = "disabled";
	172	reg = <0x54006800 0x40>;
	173	interrupts = <0 33 4>;
	174	pinctrl-names = "default";
	175	pinctrl-0 = <&pinctrl_uart0>;
	176	clocks = <&peri_clk 0>;
	177	clock-frequency = <88900000>;
b443fb42	178	resets = <&peri_rst 0>;
cd62214d	179	};
595dc1e1	180
cd62214d MY	181	serial1: serial@54006900 {
	182	compatible = "socionext,uniphier-uart";
	183	status = "disabled";
	184	reg = <0x54006900 0x40>;
	185	interrupts = <0 35 4>;
	186	pinctrl-names = "default";
	187	pinctrl-0 = <&pinctrl_uart1>;
	188	clocks = <&peri_clk 1>;
	189	clock-frequency = <88900000>;
b443fb42	190	resets = <&peri_rst 1>;
cd62214d	191	};
595dc1e1	192
cd62214d MY	193	serial2: serial@54006a00 {
	194	compatible = "socionext,uniphier-uart";
	195	status = "disabled";
	196	reg = <0x54006a00 0x40>;
	197	interrupts = <0 37 4>;
	198	pinctrl-names = "default";
	199	pinctrl-0 = <&pinctrl_uart2>;
	200	clocks = <&peri_clk 2>;
	201	clock-frequency = <88900000>;
b443fb42	202	resets = <&peri_rst 2>;
cd62214d	203	};
595dc1e1	204
cd62214d MY	205	serial3: serial@54006b00 {
	206	compatible = "socionext,uniphier-uart";
	207	status = "disabled";
	208	reg = <0x54006b00 0x40>;
	209	interrupts = <0 177 4>;
	210	pinctrl-names = "default";
	211	pinctrl-0 = <&pinctrl_uart3>;
	212	clocks = <&peri_clk 3>;
	213	clock-frequency = <88900000>;
b443fb42	214	resets = <&peri_rst 3>;
cd62214d	215	};
595dc1e1	216
0f72b74b	217	gpio: gpio@55000000 {
cd62214d	218	compatible = "socionext,uniphier-gpio";
0f72b74b MY	219	reg = <0x55000000 0x200>;
	220	interrupt-parent = <&aidet>;
	221	interrupt-controller;
	222	#interrupt-cells = <2>;
cd62214d MY	223	gpio-controller;
cd62214d MY	224	#gpio-cells = <2>;
0f72b74b MY	225	gpio-ranges = <&pinctrl 0 0 0>,
	226	<&pinctrl 96 0 0>;
	227	gpio-ranges-group-names = "gpio_range0",
	228	"gpio_range1";
	229	ngpios = <232>;
b443fb42 MY	230	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
b443fb42 MY	231	<21 217 3>;
cd62214d	232	};
f875bbb4	233
cd62214d MY	234	i2c0: i2c@58780000 {
	235	compatible = "socionext,uniphier-fi2c";
	236	status = "disabled";
	237	reg = <0x58780000 0x80>;
	238	#address-cells = <1>;
	239	#size-cells = <0>;
	240	interrupts = <0 41 4>;
	241	pinctrl-names = "default";
	242	pinctrl-0 = <&pinctrl_i2c0>;
7317a940	243	clocks = <&peri_clk 4>;
b443fb42	244	resets = <&peri_rst 4>;
cd62214d MY	245	clock-frequency = <100000>;
cd62214d MY	246	};
f875bbb4	247
cd62214d MY	248	i2c1: i2c@58781000 {
	249	compatible = "socionext,uniphier-fi2c";
	250	status = "disabled";
	251	reg = <0x58781000 0x80>;
	252	#address-cells = <1>;
	253	#size-cells = <0>;
	254	interrupts = <0 42 4>;
	255	pinctrl-names = "default";
	256	pinctrl-0 = <&pinctrl_i2c1>;
7317a940	257	clocks = <&peri_clk 5>;
b443fb42	258	resets = <&peri_rst 5>;
cd62214d MY	259	clock-frequency = <100000>;
cd62214d MY	260	};
f875bbb4	261
cd62214d MY	262	i2c2: i2c@58782000 {
	263	compatible = "socionext,uniphier-fi2c";
	264	status = "disabled";
	265	reg = <0x58782000 0x80>;
	266	#address-cells = <1>;
	267	#size-cells = <0>;
	268	interrupts = <0 43 4>;
	269	pinctrl-names = "default";
	270	pinctrl-0 = <&pinctrl_i2c2>;
7317a940	271	clocks = <&peri_clk 6>;
b443fb42	272	resets = <&peri_rst 6>;
cd62214d MY	273	clock-frequency = <100000>;
cd62214d MY	274	};
f875bbb4	275
cd62214d MY	276	i2c3: i2c@58783000 {
	277	compatible = "socionext,uniphier-fi2c";
	278	status = "disabled";
	279	reg = <0x58783000 0x80>;
	280	#address-cells = <1>;
	281	#size-cells = <0>;
	282	interrupts = <0 44 4>;
	283	pinctrl-names = "default";
	284	pinctrl-0 = <&pinctrl_i2c3>;
7317a940	285	clocks = <&peri_clk 7>;
b443fb42	286	resets = <&peri_rst 7>;
cd62214d MY	287	clock-frequency = <100000>;
cd62214d MY	288	};
c7f94eec	289
cd62214d MY	290	/* chip-internal connection for DMD */
	291	i2c4: i2c@58784000 {
	292	compatible = "socionext,uniphier-fi2c";
	293	reg = <0x58784000 0x80>;
	294	#address-cells = <1>;
	295	#size-cells = <0>;
	296	interrupts = <0 45 4>;
7317a940	297	clocks = <&peri_clk 8>;
b443fb42	298	resets = <&peri_rst 8>;
cd62214d MY	299	clock-frequency = <400000>;
cd62214d MY	300	};
c7f94eec	301
cd62214d MY	302	/* chip-internal connection for STM */
	303	i2c5: i2c@58785000 {
	304	compatible = "socionext,uniphier-fi2c";
	305	reg = <0x58785000 0x80>;
	306	#address-cells = <1>;
	307	#size-cells = <0>;
	308	interrupts = <0 25 4>;
7317a940	309	clocks = <&peri_clk 9>;
b443fb42	310	resets = <&peri_rst 9>;
cd62214d MY	311	clock-frequency = <400000>;
cd62214d MY	312	};
1013aef3	313
cd62214d MY	314	/* chip-internal connection for HDMI */
	315	i2c6: i2c@58786000 {
	316	compatible = "socionext,uniphier-fi2c";
	317	reg = <0x58786000 0x80>;
	318	#address-cells = <1>;
	319	#size-cells = <0>;
	320	interrupts = <0 26 4>;
7317a940	321	clocks = <&peri_clk 10>;
b443fb42	322	resets = <&peri_rst 10>;
cd62214d MY	323	clock-frequency = <400000>;
cd62214d MY	324	};
f875bbb4	325
cd62214d MY	326	system_bus: system-bus@58c00000 {
	327	compatible = "socionext,uniphier-system-bus";
	328	status = "disabled";
	329	reg = <0x58c00000 0x400>;
	330	#address-cells = <2>;
	331	#size-cells = <1>;
	332	pinctrl-names = "default";
	333	pinctrl-0 = <&pinctrl_system_bus>;
	334	};
f875bbb4	335
abb6ac25	336	smpctrl@59801000 {
cd62214d MY	337	compatible = "socionext,uniphier-smpctrl";
	338	reg = <0x59801000 0x400>;
	339	};
cc336095	340
cd62214d MY	341	sdctrl@59810000 {
	342	compatible = "socionext,uniphier-pxs2-sdctrl",
	343	"simple-mfd", "syscon";
6c9e46ef	344	reg = <0x59810000 0x400>;
cd62214d MY	345
	346	sd_clk: clock {
	347	compatible = "socionext,uniphier-pxs2-sd-clock";
	348	#clock-cells = <1>;
	349	};
	350
	351	sd_rst: reset {
	352	compatible = "socionext,uniphier-pxs2-sd-reset";
	353	#reset-cells = <1>;
	354	};
	355	};
f875bbb4	356
cd62214d MY	357	perictrl@59820000 {
	358	compatible = "socionext,uniphier-pxs2-perictrl",
	359	"simple-mfd", "syscon";
	360	reg = <0x59820000 0x200>;
2610b136	361
cd62214d MY	362	peri_clk: clock {
	363	compatible = "socionext,uniphier-pxs2-peri-clock";
	364	#clock-cells = <1>;
	365	};
2610b136	366
cd62214d MY	367	peri_rst: reset {
	368	compatible = "socionext,uniphier-pxs2-peri-reset";
	369	#reset-cells = <1>;
	370	};
	371	};
f875bbb4	372
cd62214d MY	373	emmc: sdhc@5a000000 {
	374	compatible = "socionext,uniphier-sdhc";
	375	status = "disabled";
	376	reg = <0x5a000000 0x800>;
	377	interrupts = <0 78 4>;
	378	pinctrl-names = "default";
	379	pinctrl-0 = <&pinctrl_emmc>;
	380	clocks = <&sd_clk 1>;
	381	reset-names = "host";
	382	resets = <&sd_rst 1>;
	383	bus-width = <8>;
	384	non-removable;
	385	cap-mmc-highspeed;
	386	cap-mmc-hw-reset;
	387	no-3-3-v;
	388	};
35343a26	389
cd62214d MY	390	sd: sdhc@5a400000 {
	391	compatible = "socionext,uniphier-sdhc";
	392	status = "disabled";
	393	reg = <0x5a400000 0x800>;
	394	interrupts = <0 76 4>;
	395	pinctrl-names = "default", "1.8v";
	396	pinctrl-0 = <&pinctrl_sd>;
	397	pinctrl-1 = <&pinctrl_sd_1v8>;
	398	clocks = <&sd_clk 0>;
	399	reset-names = "host";
	400	resets = <&sd_rst 0>;
	401	bus-width = <4>;
	402	cap-sd-highspeed;
	403	sd-uhs-sdr12;
	404	sd-uhs-sdr25;
	405	sd-uhs-sdr50;
	406	};
35343a26	407
cd62214d MY	408	soc-glue@5f800000 {
	409	compatible = "socionext,uniphier-pxs2-soc-glue",
	410	"simple-mfd", "syscon";
	411	reg = <0x5f800000 0x2000>;
aa37aba1	412
cd62214d MY	413	pinctrl: pinctrl {
cd62214d MY	414	compatible = "socionext,uniphier-pxs2-pinctrl";
cd62214d MY	415	};
cd62214d MY	416	};
9fbb2f7e	417
6c9e46ef MY	418	aidet: aidet@5fc20000 {
6c9e46ef MY	419	compatible = "socionext,uniphier-pxs2-aidet";
cd62214d	420	reg = <0x5fc20000 0x200>;
6c9e46ef MY	421	interrupt-controller;
6c9e46ef MY	422	#interrupt-cells = <2>;
cd62214d	423	};
233812a6	424
cd62214d MY	425	timer@60000200 {
	426	compatible = "arm,cortex-a9-global-timer";
	427	reg = <0x60000200 0x20>;
	428	interrupts = <1 11 0xf04>;
	429	clocks = <&arm_timer_clk>;
	430	};
	431
	432	timer@60000600 {
	433	compatible = "arm,cortex-a9-twd-timer";
	434	reg = <0x60000600 0x20>;
	435	interrupts = <1 13 0xf04>;
	436	clocks = <&arm_timer_clk>;
	437	};
	438
	439	intc: interrupt-controller@60001000 {
	440	compatible = "arm,cortex-a9-gic";
	441	reg = <0x60001000 0x1000>,
	442	<0x60000100 0x100>;
	443	#interrupt-cells = <3>;
	444	interrupt-controller;
	445	};
	446
	447	sysctrl@61840000 {
	448	compatible = "socionext,uniphier-pxs2-sysctrl",
	449	"simple-mfd", "syscon";
7317a940	450	reg = <0x61840000 0x10000>;
cd62214d MY	451
	452	sys_clk: clock {
	453	compatible = "socionext,uniphier-pxs2-clock";
	454	#clock-cells = <1>;
	455	};
35343a26	456
cd62214d MY	457	sys_rst: reset {
	458	compatible = "socionext,uniphier-pxs2-reset";
	459	#reset-cells = <1>;
	460	};
b443fb42 MY	461
	462	pvtctl: pvtctl {
	463	compatible = "socionext,uniphier-pxs2-thermal";
	464	interrupts = <0 3 4>;
	465	#thermal-sensor-cells = <0>;
	466	socionext,tmod-calibration = <0x0f86 0x6844>;
	467	};
cd62214d MY	468	};
	469
	470	usb0: usb@65b00000 {
	471	compatible = "socionext,uniphier-pxs2-dwc3";
	472	status = "disabled";
	473	reg = <0x65b00000 0x1000>;
	474	#address-cells = <1>;
	475	#size-cells = <1>;
	476	ranges;
	477	pinctrl-names = "default";
	478	pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
	479	dwc3@65a00000 {
	480	compatible = "snps,dwc3";
	481	reg = <0x65a00000 0x10000>;
	482	interrupts = <0 134 4>;
3444d1d4	483	dr_mode = "host";
cd62214d MY	484	tx-fifo-resize;
	485	};
	486	};
	487
	488	usb1: usb@65d00000 {
	489	compatible = "socionext,uniphier-pxs2-dwc3";
	490	status = "disabled";
	491	reg = <0x65d00000 0x1000>;
	492	#address-cells = <1>;
	493	#size-cells = <1>;
	494	ranges;
	495	pinctrl-names = "default";
	496	pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
	497	dwc3@65c00000 {
	498	compatible = "snps,dwc3";
	499	reg = <0x65c00000 0x10000>;
	500	interrupts = <0 137 4>;
3444d1d4	501	dr_mode = "host";
cd62214d MY	502	tx-fifo-resize;
	503	};
	504	};
	505
	506	nand: nand@68000000 {
4e7f8de4	507	compatible = "socionext,uniphier-denali-nand-v5b";
cd62214d MY	508	status = "disabled";
	509	reg-names = "nand_data", "denali_reg";
	510	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	511	interrupts = <0 65 4>;
	512	pinctrl-names = "default";
6c9e46ef	513	pinctrl-0 = <&pinctrl_nand2cs>;
cd62214d	514	clocks = <&sys_clk 2>;
b443fb42	515	resets = <&sys_rst 2>;
cd62214d MY	516	};
cd62214d MY	517	};
233812a6	518	};
cd62214d	519
6c9e46ef	520	#include "uniphier-pinctrl.dtsi"