[people/ms/u-boot.git] / arch / arm / dts / uniphier-pxs3-ref.dts

/*
 * Device Tree Source for UniPhier PXs3 Reference Board
 *
 * Copyright (C) 2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/dts-v1/;
#include "uniphier-pxs3.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier PXs3 Reference Board";
	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c6 = &i2c6;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0xa0000000>;
	};
};

&ethsc {
	interrupts = <4 8>;
};

&serial0 {
	status = "okay";
};

&gpio {
	xirq4 {
		gpio-hog;
		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
		input;
	};
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&nand {
	status = "okay";
};
Commit	Line	Data
61e6cc0a MY	1	/*
	2	* Device Tree Source for UniPhier PXs3 Reference Board
	3	*
	4	* Copyright (C) 2017 Socionext Inc.
	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
	6	*
31c86aa7	7	* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
61e6cc0a MY	8	*/
	9
	10	/dts-v1/;
31c86aa7 MY	11	#include "uniphier-pxs3.dtsi"
31c86aa7 MY	12	#include "uniphier-support-card.dtsi"
61e6cc0a MY	13
	14	/ {
	15	model = "UniPhier PXs3 Reference Board";
	16	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
	17
7ad79c12 MY	18	chosen {
	19	stdout-path = "serial0:115200n8";
	20	};
	21
61e6cc0a MY	22	aliases {
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	serial2 = &serial2;
	26	serial3 = &serial3;
	27	i2c0 = &i2c0;
	28	i2c1 = &i2c1;
	29	i2c2 = &i2c2;
	30	i2c3 = &i2c3;
	31	i2c6 = &i2c6;
	32	};
	33
7ad79c12	34	memory@80000000 {
61e6cc0a MY	35	device_type = "memory";
	36	reg = <0 0x80000000 0 0xa0000000>;
	37	};
61e6cc0a MY	38	};
	39
	40	&ethsc {
b443fb42	41	interrupts = <4 8>;
61e6cc0a MY	42	};
	43
	44	&serial0 {
	45	status = "okay";
	46	};
	47
b443fb42 MY	48	&gpio {
	49	xirq4 {
	50	gpio-hog;
	51	gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
	52	input;
	53	};
	54	};
	55
61e6cc0a MY	56	&i2c0 {
	57	status = "okay";
	58	};
31c86aa7 MY	59
	60	&i2c1 {
	61	status = "okay";
	62	};
	63
	64	&i2c2 {
	65	status = "okay";
	66	};
	67
	68	&i2c3 {
	69	status = "okay";
	70	};
	71
	72	&usb0 {
	73	status = "okay";
	74	};
	75
	76	&usb1 {
	77	status = "okay";
	78	};
27287487 MY	79
	80	&nand {
	81	status = "okay";
	82	};