[people/ms/u-boot.git] / arch / arm / dts / uniphier-pxs3.dtsi

/*
 * Device Tree Source for UniPhier PXs3 SoC
 *
 * Copyright (C) 2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/memreserve/ 0x80000000 0x02000000;

/ {
	compatible = "socionext,uniphier-pxs3";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x000>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x001>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x002>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x003>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};
	};

	cluster0_opp: opp_table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-325000000 {
			opp-hz = /bits/ 64 <325000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-650000000 {
			opp-hz = /bits/ 64 <650000000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-866667000 {
			opp-hz = /bits/ 64 <866667000>;
			clock-latency-ns = <300>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <300>;
		};
		opp-1300000000 {
			opp-hz = /bits/ 64 <1300000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>,
			     <1 14 4>,
			     <1 11 4>,
			     <1 10 4>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			clock-frequency = <58820000>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			clock-frequency = <58820000>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			clock-frequency = <58820000>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			clock-frequency = <58820000>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-pxs3-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 96 0 0>,
				      <&pinctrl 160 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1",
						  "gpio_range2";
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&peri_clk 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pxs3-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_clk: clock {
				compatible = "socionext,uniphier-pxs3-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pxs3-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pxs3-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pxs3-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pxs3-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a000000 {
			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
			reg = <0x5a000000 0x400>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc_1v8>;
			clocks = <&sys_clk 4>;
			bus-width = <8>;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			cdns,phy-input-delay-legacy = <4>;
			cdns,phy-input-delay-mmc-highspeed = <2>;
			cdns,phy-input-delay-mmc-ddr = <3>;
			cdns,phy-dll-delay-sdclk = <21>;
			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
		};

		sd: sdhc@5a400000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a400000 0x800>;
			interrupts = <0 76 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sd>;
			clocks = <&sd_clk 0>;
			reset-names = "host";
			resets = <&sd_rst 0>;
			bus-width = <4>;
			cap-sd-highspeed;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-pxs3-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pxs3-pinctrl";
			};
		};

		aidet: aidet@5fc20000 {
			compatible = "socionext,uniphier-pxs3-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gic: interrupt-controller@5fe00000 {
			compatible = "arm,gic-v3";
			reg = <0x5fe00000 0x10000>,	/* GICD */
			      <0x5fe80000 0x80000>;	/* GICR */
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 4>;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pxs3-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pxs3-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pxs3-reset";
				#reset-cells = <1>;
			};

			watchdog {
				compatible = "socionext,uniphier-wdt";
			};
		};

		usb0: usb@65b00000 {
			compatible = "socionext,uniphier-pxs3-dwc3";
			status = "disabled";
			reg = <0x65b00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
			dwc3@65a00000 {
				compatible = "snps,dwc3";
				reg = <0x65a00000 0x10000>;
				interrupts = <0 134 4>;
				dr_mode = "host";
				tx-fifo-resize;
			};
		};

		usb1: usb@65d00000 {
			compatible = "socionext,uniphier-pxs3-dwc3";
			status = "disabled";
			reg = <0x65d00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
			dwc3@65c00000 {
				compatible = "snps,dwc3";
				reg = <0x65c00000 0x10000>;
				interrupts = <0 137 4>;
				dr_mode = "host";
				tx-fifo-resize;
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clocks = <&sys_clk 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"
Commit	Line	Data
61e6cc0a MY	1	/*
	2	* Device Tree Source for UniPhier PXs3 SoC
	3	*
	4	* Copyright (C) 2017 Socionext Inc.
	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
	6	*
31c86aa7	7	* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
61e6cc0a MY	8	*/
61e6cc0a MY	9
31c86aa7	10	/memreserve/ 0x80000000 0x02000000;
61e6cc0a MY	11
	12	/ {
	13	compatible = "socionext,uniphier-pxs3";
	14	#address-cells = <2>;
	15	#size-cells = <2>;
	16	interrupt-parent = <&gic>;
	17
	18	cpus {
	19	#address-cells = <2>;
	20	#size-cells = <0>;
	21
	22	cpu-map {
	23	cluster0 {
	24	core0 {
	25	cpu = <&cpu0>;
	26	};
	27	core1 {
	28	cpu = <&cpu1>;
	29	};
	30	core2 {
	31	cpu = <&cpu2>;
	32	};
	33	core3 {
	34	cpu = <&cpu3>;
	35	};
	36	};
	37	};
	38
	39	cpu0: cpu@0 {
	40	device_type = "cpu";
	41	compatible = "arm,cortex-a53", "arm,armv8";
	42	reg = <0 0x000>;
31c86aa7	43	clocks = <&sys_clk 33>;
61e6cc0a	44	enable-method = "psci";
31c86aa7	45	operating-points-v2 = <&cluster0_opp>;
61e6cc0a MY	46	};
	47
	48	cpu1: cpu@1 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a53", "arm,armv8";
	51	reg = <0 0x001>;
31c86aa7	52	clocks = <&sys_clk 33>;
61e6cc0a	53	enable-method = "psci";
31c86aa7	54	operating-points-v2 = <&cluster0_opp>;
61e6cc0a MY	55	};
	56
	57	cpu2: cpu@2 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a53", "arm,armv8";
	60	reg = <0 0x002>;
31c86aa7	61	clocks = <&sys_clk 33>;
61e6cc0a	62	enable-method = "psci";
31c86aa7	63	operating-points-v2 = <&cluster0_opp>;
61e6cc0a MY	64	};
	65
	66	cpu3: cpu@3 {
	67	device_type = "cpu";
	68	compatible = "arm,cortex-a53", "arm,armv8";
	69	reg = <0 0x003>;
31c86aa7	70	clocks = <&sys_clk 33>;
61e6cc0a	71	enable-method = "psci";
31c86aa7 MY	72	operating-points-v2 = <&cluster0_opp>;
	73	};
	74	};
	75
	76	cluster0_opp: opp_table {
	77	compatible = "operating-points-v2";
	78	opp-shared;
	79
	80	opp-250000000 {
	81	opp-hz = /bits/ 64 <250000000>;
	82	clock-latency-ns = <300>;
	83	};
	84	opp-325000000 {
	85	opp-hz = /bits/ 64 <325000000>;
	86	clock-latency-ns = <300>;
	87	};
	88	opp-500000000 {
	89	opp-hz = /bits/ 64 <500000000>;
	90	clock-latency-ns = <300>;
	91	};
	92	opp-650000000 {
	93	opp-hz = /bits/ 64 <650000000>;
	94	clock-latency-ns = <300>;
	95	};
	96	opp-666667000 {
	97	opp-hz = /bits/ 64 <666667000>;
	98	clock-latency-ns = <300>;
	99	};
	100	opp-866667000 {
	101	opp-hz = /bits/ 64 <866667000>;
	102	clock-latency-ns = <300>;
	103	};
	104	opp-1000000000 {
	105	opp-hz = /bits/ 64 <1000000000>;
	106	clock-latency-ns = <300>;
	107	};
	108	opp-1300000000 {
	109	opp-hz = /bits/ 64 <1300000000>;
	110	clock-latency-ns = <300>;
61e6cc0a MY	111	};
	112	};
	113
	114	psci {
	115	compatible = "arm,psci-1.0";
	116	method = "smc";
	117	};
	118
	119	clocks {
	120	refclk: ref {
	121	compatible = "fixed-clock";
	122	#clock-cells = <0>;
	123	clock-frequency = <25000000>;
	124	};
	125	};
	126
	127	timer {
	128	compatible = "arm,armv8-timer";
	129	interrupts = <1 13 4>,
	130	<1 14 4>,
	131	<1 11 4>,
	132	<1 10 4>;
	133	};
	134
7ad79c12	135	soc@0 {
61e6cc0a MY	136	compatible = "simple-bus";
	137	#address-cells = <1>;
	138	#size-cells = <1>;
	139	ranges = <0 0 0 0xffffffff>;
	140
	141	serial0: serial@54006800 {
	142	compatible = "socionext,uniphier-uart";
	143	status = "disabled";
	144	reg = <0x54006800 0x40>;
	145	interrupts = <0 33 4>;
	146	pinctrl-names = "default";
	147	pinctrl-0 = <&pinctrl_uart0>;
	148	clocks = <&peri_clk 0>;
	149	clock-frequency = <58820000>;
	150	};
	151
	152	serial1: serial@54006900 {
	153	compatible = "socionext,uniphier-uart";
	154	status = "disabled";
	155	reg = <0x54006900 0x40>;
	156	interrupts = <0 35 4>;
	157	pinctrl-names = "default";
	158	pinctrl-0 = <&pinctrl_uart1>;
	159	clocks = <&peri_clk 1>;
	160	clock-frequency = <58820000>;
	161	};
	162
	163	serial2: serial@54006a00 {
	164	compatible = "socionext,uniphier-uart";
	165	status = "disabled";
	166	reg = <0x54006a00 0x40>;
	167	interrupts = <0 37 4>;
	168	pinctrl-names = "default";
	169	pinctrl-0 = <&pinctrl_uart2>;
	170	clocks = <&peri_clk 2>;
	171	clock-frequency = <58820000>;
	172	};
	173
	174	serial3: serial@54006b00 {
	175	compatible = "socionext,uniphier-uart";
	176	status = "disabled";
	177	reg = <0x54006b00 0x40>;
	178	interrupts = <0 177 4>;
	179	pinctrl-names = "default";
	180	pinctrl-0 = <&pinctrl_uart3>;
	181	clocks = <&peri_clk 3>;
	182	clock-frequency = <58820000>;
	183	};
	184
31c86aa7 MY	185	gpio: gpio@55000000 {
	186	compatible = "socionext,uniphier-pxs3-gpio";
	187	reg = <0x55000000 0x200>;
	188	interrupt-parent = <&aidet>;
	189	interrupt-controller;
	190	#interrupt-cells = <2>;
	191	gpio-controller;
	192	#gpio-cells = <2>;
	193	gpio-ranges = <&pinctrl 0 0 0>,
	194	<&pinctrl 96 0 0>,
	195	<&pinctrl 160 0 0>;
	196	gpio-ranges-group-names = "gpio_range0",
	197	"gpio_range1",
	198	"gpio_range2";
	199	};
	200
61e6cc0a MY	201	i2c0: i2c@58780000 {
	202	compatible = "socionext,uniphier-fi2c";
	203	status = "disabled";
	204	reg = <0x58780000 0x80>;
	205	#address-cells = <1>;
	206	#size-cells = <0>;
	207	interrupts = <0 41 4>;
	208	pinctrl-names = "default";
	209	pinctrl-0 = <&pinctrl_i2c0>;
	210	clocks = <&peri_clk 4>;
	211	clock-frequency = <100000>;
	212	};
	213
	214	i2c1: i2c@58781000 {
	215	compatible = "socionext,uniphier-fi2c";
	216	status = "disabled";
	217	reg = <0x58781000 0x80>;
	218	#address-cells = <1>;
	219	#size-cells = <0>;
	220	interrupts = <0 42 4>;
	221	pinctrl-names = "default";
	222	pinctrl-0 = <&pinctrl_i2c1>;
	223	clocks = <&peri_clk 5>;
	224	clock-frequency = <100000>;
	225	};
	226
	227	i2c2: i2c@58782000 {
	228	compatible = "socionext,uniphier-fi2c";
	229	status = "disabled";
	230	reg = <0x58782000 0x80>;
	231	#address-cells = <1>;
	232	#size-cells = <0>;
	233	interrupts = <0 43 4>;
31c86aa7 MY	234	pinctrl-names = "default";
31c86aa7 MY	235	pinctrl-0 = <&pinctrl_i2c2>;
61e6cc0a MY	236	clocks = <&peri_clk 6>;
	237	clock-frequency = <100000>;
	238	};
	239
	240	i2c3: i2c@58783000 {
	241	compatible = "socionext,uniphier-fi2c";
	242	status = "disabled";
	243	reg = <0x58783000 0x80>;
	244	#address-cells = <1>;
	245	#size-cells = <0>;
	246	interrupts = <0 44 4>;
	247	pinctrl-names = "default";
	248	pinctrl-0 = <&pinctrl_i2c3>;
	249	clocks = <&peri_clk 7>;
	250	clock-frequency = <100000>;
	251	};
	252
	253	/* chip-internal connection for HDMI */
	254	i2c6: i2c@58786000 {
	255	compatible = "socionext,uniphier-fi2c";
	256	reg = <0x58786000 0x80>;
	257	#address-cells = <1>;
	258	#size-cells = <0>;
	259	interrupts = <0 26 4>;
	260	clocks = <&peri_clk 10>;
	261	clock-frequency = <400000>;
	262	};
	263
	264	system_bus: system-bus@58c00000 {
	265	compatible = "socionext,uniphier-system-bus";
	266	status = "disabled";
	267	reg = <0x58c00000 0x400>;
	268	#address-cells = <2>;
	269	#size-cells = <1>;
	270	pinctrl-names = "default";
	271	pinctrl-0 = <&pinctrl_system_bus>;
	272	};
	273
abb6ac25	274	smpctrl@59801000 {
61e6cc0a MY	275	compatible = "socionext,uniphier-smpctrl";
	276	reg = <0x59801000 0x400>;
	277	};
	278
	279	sdctrl@59810000 {
	280	compatible = "socionext,uniphier-pxs3-sdctrl",
	281	"simple-mfd", "syscon";
31c86aa7	282	reg = <0x59810000 0x400>;
61e6cc0a MY	283
	284	sd_clk: clock {
	285	compatible = "socionext,uniphier-pxs3-sd-clock";
	286	#clock-cells = <1>;
	287	};
	288
	289	sd_rst: reset {
	290	compatible = "socionext,uniphier-pxs3-sd-reset";
	291	#reset-cells = <1>;
	292	};
	293	};
	294
	295	perictrl@59820000 {
	296	compatible = "socionext,uniphier-pxs3-perictrl",
	297	"simple-mfd", "syscon";
	298	reg = <0x59820000 0x200>;
	299
	300	peri_clk: clock {
	301	compatible = "socionext,uniphier-pxs3-peri-clock";
	302	#clock-cells = <1>;
	303	};
	304
	305	peri_rst: reset {
	306	compatible = "socionext,uniphier-pxs3-peri-reset";
	307	#reset-cells = <1>;
	308	};
	309	};
	310
	311	emmc: sdhc@5a000000 {
	312	compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
61e6cc0a MY	313	reg = <0x5a000000 0x400>;
	314	interrupts = <0 78 4>;
	315	pinctrl-names = "default";
	316	pinctrl-0 = <&pinctrl_emmc_1v8>;
	317	clocks = <&sys_clk 4>;
	318	bus-width = <8>;
	319	mmc-ddr-1_8v;
	320	mmc-hs200-1_8v;
31c86aa7 MY	321	cdns,phy-input-delay-legacy = <4>;
	322	cdns,phy-input-delay-mmc-highspeed = <2>;
	323	cdns,phy-input-delay-mmc-ddr = <3>;
	324	cdns,phy-dll-delay-sdclk = <21>;
	325	cdns,phy-dll-delay-sdclk-hsmmc = <21>;
61e6cc0a MY	326	};
	327
	328	sd: sdhc@5a400000 {
	329	compatible = "socionext,uniphier-sdhc";
	330	status = "disabled";
	331	reg = <0x5a400000 0x800>;
	332	interrupts = <0 76 4>;
	333	pinctrl-names = "default";
	334	pinctrl-0 = <&pinctrl_sd>;
	335	clocks = <&sd_clk 0>;
	336	reset-names = "host";
	337	resets = <&sd_rst 0>;
	338	bus-width = <4>;
	339	cap-sd-highspeed;
	340	};
	341
	342	soc-glue@5f800000 {
	343	compatible = "socionext,uniphier-pxs3-soc-glue",
	344	"simple-mfd", "syscon";
	345	reg = <0x5f800000 0x2000>;
	346
	347	pinctrl: pinctrl {
	348	compatible = "socionext,uniphier-pxs3-pinctrl";
	349	};
	350	};
	351
31c86aa7 MY	352	aidet: aidet@5fc20000 {
31c86aa7 MY	353	compatible = "socionext,uniphier-pxs3-aidet";
61e6cc0a	354	reg = <0x5fc20000 0x200>;
31c86aa7 MY	355	interrupt-controller;
31c86aa7 MY	356	#interrupt-cells = <2>;
61e6cc0a MY	357	};
	358
	359	gic: interrupt-controller@5fe00000 {
	360	compatible = "arm,gic-v3";
	361	reg = <0x5fe00000 0x10000>, /* GICD */
	362	<0x5fe80000 0x80000>; /* GICR */
	363	interrupt-controller;
	364	#interrupt-cells = <3>;
	365	interrupts = <1 9 4>;
	366	};
	367
	368	sysctrl@61840000 {
	369	compatible = "socionext,uniphier-pxs3-sysctrl",
	370	"simple-mfd", "syscon";
	371	reg = <0x61840000 0x10000>;
	372
	373	sys_clk: clock {
	374	compatible = "socionext,uniphier-pxs3-clock";
	375	#clock-cells = <1>;
	376	};
	377
	378	sys_rst: reset {
	379	compatible = "socionext,uniphier-pxs3-reset";
	380	#reset-cells = <1>;
	381	};
31c86aa7 MY	382
	383	watchdog {
	384	compatible = "socionext,uniphier-wdt";
	385	};
	386	};
	387
	388	usb0: usb@65b00000 {
	389	compatible = "socionext,uniphier-pxs3-dwc3";
	390	status = "disabled";
	391	reg = <0x65b00000 0x1000>;
	392	#address-cells = <1>;
	393	#size-cells = <1>;
	394	ranges;
	395	pinctrl-names = "default";
	396	pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
	397	dwc3@65a00000 {
	398	compatible = "snps,dwc3";
	399	reg = <0x65a00000 0x10000>;
	400	interrupts = <0 134 4>;
	401	dr_mode = "host";
	402	tx-fifo-resize;
	403	};
	404	};
	405
	406	usb1: usb@65d00000 {
	407	compatible = "socionext,uniphier-pxs3-dwc3";
	408	status = "disabled";
	409	reg = <0x65d00000 0x1000>;
	410	#address-cells = <1>;
	411	#size-cells = <1>;
	412	ranges;
	413	pinctrl-names = "default";
	414	pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
	415	dwc3@65c00000 {
	416	compatible = "snps,dwc3";
	417	reg = <0x65c00000 0x10000>;
	418	interrupts = <0 137 4>;
	419	dr_mode = "host";
	420	tx-fifo-resize;
	421	};
61e6cc0a MY	422	};
	423
	424	nand: nand@68000000 {
31c86aa7	425	compatible = "socionext,uniphier-denali-nand-v5b";
61e6cc0a MY	426	status = "disabled";
	427	reg-names = "nand_data", "denali_reg";
	428	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	429	interrupts = <0 65 4>;
	430	pinctrl-names = "default";
	431	pinctrl-0 = <&pinctrl_nand>;
	432	clocks = <&sys_clk 2>;
61e6cc0a MY	433	};
	434	};
	435	};
	436
31c86aa7	437	#include "uniphier-pinctrl.dtsi"