[people/ms/u-boot.git] / arch / arm / dts / zynq-7000.dtsi

/*
 * Xilinx Zynq 7000 DTSI
 * Describes the hardware common to all Zynq 7000-based boards.
 *
 *  Copyright (C) 2011 - 2015 Xilinx
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "xlnx,zynq-7000";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			clocks = <&clkc 3>;
			clock-latency = <1000>;
			cpu0-supply = <&regulator_vccpint>;
			operating-points = <
				/* kHz    uV */
				666667  1000000
				333334  1000000
			>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			clocks = <&clkc 3>;
		};
	};

	fpga_full: fpga-full {
		compatible = "fpga-region";
		fpga-mgr = <&devcfg>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
	};

	pmu@f8891000 {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 5 4>, <0 6 4>;
		interrupt-parent = <&intc>;
		reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
	};

	regulator_vccpint: fixedregulator {
		compatible = "regulator-fixed";
		regulator-name = "VCCPINT";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	amba: amba {
		u-boot,dm-pre-reloc;
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		adc: adc@f8007100 {
			compatible = "xlnx,zynq-xadc-1.00.a";
			reg = <0xf8007100 0x20>;
			interrupts = <0 7 4>;
			interrupt-parent = <&intc>;
			clocks = <&clkc 12>;
		};

		can0: can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <&clkc 19>, <&clkc 36>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0 28 4>;
			interrupt-parent = <&intc>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		can1: can@e0009000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <&clkc 20>, <&clkc 37>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0009000 0x1000>;
			interrupts = <0 51 4>;
			interrupt-parent = <&intc>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		gpio0: gpio@e000a000 {
			compatible = "xlnx,zynq-gpio-1.0";
			#gpio-cells = <2>;
			clocks = <&clkc 42>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupts = <0 20 4>;
			reg = <0xe000a000 0x1000>;
		};

		i2c0: i2c@e0004000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <&clkc 38>;
			interrupt-parent = <&intc>;
			interrupts = <0 25 4>;
			reg = <0xe0004000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@e0005000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <&clkc 39>;
			interrupt-parent = <&intc>;
			interrupts = <0 48 4>;
			reg = <0xe0005000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0xF8F01000 0x1000>,
			      <0xF8F00100 0x100>;
		};

		L2: cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xF8F02000 0x1000>;
			interrupts = <0 2 4>;
			arm,data-latency = <3 2 2>;
			arm,tag-latency = <2 2 2>;
			cache-unified;
			cache-level = <2>;
		};

		mc: memory-controller@f8006000 {
			compatible = "xlnx,zynq-ddrc-a05";
			reg = <0xf8006000 0x1000>;
		};

		uart0: serial@e0000000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "disabled";
			clocks = <&clkc 23>, <&clkc 40>;
			clock-names = "uart_clk", "pclk";
			reg = <0xE0000000 0x1000>;
			interrupts = <0 27 4>;
		};

		uart1: serial@e0001000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "disabled";
			clocks = <&clkc 24>, <&clkc 41>;
			clock-names = "uart_clk", "pclk";
			reg = <0xE0001000 0x1000>;
			interrupts = <0 50 4>;
		};

		spi0: spi@e0006000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0006000 0x1000>;
			status = "disabled";
			interrupt-parent = <&intc>;
			interrupts = <0 26 4>;
			clocks = <&clkc 25>, <&clkc 34>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@e0007000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0007000 0x1000>;
			status = "disabled";
			interrupt-parent = <&intc>;
			interrupts = <0 49 4>;
			clocks = <&clkc 26>, <&clkc 35>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		qspi: spi@e000d000 {
			clock-names = "ref_clk", "pclk";
			clocks = <&clkc 10>, <&clkc 43>;
			compatible = "xlnx,zynq-qspi-1.0";
			status = "disabled";
			interrupt-parent = <&intc>;
			interrupts = <0 19 4>;
			reg = <0xe000d000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem0: ethernet@e000b000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000b000 0x1000>;
			status = "disabled";
			interrupts = <0 22 4>;
			clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem1: ethernet@e000c000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000c000 0x1000>;
			status = "disabled";
			interrupts = <0 45 4>;
			clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		sdhci0: sdhci@e0100000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&clkc 21>, <&clkc 32>;
			interrupt-parent = <&intc>;
			interrupts = <0 24 4>;
			reg = <0xe0100000 0x1000>;
		};

		sdhci1: sdhci@e0101000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&clkc 22>, <&clkc 33>;
			interrupt-parent = <&intc>;
			interrupts = <0 47 4>;
			reg = <0xe0101000 0x1000>;
		};

		slcr: slcr@f8000000 {
			u-boot,dm-pre-reloc;
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
			reg = <0xF8000000 0x1000>;
			ranges;
			clkc: clkc@100 {
				u-boot,dm-pre-reloc;
				#clock-cells = <1>;
				compatible = "xlnx,ps7-clkc";
				fclk-enable = <0>;
				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
						"gem1_aper", "sdio0_aper", "sdio1_aper",
						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
						"dbg_trc", "dbg_apb";
				reg = <0x100 0x100>;
			};

			rstc: rstc@200 {
				compatible = "xlnx,zynq-reset";
				reg = <0x200 0x48>;
				#reset-cells = <1>;
				syscon = <&slcr>;
			};

			pinctrl0: pinctrl@700 {
				compatible = "xlnx,pinctrl-zynq";
				reg = <0x700 0x200>;
				syscon = <&slcr>;
			};
		};

		dmac_s: dmac@f8003000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xf8003000 0x1000>;
			interrupt-parent = <&intc>;
			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
				"dma4", "dma5", "dma6", "dma7";
			interrupts = <0 13 4>,
			             <0 14 4>, <0 15 4>,
			             <0 16 4>, <0 17 4>,
			             <0 40 4>, <0 41 4>,
			             <0 42 4>, <0 43 4>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <4>;
			clocks = <&clkc 27>;
			clock-names = "apb_pclk";
		};

		devcfg: devcfg@f8007000 {
			compatible = "xlnx,zynq-devcfg-1.0";
			interrupt-parent = <&intc>;
			interrupts = <0 8 4>;
			reg = <0xf8007000 0x100>;
			clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
			syscon = <&slcr>;
		};

		global_timer: timer@f8f00200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xf8f00200 0x20>;
			interrupts = <1 11 0x301>;
			interrupt-parent = <&intc>;
			clocks = <&clkc 4>;
		};

		ttc0: timer@f8001000 {
			interrupt-parent = <&intc>;
			interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
			compatible = "cdns,ttc";
			clocks = <&clkc 6>;
			reg = <0xF8001000 0x1000>;
		};

		ttc1: timer@f8002000 {
			interrupt-parent = <&intc>;
			interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
			compatible = "cdns,ttc";
			clocks = <&clkc 6>;
			reg = <0xF8002000 0x1000>;
		};

		scutimer: timer@f8f00600 {
			interrupt-parent = <&intc>;
			interrupts = <1 13 0x301>;
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xf8f00600 0x20>;
			clocks = <&clkc 4>;
		};

		usb0: usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <&clkc 28>;
			interrupt-parent = <&intc>;
			interrupts = <0 21 4>;
			reg = <0xe0002000 0x1000>;
			phy_type = "ulpi";
		};

		usb1: usb@e0003000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <&clkc 29>;
			interrupt-parent = <&intc>;
			interrupts = <0 44 4>;
			reg = <0xe0003000 0x1000>;
			phy_type = "ulpi";
		};

		watchdog0: watchdog@f8005000 {
			clocks = <&clkc 45>;
			compatible = "cdns,wdt-r1p2";
			interrupt-parent = <&intc>;
			interrupts = <0 9 1>;
			reg = <0xf8005000 0x1000>;
			timeout-sec = <10>;
		};
	};
};
Commit	Line	Data
f8f36c5d JT	1	/*
	2	* Xilinx Zynq 7000 DTSI
	3	* Describes the hardware common to all Zynq 7000-based boards.
	4	*
05e7ca63	5	* Copyright (C) 2011 - 2015 Xilinx
f8f36c5d JT	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
f8f36c5d JT	9
f8f36c5d JT	10	/ {
cc7978be MS	11	#address-cells = <1>;
cc7978be MS	12	#size-cells = <1>;
f8f36c5d	13	compatible = "xlnx,zynq-7000";
580a54c5 MY	14
	15	cpus {
	16	#address-cells = <1>;
	17	#size-cells = <0>;
	18
720ba46e	19	cpu0: cpu@0 {
580a54c5 MY	20	compatible = "arm,cortex-a9";
	21	device_type = "cpu";
	22	reg = <0>;
	23	clocks = <&clkc 3>;
	24	clock-latency = <1000>;
bece06ce	25	cpu0-supply = <&regulator_vccpint>;
580a54c5 MY	26	operating-points = <
	27	/* kHz uV */
	28	666667 1000000
	29	333334 1000000
580a54c5 MY	30	>;
	31	};
	32
720ba46e	33	cpu1: cpu@1 {
580a54c5 MY	34	compatible = "arm,cortex-a9";
	35	device_type = "cpu";
	36	reg = <1>;
	37	clocks = <&clkc 3>;
	38	};
	39	};
	40
0b180d02 MS	41	fpga_full: fpga-full {
	42	compatible = "fpga-region";
	43	fpga-mgr = <&devcfg>;
	44	#address-cells = <1>;
	45	#size-cells = <1>;
	46	ranges;
	47	};
	48
cc7978be	49	pmu@f8891000 {
580a54c5 MY	50	compatible = "arm,cortex-a9-pmu";
	51	interrupts = <0 5 4>, <0 6 4>;
	52	interrupt-parent = <&intc>;
	53	reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
	54	};
	55
cc7978be	56	regulator_vccpint: fixedregulator {
bece06ce MS	57	compatible = "regulator-fixed";
	58	regulator-name = "VCCPINT";
	59	regulator-min-microvolt = <1000000>;
	60	regulator-max-microvolt = <1000000>;
	61	regulator-boot-on;
	62	regulator-always-on;
	63	};
	64
461c3888	65	amba: amba {
035c6b27	66	u-boot,dm-pre-reloc;
580a54c5 MY	67	compatible = "simple-bus";
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	interrupt-parent = <&intc>;
	71	ranges;
	72
fb1a5061 MS	73	adc: adc@f8007100 {
	74	compatible = "xlnx,zynq-xadc-1.00.a";
	75	reg = <0xf8007100 0x20>;
	76	interrupts = <0 7 4>;
	77	interrupt-parent = <&intc>;
	78	clocks = <&clkc 12>;
	79	};
	80
	81	can0: can@e0008000 {
	82	compatible = "xlnx,zynq-can-1.0";
	83	status = "disabled";
	84	clocks = <&clkc 19>, <&clkc 36>;
	85	clock-names = "can_clk", "pclk";
	86	reg = <0xe0008000 0x1000>;
	87	interrupts = <0 28 4>;
	88	interrupt-parent = <&intc>;
	89	tx-fifo-depth = <0x40>;
	90	rx-fifo-depth = <0x40>;
	91	};
	92
	93	can1: can@e0009000 {
	94	compatible = "xlnx,zynq-can-1.0";
	95	status = "disabled";
	96	clocks = <&clkc 20>, <&clkc 37>;
	97	clock-names = "can_clk", "pclk";
	98	reg = <0xe0009000 0x1000>;
	99	interrupts = <0 51 4>;
	100	interrupt-parent = <&intc>;
	101	tx-fifo-depth = <0x40>;
	102	rx-fifo-depth = <0x40>;
	103	};
	104
	105	gpio0: gpio@e000a000 {
	106	compatible = "xlnx,zynq-gpio-1.0";
	107	#gpio-cells = <2>;
	108	clocks = <&clkc 42>;
	109	gpio-controller;
58fab4cd	110	interrupt-controller;
534f7e02	111	#interrupt-cells = <2>;
fb1a5061 MS	112	interrupt-parent = <&intc>;
	113	interrupts = <0 20 4>;
	114	reg = <0xe000a000 0x1000>;
	115	};
	116
a0cb47f1	117	i2c0: i2c@e0004000 {
580a54c5 MY	118	compatible = "cdns,i2c-r1p10";
	119	status = "disabled";
	120	clocks = <&clkc 38>;
	121	interrupt-parent = <&intc>;
	122	interrupts = <0 25 4>;
	123	reg = <0xe0004000 0x1000>;
	124	#address-cells = <1>;
	125	#size-cells = <0>;
	126	};
	127
a0cb47f1	128	i2c1: i2c@e0005000 {
580a54c5 MY	129	compatible = "cdns,i2c-r1p10";
	130	status = "disabled";
	131	clocks = <&clkc 39>;
	132	interrupt-parent = <&intc>;
	133	interrupts = <0 48 4>;
	134	reg = <0xe0005000 0x1000>;
	135	#address-cells = <1>;
	136	#size-cells = <0>;
	137	};
	138
	139	intc: interrupt-controller@f8f01000 {
	140	compatible = "arm,cortex-a9-gic";
	141	#interrupt-cells = <3>;
580a54c5 MY	142	interrupt-controller;
	143	reg = <0xF8F01000 0x1000>,
	144	<0xF8F00100 0x100>;
	145	};
	146
a0cb47f1	147	L2: cache-controller@f8f02000 {
580a54c5 MY	148	compatible = "arm,pl310-cache";
580a54c5 MY	149	reg = <0xF8F02000 0x1000>;
d50cb3d6	150	interrupts = <0 2 4>;
580a54c5 MY	151	arm,data-latency = <3 2 2>;
	152	arm,tag-latency = <2 2 2>;
	153	cache-unified;
	154	cache-level = <2>;
	155	};
	156
fb1a5061 MS	157	mc: memory-controller@f8006000 {
	158	compatible = "xlnx,zynq-ddrc-a05";
	159	reg = <0xf8006000 0x1000>;
	160	};
	161
a0cb47f1	162	uart0: serial@e0000000 {
8a8c46a6	163	compatible = "xlnx,xuartps", "cdns,uart-r1p8";
580a54c5 MY	164	status = "disabled";
580a54c5 MY	165	clocks = <&clkc 23>, <&clkc 40>;
8a8c46a6	166	clock-names = "uart_clk", "pclk";
580a54c5 MY	167	reg = <0xE0000000 0x1000>;
	168	interrupts = <0 27 4>;
	169	};
	170
a0cb47f1	171	uart1: serial@e0001000 {
8a8c46a6	172	compatible = "xlnx,xuartps", "cdns,uart-r1p8";
580a54c5 MY	173	status = "disabled";
580a54c5 MY	174	clocks = <&clkc 24>, <&clkc 41>;
8a8c46a6	175	clock-names = "uart_clk", "pclk";
580a54c5 MY	176	reg = <0xE0001000 0x1000>;
	177	interrupts = <0 50 4>;
	178	};
	179
a8a8fc9c	180	spi0: spi@e0006000 {
40b383fa	181	compatible = "xlnx,zynq-spi-r1p6";
a8a8fc9c JT	182	reg = <0xe0006000 0x1000>;
	183	status = "disabled";
	184	interrupt-parent = <&intc>;
	185	interrupts = <0 26 4>;
	186	clocks = <&clkc 25>, <&clkc 34>;
	187	clock-names = "ref_clk", "pclk";
	188	#address-cells = <1>;
	189	#size-cells = <0>;
	190	};
	191
	192	spi1: spi@e0007000 {
40b383fa	193	compatible = "xlnx,zynq-spi-r1p6";
a8a8fc9c JT	194	reg = <0xe0007000 0x1000>;
	195	status = "disabled";
	196	interrupt-parent = <&intc>;
	197	interrupts = <0 49 4>;
	198	clocks = <&clkc 26>, <&clkc 35>;
	199	clock-names = "ref_clk", "pclk";
	200	#address-cells = <1>;
	201	#size-cells = <0>;
	202	};
	203
70676cb3 JT	204	qspi: spi@e000d000 {
	205	clock-names = "ref_clk", "pclk";
	206	clocks = <&clkc 10>, <&clkc 43>;
	207	compatible = "xlnx,zynq-qspi-1.0";
	208	status = "disabled";
	209	interrupt-parent = <&intc>;
	210	interrupts = <0 19 4>;
	211	reg = <0xe000d000 0x1000>;
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214	};
	215
580a54c5	216	gem0: ethernet@e000b000 {
7e163363	217	compatible = "cdns,zynq-gem", "cdns,gem";
08305feb	218	reg = <0xe000b000 0x1000>;
580a54c5 MY	219	status = "disabled";
	220	interrupts = <0 22 4>;
	221	clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
	222	clock-names = "pclk", "hclk", "tx_clk";
5ee236a3 MS	223	#address-cells = <1>;
5ee236a3 MS	224	#size-cells = <0>;
580a54c5 MY	225	};
	226
	227	gem1: ethernet@e000c000 {
7e163363	228	compatible = "cdns,zynq-gem", "cdns,gem";
08305feb	229	reg = <0xe000c000 0x1000>;
580a54c5 MY	230	status = "disabled";
	231	interrupts = <0 45 4>;
	232	clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
	233	clock-names = "pclk", "hclk", "tx_clk";
5ee236a3 MS	234	#address-cells = <1>;
5ee236a3 MS	235	#size-cells = <0>;
580a54c5 MY	236	};
580a54c5 MY	237
a0cb47f1	238	sdhci0: sdhci@e0100000 {
580a54c5 MY	239	compatible = "arasan,sdhci-8.9a";
	240	status = "disabled";
	241	clock-names = "clk_xin", "clk_ahb";
	242	clocks = <&clkc 21>, <&clkc 32>;
	243	interrupt-parent = <&intc>;
	244	interrupts = <0 24 4>;
	245	reg = <0xe0100000 0x1000>;
e5c343dd	246	};
580a54c5	247
a0cb47f1	248	sdhci1: sdhci@e0101000 {
580a54c5 MY	249	compatible = "arasan,sdhci-8.9a";
	250	status = "disabled";
	251	clock-names = "clk_xin", "clk_ahb";
	252	clocks = <&clkc 22>, <&clkc 33>;
	253	interrupt-parent = <&intc>;
	254	interrupts = <0 47 4>;
	255	reg = <0xe0101000 0x1000>;
e5c343dd	256	};
580a54c5 MY	257
580a54c5 MY	258	slcr: slcr@f8000000 {
781745bd	259	u-boot,dm-pre-reloc;
580a54c5 MY	260	#address-cells = <1>;
580a54c5 MY	261	#size-cells = <1>;
621a93e1	262	compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
580a54c5 MY	263	reg = <0xF8000000 0x1000>;
	264	ranges;
	265	clkc: clkc@100 {
781745bd	266	u-boot,dm-pre-reloc;
580a54c5 MY	267	#clock-cells = <1>;
580a54c5 MY	268	compatible = "xlnx,ps7-clkc";
580a54c5 MY	269	fclk-enable = <0>;
	270	clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
	271	"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
	272	"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
	273	"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
	274	"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
	275	"dma", "usb0_aper", "usb1_aper", "gem0_aper",
	276	"gem1_aper", "sdio0_aper", "sdio1_aper",
	277	"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
	278	"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
	279	"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
	280	"dbg_trc", "dbg_apb";
	281	reg = <0x100 0x100>;
	282	};
e913ce2a	283
4c987271 MF	284	rstc: rstc@200 {
	285	compatible = "xlnx,zynq-reset";
	286	reg = <0x200 0x48>;
	287	#reset-cells = <1>;
	288	syscon = <&slcr>;
	289	};
	290
e913ce2a MS	291	pinctrl0: pinctrl@700 {
	292	compatible = "xlnx,pinctrl-zynq";
	293	reg = <0x700 0x200>;
	294	syscon = <&slcr>;
	295	};
580a54c5 MY	296	};
580a54c5 MY	297
fb1a5061 MS	298	dmac_s: dmac@f8003000 {
	299	compatible = "arm,pl330", "arm,primecell";
	300	reg = <0xf8003000 0x1000>;
	301	interrupt-parent = <&intc>;
	302	interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
	303	"dma4", "dma5", "dma6", "dma7";
	304	interrupts = <0 13 4>,
	305	<0 14 4>, <0 15 4>,
	306	<0 16 4>, <0 17 4>,
	307	<0 40 4>, <0 41 4>,
	308	<0 42 4>, <0 43 4>;
	309	#dma-cells = <1>;
	310	#dma-channels = <8>;
	311	#dma-requests = <4>;
	312	clocks = <&clkc 27>;
	313	clock-names = "apb_pclk";
	314	};
	315
	316	devcfg: devcfg@f8007000 {
	317	compatible = "xlnx,zynq-devcfg-1.0";
77bb73de MS	318	interrupt-parent = <&intc>;
77bb73de MS	319	interrupts = <0 8 4>;
fb1a5061	320	reg = <0xf8007000 0x100>;
77bb73de MS	321	clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
77bb73de MS	322	clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
20fe3f17	323	syscon = <&slcr>;
fb1a5061 MS	324	};
fb1a5061 MS	325
580a54c5 MY	326	global_timer: timer@f8f00200 {
	327	compatible = "arm,cortex-a9-global-timer";
	328	reg = <0xf8f00200 0x20>;
	329	interrupts = <1 11 0x301>;
	330	interrupt-parent = <&intc>;
	331	clocks = <&clkc 4>;
	332	};
	333
a0cb47f1	334	ttc0: timer@f8001000 {
580a54c5	335	interrupt-parent = <&intc>;
b346bd1d	336	interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
580a54c5 MY	337	compatible = "cdns,ttc";
	338	clocks = <&clkc 6>;
	339	reg = <0xF8001000 0x1000>;
	340	};
	341
a0cb47f1	342	ttc1: timer@f8002000 {
580a54c5	343	interrupt-parent = <&intc>;
b346bd1d	344	interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
580a54c5 MY	345	compatible = "cdns,ttc";
	346	clocks = <&clkc 6>;
	347	reg = <0xF8002000 0x1000>;
	348	};
fb1a5061	349
a0cb47f1	350	scutimer: timer@f8f00600 {
580a54c5	351	interrupt-parent = <&intc>;
e5c343dd	352	interrupts = <1 13 0x301>;
580a54c5	353	compatible = "arm,cortex-a9-twd-timer";
e5c343dd	354	reg = <0xf8f00600 0x20>;
580a54c5	355	clocks = <&clkc 4>;
e5c343dd	356	};
fb1a5061 MS	357
	358	usb0: usb@e0002000 {
	359	compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
	360	status = "disabled";
	361	clocks = <&clkc 28>;
	362	interrupt-parent = <&intc>;
	363	interrupts = <0 21 4>;
	364	reg = <0xe0002000 0x1000>;
	365	phy_type = "ulpi";
	366	};
	367
	368	usb1: usb@e0003000 {
	369	compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
	370	status = "disabled";
	371	clocks = <&clkc 29>;
	372	interrupt-parent = <&intc>;
	373	interrupts = <0 44 4>;
	374	reg = <0xe0003000 0x1000>;
	375	phy_type = "ulpi";
	376	};
	377
	378	watchdog0: watchdog@f8005000 {
	379	clocks = <&clkc 45>;
	380	compatible = "cdns,wdt-r1p2";
	381	interrupt-parent = <&intc>;
	382	interrupts = <0 9 1>;
	383	reg = <0xf8005000 0x1000>;
	384	timeout-sec = <10>;
	385	};
580a54c5	386	};
f8f36c5d	387	};