[people/ms/u-boot.git] / arch / arm / dts / zynqmp-zcu102-revB.dts

/*
 * dts file for Xilinx ZynqMP ZCU102 RevB
 *
 * (C) Copyright 2016, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "zynqmp-zcu102-revA.dts"

/ {
	model = "ZynqMP ZCU102 RevB";
	compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};

&gem3 {
	phy-handle = <&phyc>;
	phyc: phy@c {
		reg = <0xc>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
	};
	/* Cleanup from RevA */
	/delete-node/ phy@21;
};

/* Different qspi 512Mbit version */

/* Fix collision with u61 */
&i2c0 {
	i2cswitch@75 {
		i2c@2 {
			max15303@1b { /* u8 */
				compatible = "max15303";
				reg = <0x1b>;
			};
			/delete-node/ max15303@20;
		};
	};
};
Commit	Line	Data
1f4f3d33 MS	1	/*
	2	* dts file for Xilinx ZynqMP ZCU102 RevB
	3	*
	4	* (C) Copyright 2016, Xilinx, Inc.
	5	*
	6	* Michal Simek <michal.simek@xilinx.com>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
be463451	11	#include "zynqmp-zcu102-revA.dts"
1f4f3d33 MS	12
	13	/ {
	14	model = "ZynqMP ZCU102 RevB";
582ee924	15	compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
1f4f3d33 MS	16	};
	17
	18	&gem3 {
	19	phy-handle = <&phyc>;
	20	phyc: phy@c {
	21	reg = <0xc>;
	22	ti,rx-internal-delay = <0x8>;
	23	ti,tx-internal-delay = <0xa>;
	24	ti,fifo-depth = <0x1>;
	25	};
	26	/* Cleanup from RevA */
	27	/delete-node/ phy@21;
	28	};
	29
	30	/* Different qspi 512Mbit version */
	31
	32	/* Fix collision with u61 */
	33	&i2c0 {
	34	i2cswitch@75 {
	35	i2c@2 {
	36	max15303@1b { /* u8 */
	37	compatible = "max15303";
	38	reg = <0x1b>;
	39	};
	40	/delete-node/ max15303@20;
	41	};
	42	};
	43	};