[people/ms/u-boot.git] / arch / arm / imx-common / cpu.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <bootm.h>
#include <common.h>
#include <netdev.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <imx_thermal.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>

#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)
static u32 reset_cause = -1;

static char *get_reset_cause(void)
{
	u32 cause;
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;

	cause = readl(&src_regs->srsr);
	writel(cause, &src_regs->srsr);
	reset_cause = cause;

	switch (cause) {
	case 0x00001:
	case 0x00011:
		return "POR";
	case 0x00004:
		return "CSU";
	case 0x00008:
		return "IPP USER";
	case 0x00010:
#ifdef	CONFIG_MX7
		return "WDOG1";
#else
		return "WDOG";
#endif
	case 0x00020:
		return "JTAG HIGH-Z";
	case 0x00040:
		return "JTAG SW";
	case 0x00080:
		return "WDOG3";
#ifdef CONFIG_MX7
	case 0x00100:
		return "WDOG4";
	case 0x00200:
		return "TEMPSENSE";
#else
	case 0x00100:
		return "TEMPSENSE";
	case 0x10000:
		return "WARM BOOT";
#endif
	default:
		return "unknown reset";
	}
}

u32 get_imx_reset_cause(void)
{
	return reset_cause;
}
#endif

#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE	ESDCTL_BASE_ADDR
#else
#define MEMCTL_BASE	MMDC_P0_BASE_ADDR
#endif
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};

/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
	uint32_t	ctl;
	uint32_t	pdc;
	uint32_t	otc;
	uint32_t	cfg0;
	uint32_t	cfg1;
	uint32_t	cfg2;
	uint32_t	misc;
};

#define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
#define ESD_MMDC_CTL_GET_COLUMN(mdctl)	((ctl >> 20) & 7)
#define ESD_MMDC_CTL_GET_WIDTH(mdctl)	((ctl >> 16) & 3)
#define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)

/*
 * imx_ddr_size - return size in bytes of DRAM according MMDC config
 * The MMDC MDCTL register holds the number of bits for row, col, and data
 * width and the MMDC MDMISC register holds the number of banks. Combine
 * all these bits to determine the meme size the MMDC has been configured for
 */
unsigned imx_ddr_size(void)
{
	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
	unsigned ctl = readl(&mem->ctl);
	unsigned misc = readl(&mem->misc);
	int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */

	bits += ESD_MMDC_CTL_GET_ROW(ctl);
	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
	bits += ESD_MMDC_CTL_GET_CS1(ctl);

	/* The MX6 can do only 3840 MiB of DRAM */
	if (bits == 32)
		return 0xf0000000;

	return 1 << bits;
}
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)

const char *get_imx_type(u32 imxtype)
{
	switch (imxtype) {
	case MXC_CPU_MX7S:
		return "7S";	/* Single-core version of the mx7 */
	case MXC_CPU_MX7D:
		return "7D";	/* Dual-core version of the mx7 */
	case MXC_CPU_MX6QP:
		return "6QP";	/* Quad-Plus version of the mx6 */
	case MXC_CPU_MX6DP:
		return "6DP";	/* Dual-Plus version of the mx6 */
	case MXC_CPU_MX6Q:
		return "6Q";	/* Quad-core version of the mx6 */
	case MXC_CPU_MX6D:
		return "6D";	/* Dual-core version of the mx6 */
	case MXC_CPU_MX6DL:
		return "6DL";	/* Dual Lite version of the mx6 */
	case MXC_CPU_MX6SOLO:
		return "6SOLO";	/* Solo version of the mx6 */
	case MXC_CPU_MX6SL:
		return "6SL";	/* Solo-Lite version of the mx6 */
	case MXC_CPU_MX6SLL:
		return "6SLL";	/* SLL version of the mx6 */
	case MXC_CPU_MX6SX:
		return "6SX";   /* SoloX version of the mx6 */
	case MXC_CPU_MX6UL:
		return "6UL";   /* Ultra-Lite version of the mx6 */
	case MXC_CPU_MX6ULL:
		return "6ULL";	/* ULL version of the mx6 */
	case MXC_CPU_MX51:
		return "51";
	case MXC_CPU_MX53:
		return "53";
	default:
		return "??";
	}
}

int print_cpuinfo(void)
{
	u32 cpurev;
	__maybe_unused u32 max_freq;

	cpurev = get_cpu_rev();

#if defined(CONFIG_IMX_THERMAL)
	struct udevice *thermal_dev;
	int cpu_tmp, minc, maxc, ret;

	printf("CPU:   Freescale i.MX%s rev%d.%d",
	       get_imx_type((cpurev & 0xFF000) >> 12),
	       (cpurev & 0x000F0) >> 4,
	       (cpurev & 0x0000F) >> 0);
	max_freq = get_cpu_speed_grade_hz();
	if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
		printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	} else {
		printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
		       mxc_get_clock(MXC_ARM_CLK) / 1000000);
	}
#else
	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
		get_imx_type((cpurev & 0xFF000) >> 12),
		(cpurev & 0x000F0) >> 4,
		(cpurev & 0x0000F) >> 0,
		mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif

#if defined(CONFIG_IMX_THERMAL)
	puts("CPU:   ");
	switch (get_cpu_temp_grade(&minc, &maxc)) {
	case TEMP_AUTOMOTIVE:
		puts("Automotive temperature grade ");
		break;
	case TEMP_INDUSTRIAL:
		puts("Industrial temperature grade ");
		break;
	case TEMP_EXTCOMMERCIAL:
		puts("Extended Commercial temperature grade ");
		break;
	default:
		puts("Commercial temperature grade ");
		break;
	}
	printf("(%dC to %dC)", minc, maxc);
	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	if (!ret) {
		ret = thermal_get_temp(thermal_dev, &cpu_tmp);

		if (!ret)
			printf(" at %dC\n", cpu_tmp);
		else
			debug(" - invalid sensor data\n");
	} else {
		debug(" - invalid sensor device\n");
	}
#endif

	printf("Reset cause: %s\n", get_reset_cause());
	return 0;
}
#endif

int cpu_eth_init(bd_t *bis)
{
	int rc = -ENODEV;

#if defined(CONFIG_FEC_MXC)
	rc = fecmxc_initialize(bis);
#endif

	return rc;
}

#ifdef CONFIG_FSL_ESDHC
/*
 * Initializes on-chip MMC controllers.
 * to override, implement board_mmc_init()
 */
int cpu_mmc_init(bd_t *bis)
{
	return fsl_esdhc_mmc_init(bis);
}
#endif

#ifndef CONFIG_MX7
u32 get_ahb_clk(void)
{
	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, ahb_podf;

	reg = __raw_readl(&imx_ccm->cbcdr);
	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;

	return get_periph_clk() / (ahb_podf + 1);
}
#endif

void arch_preboot_os(void)
{
#if defined(CONFIG_CMD_SATA)
	sata_stop();
#if defined(CONFIG_MX6)
	disable_sata_clock();
#endif
#endif
#if defined(CONFIG_VIDEO_IPUV3)
	/* disable video before launching O/S */
	ipuv3_fb_shutdown();
#endif
#if defined(CONFIG_VIDEO_MXS)
	lcdif_power_down();
#endif
}

void set_chipselect_size(int const cs_size)
{
	unsigned int reg;
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	reg = readl(&iomuxc_regs->gpr[1]);

	switch (cs_size) {
	case CS0_128:
		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
		reg |= 0x5;
		break;
	case CS0_64M_CS1_64M:
		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
		reg |= 0x1B;
		break;
	case CS0_64M_CS1_32M_CS2_32M:
		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
		reg |= 0x4B;
		break;
	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
		reg |= 0x249;
		break;
	default:
		printf("Unknown chip select size: %d\n", cs_size);
		break;
	}

	writel(reg, &iomuxc_regs->gpr[1]);
}
Commit	Line	Data
18936ee2 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
18936ee2 JL	8	*/
18936ee2 JL	9
5624c6bd	10	#include <bootm.h>
18936ee2	11	#include <common.h>
5624c6bd	12	#include <netdev.h>
1221ce45	13	#include <linux/errno.h>
18936ee2 JL	14	#include <asm/io.h>
	15	#include <asm/arch/imx-regs.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/sys_proto.h>
6a376046	18	#include <asm/arch/crm_regs.h>
70caa8e2	19	#include <imx_thermal.h>
e1eb75b5	20	#include <ipu_pixfmt.h>
7a264168	21	#include <thermal.h>
44b9841d	22	#include <sata.h>
18936ee2 JL	23
	24	#ifdef CONFIG_FSL_ESDHC
	25	#include <fsl_esdhc.h>
	26	#endif
	27
28420e78	28	#if defined(CONFIG_DISPLAY_CPUINFO)
11c2e505 EN	29	static u32 reset_cause = -1;
	30
	31	static char *get_reset_cause(void)
18936ee2 JL	32	{
	33	u32 cause;
	34	struct src src_regs = (struct src )SRC_BASE_ADDR;
	35
	36	cause = readl(&src_regs->srsr);
	37	writel(cause, &src_regs->srsr);
11c2e505	38	reset_cause = cause;
18936ee2 JL	39
	40	switch (cause) {
	41	case 0x00001:
cece2622	42	case 0x00011:
18936ee2 JL	43	return "POR";
	44	case 0x00004:
	45	return "CSU";
	46	case 0x00008:
	47	return "IPP USER";
	48	case 0x00010:
cd562c8d AA	49	#ifdef CONFIG_MX7
	50	return "WDOG1";
	51	#else
18936ee2	52	return "WDOG";
cd562c8d	53	#endif
18936ee2 JL	54	case 0x00020:
	55	return "JTAG HIGH-Z";
	56	case 0x00040:
	57	return "JTAG SW";
cd562c8d AA	58	case 0x00080:
	59	return "WDOG3";
	60	#ifdef CONFIG_MX7
	61	case 0x00100:
	62	return "WDOG4";
	63	case 0x00200:
	64	return "TEMPSENSE";
	65	#else
	66	case 0x00100:
	67	return "TEMPSENSE";
18936ee2 JL	68	case 0x10000:
18936ee2 JL	69	return "WARM BOOT";
cd562c8d	70	#endif
18936ee2 JL	71	default:
	72	return "unknown reset";
	73	}
	74	}
	75
11c2e505 EN	76	u32 get_imx_reset_cause(void)
	77	{
	78	return reset_cause;
	79	}
28420e78	80	#endif
11c2e505	81
eb0344d9 TK	82	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
eb0344d9 TK	83	#if defined(CONFIG_MX53)
3e9cbbbb	84	#define MEMCTL_BASE ESDCTL_BASE_ADDR
eb0344d9	85	#else
3e9cbbbb	86	#define MEMCTL_BASE MMDC_P0_BASE_ADDR
eb0344d9 TK	87	#endif
	88	static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
	89	static const unsigned char bank_lookup[] = {3, 2};
	90
b07161c3	91	/* these MMDC registers are common to the IMX53 and IMX6 */
eb0344d9 TK	92	struct esd_mmdc_regs {
	93	uint32_t ctl;
	94	uint32_t pdc;
	95	uint32_t otc;
	96	uint32_t cfg0;
	97	uint32_t cfg1;
	98	uint32_t cfg2;
	99	uint32_t misc;
eb0344d9 TK	100	};
	101
	102	#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
	103	#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
	104	#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
	105	#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
	106	#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
	107
b07161c3 TH	108	/*
	109	* imx_ddr_size - return size in bytes of DRAM according MMDC config
	110	* The MMDC MDCTL register holds the number of bits for row, col, and data
	111	* width and the MMDC MDMISC register holds the number of banks. Combine
	112	* all these bits to determine the meme size the MMDC has been configured for
	113	*/
eb0344d9 TK	114	unsigned imx_ddr_size(void)
	115	{
	116	struct esd_mmdc_regs mem = (struct esd_mmdc_regs )MEMCTL_BASE;
	117	unsigned ctl = readl(&mem->ctl);
	118	unsigned misc = readl(&mem->misc);
	119	int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
	120
	121	bits += ESD_MMDC_CTL_GET_ROW(ctl);
	122	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
	123	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
	124	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
	125	bits += ESD_MMDC_CTL_GET_CS1(ctl);
fcfdfdd5 MV	126
	127	/* The MX6 can do only 3840 MiB of DRAM */
	128	if (bits == 32)
	129	return 0xf0000000;
	130
eb0344d9 TK	131	return 1 << bits;
	132	}
	133	#endif
	134
18936ee2	135	#if defined(CONFIG_DISPLAY_CPUINFO)
a7683867	136
20332a06	137	const char *get_imx_type(u32 imxtype)
a7683867 FE	138	{
a7683867 FE	139	switch (imxtype) {
e25a0656	140	case MXC_CPU_MX7S:
249092fa	141	return "7S"; /* Single-core version of the mx7 */
cd562c8d AA	142	case MXC_CPU_MX7D:
cd562c8d AA	143	return "7D"; /* Dual-core version of the mx7 */
d0acd993 PF	144	case MXC_CPU_MX6QP:
	145	return "6QP"; /* Quad-Plus version of the mx6 */
	146	case MXC_CPU_MX6DP:
	147	return "6DP"; /* Dual-Plus version of the mx6 */
20332a06	148	case MXC_CPU_MX6Q:
a7683867	149	return "6Q"; /* Quad-core version of the mx6 */
94db6655 FE	150	case MXC_CPU_MX6D:
94db6655 FE	151	return "6D"; /* Dual-core version of the mx6 */
20332a06 TK	152	case MXC_CPU_MX6DL:
	153	return "6DL"; /* Dual Lite version of the mx6 */
	154	case MXC_CPU_MX6SOLO:
	155	return "6SOLO"; /* Solo version of the mx6 */
	156	case MXC_CPU_MX6SL:
a7683867	157	return "6SL"; /* Solo-Lite version of the mx6 */
7ce6d3c8 PF	158	case MXC_CPU_MX6SLL:
7ce6d3c8 PF	159	return "6SLL"; /* SLL version of the mx6 */
05d54b82 FE	160	case MXC_CPU_MX6SX:
05d54b82 FE	161	return "6SX"; /* SoloX version of the mx6 */
8631c06e PF	162	case MXC_CPU_MX6UL:
8631c06e PF	163	return "6UL"; /* Ultra-Lite version of the mx6 */
65ce54be PF	164	case MXC_CPU_MX6ULL:
65ce54be PF	165	return "6ULL"; /* ULL version of the mx6 */
20332a06	166	case MXC_CPU_MX51:
a7683867	167	return "51";
20332a06	168	case MXC_CPU_MX53:
a7683867 FE	169	return "53";
a7683867 FE	170	default:
e972d72b	171	return "??";
a7683867 FE	172	}
	173	}
	174
18936ee2 JL	175	int print_cpuinfo(void)
18936ee2 JL	176	{
943a3f2c SB	177	u32 cpurev;
943a3f2c SB	178	__maybe_unused u32 max_freq;
18936ee2	179
1368f993 AA	180	cpurev = get_cpu_rev();
	181
	182	#if defined(CONFIG_IMX_THERMAL)
7a264168	183	struct udevice *thermal_dev;
70caa8e2	184	int cpu_tmp, minc, maxc, ret;
a7683867	185
b83ddac8 TH	186	printf("CPU: Freescale i.MX%s rev%d.%d",
	187	get_imx_type((cpurev & 0xFF000) >> 12),
	188	(cpurev & 0x000F0) >> 4,
	189	(cpurev & 0x0000F) >> 0);
	190	max_freq = get_cpu_speed_grade_hz();
	191	if (!max_freq \|\| max_freq == mxc_get_clock(MXC_ARM_CLK)) {
	192	printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	193	} else {
	194	printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
	195	mxc_get_clock(MXC_ARM_CLK) / 1000000);
	196	}
	197	#else
a7683867 FE	198	printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
a7683867 FE	199	get_imx_type((cpurev & 0xFF000) >> 12),
18936ee2 JL	200	(cpurev & 0x000F0) >> 4,
	201	(cpurev & 0x0000F) >> 0,
	202	mxc_get_clock(MXC_ARM_CLK) / 1000000);
b83ddac8	203	#endif
7a264168	204
1368f993	205	#if defined(CONFIG_IMX_THERMAL)
70caa8e2 TH	206	puts("CPU: ");
	207	switch (get_cpu_temp_grade(&minc, &maxc)) {
	208	case TEMP_AUTOMOTIVE:
	209	puts("Automotive temperature grade ");
	210	break;
	211	case TEMP_INDUSTRIAL:
	212	puts("Industrial temperature grade ");
	213	break;
	214	case TEMP_EXTCOMMERCIAL:
	215	puts("Extended Commercial temperature grade ");
	216	break;
	217	default:
	218	puts("Commercial temperature grade ");
	219	break;
	220	}
	221	printf("(%dC to %dC)", minc, maxc);
7a264168 YL	222	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	223	if (!ret) {
	224	ret = thermal_get_temp(thermal_dev, &cpu_tmp);
	225
	226	if (!ret)
70caa8e2	227	printf(" at %dC\n", cpu_tmp);
7a264168	228	else
3a384b49	229	debug(" - invalid sensor data\n");
7a264168	230	} else {
3a384b49	231	debug(" - invalid sensor device\n");
7a264168 YL	232	}
	233	#endif
	234
18936ee2 JL	235	printf("Reset cause: %s\n", get_reset_cause());
	236	return 0;
	237	}
	238	#endif
	239
	240	int cpu_eth_init(bd_t *bis)
	241	{
	242	int rc = -ENODEV;
	243
	244	#if defined(CONFIG_FEC_MXC)
	245	rc = fecmxc_initialize(bis);
	246	#endif
	247
	248	return rc;
	249	}
	250
ecb0f317	251	#ifdef CONFIG_FSL_ESDHC
18936ee2 JL	252	/*
	253	* Initializes on-chip MMC controllers.
	254	* to override, implement board_mmc_init()
	255	*/
	256	int cpu_mmc_init(bd_t *bis)
	257	{
18936ee2	258	return fsl_esdhc_mmc_init(bis);
18936ee2	259	}
ecb0f317	260	#endif
18936ee2	261
cd562c8d	262	#ifndef CONFIG_MX7
6a376046 FE	263	u32 get_ahb_clk(void)
	264	{
	265	struct mxc_ccm_reg imx_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	266	u32 reg, ahb_podf;
	267
	268	reg = __raw_readl(&imx_ccm->cbcdr);
	269	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	270	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
	271
	272	return get_periph_clk() / (ahb_podf + 1);
	273	}
cd562c8d	274	#endif
e1eb75b5	275
e1eb75b5 EN	276	void arch_preboot_os(void)
e1eb75b5 EN	277	{
44b9841d NK	278	#if defined(CONFIG_CMD_SATA)
44b9841d NK	279	sata_stop();
dd1c8f1b SM	280	#if defined(CONFIG_MX6)
	281	disable_sata_clock();
	282	#endif
44b9841d NK	283	#endif
44b9841d NK	284	#if defined(CONFIG_VIDEO_IPUV3)
e1eb75b5 EN	285	/* disable video before launching O/S */
e1eb75b5 EN	286	ipuv3_fb_shutdown();
e1eb75b5	287	#endif
623787fd PF	288	#if defined(CONFIG_VIDEO_MXS)
	289	lcdif_power_down();
	290	#endif
44b9841d	291	}
32c81ea6 FE	292
	293	void set_chipselect_size(int const cs_size)
	294	{
	295	unsigned int reg;
	296	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	297	reg = readl(&iomuxc_regs->gpr[1]);
	298
	299	switch (cs_size) {
	300	case CS0_128:
	301	reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
	302	reg \|= 0x5;
	303	break;
	304	case CS0_64M_CS1_64M:
	305	reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
	306	reg \|= 0x1B;
	307	break;
	308	case CS0_64M_CS1_32M_CS2_32M:
	309	reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
	310	reg \|= 0x4B;
	311	break;
	312	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
	313	reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
	314	reg \|= 0x249;
	315	break;
	316	default:
	317	printf("Unknown chip select size: %d\n", cs_size);
	318	break;
	319	}
	320
	321	writel(reg, &iomuxc_regs->gpr[1]);
	322	}