[people/ms/u-boot.git] / arch / arm / include / asm / arch-am33xx / clock.h

/*
 * clock.h
 *
 * clock header
 *
 * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CLOCKS_H_
#define _CLOCKS_H_

#include <asm/arch/clocks_am33xx.h>

#ifdef CONFIG_TI81XX
#include <asm/arch/clock_ti81xx.h>
#endif

#define LDELAY 1000000

/*CM_<clock_domain>__CLKCTRL */
#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
#define CD_CLKCTRL_CLKTRCTRL_MASK		3

#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2

/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
#define MODULE_CLKCTRL_MODULEMODE_MASK		3
#define MODULE_CLKCTRL_IDLEST_SHIFT		16
#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)

#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2

#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
#define MODULE_CLKCTRL_IDLEST_IDLE		2
#define MODULE_CLKCTRL_IDLEST_DISABLED		3

/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_SSC_EN_SHIFT		12
#define CM_CLKMODE_DPLL_SSC_EN_MASK		(1 << 12)
#define CM_CLKMODE_DPLL_SSC_ACK_MASK		(1 << 13)
#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK	(1 << 14)
#define CM_CLKMODE_DPLL_SSC_TYPE_MASK		(1 << 15)
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
#define CM_CLKMODE_DPLL_EN_SHIFT		0
#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)

#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7

#define DPLL_EN_STOP			1
#define DPLL_EN_MN_BYPASS		4
#define DPLL_EN_LOW_POWER_BYPASS	5
#define DPLL_EN_LOCK			7

/* CM_IDLEST_DPLL fields */
#define ST_DPLL_CLK_MASK		1

/* CM_CLKSEL_DPLL */
#define CM_CLKSEL_DPLL_M_SHIFT			8
#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
#define CM_CLKSEL_DPLL_N_SHIFT			0
#define CM_CLKSEL_DPLL_N_MASK			0x7F

struct dpll_params {
	u32 m;
	u32 n;
	s8 m2;
	s8 m3;
	s8 m4;
	s8 m5;
	s8 m6;
};

struct dpll_regs {
	u32 cm_clkmode_dpll;
	u32 cm_idlest_dpll;
	u32 cm_autoidle_dpll;
	u32 cm_clksel_dpll;
	u32 cm_div_m2_dpll;
	u32 cm_div_m3_dpll;
	u32 cm_div_m4_dpll;
	u32 cm_div_m5_dpll;
	u32 cm_div_m6_dpll;
};

extern const struct dpll_regs dpll_mpu_regs;
extern const struct dpll_regs dpll_core_regs;
extern const struct dpll_regs dpll_per_regs;
extern const struct dpll_regs dpll_ddr_regs;

extern struct cm_wkuppll *const cmwkup;

const struct dpll_params *get_dpll_mpu_params(void);
const struct dpll_params *get_dpll_core_params(void);
const struct dpll_params *get_dpll_per_params(void);
const struct dpll_params *get_dpll_ddr_params(void);
void scale_vcores(void);
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
void prcm_init(void);
void enable_basic_clocks(void);
void do_enable_clocks(u32 *const *, u32 *const *, u8);
void do_disable_clocks(u32 *const *, u32 *const *, u8);

void set_mpu_spreadspectrum(int permille);
#endif
Commit	Line	Data
f87fa62a CN	1	/*
	2	* clock.h
	3	*
	4	* clock header
	5	*
b43c17cb	6	* Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
f87fa62a	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
f87fa62a CN	9	*/
	10
	11	#ifndef _CLOCKS_H_
	12	#define _CLOCKS_H_
	13
	14	#include <asm/arch/clocks_am33xx.h>
	15
dcf846d5 TA	16	#ifdef CONFIG_TI81XX
	17	#include <asm/arch/clock_ti81xx.h>
	18	#endif
	19
94d77fb6 LV	20	#define LDELAY 1000000
94d77fb6 LV	21
95cb69fa LV	22	/CM_<clock_domain>__CLKCTRL /
	23	#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
	24	#define CD_CLKCTRL_CLKTRCTRL_MASK 3
	25
	26	#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
	27	#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
	28	#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
	29
	30	/* CM_<clock_domain>_<module>_CLKCTRL */
	31	#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
	32	#define MODULE_CLKCTRL_MODULEMODE_MASK 3
	33	#define MODULE_CLKCTRL_IDLEST_SHIFT 16
	34	#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
	35
	36	#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
	37	#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
	38
	39	#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
	40	#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
	41	#define MODULE_CLKCTRL_IDLEST_IDLE 2
	42	#define MODULE_CLKCTRL_IDLEST_DISABLED 3
	43
94d77fb6	44	/* CM_CLKMODE_DPLL */
4b97bcbe YY	45	#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
4b97bcbe YY	46	#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
c01bc75e HS	47	#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13)
	48	#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
	49	#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15)
94d77fb6 LV	50	#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
	51	#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
	52	#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
	53	#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
	54	#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
	55	#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
	56	#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
	57	#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
	58	#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
	59	#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
	60	#define CM_CLKMODE_DPLL_EN_SHIFT 0
	61	#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
	62
	63	#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
	64	#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
	65
	66	#define DPLL_EN_STOP 1
	67	#define DPLL_EN_MN_BYPASS 4
	68	#define DPLL_EN_LOW_POWER_BYPASS 5
	69	#define DPLL_EN_LOCK 7
	70
	71	/* CM_IDLEST_DPLL fields */
	72	#define ST_DPLL_CLK_MASK 1
	73
	74	/* CM_CLKSEL_DPLL */
	75	#define CM_CLKSEL_DPLL_M_SHIFT 8
	76	#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
	77	#define CM_CLKSEL_DPLL_N_SHIFT 0
	78	#define CM_CLKSEL_DPLL_N_MASK 0x7F
	79
	80	struct dpll_params {
	81	u32 m;
	82	u32 n;
	83	s8 m2;
	84	s8 m3;
	85	s8 m4;
	86	s8 m5;
	87	s8 m6;
	88	};
	89
	90	struct dpll_regs {
	91	u32 cm_clkmode_dpll;
	92	u32 cm_idlest_dpll;
	93	u32 cm_autoidle_dpll;
	94	u32 cm_clksel_dpll;
	95	u32 cm_div_m2_dpll;
	96	u32 cm_div_m3_dpll;
	97	u32 cm_div_m4_dpll;
	98	u32 cm_div_m5_dpll;
	99	u32 cm_div_m6_dpll;
	100	};
	101
	102	extern const struct dpll_regs dpll_mpu_regs;
	103	extern const struct dpll_regs dpll_core_regs;
	104	extern const struct dpll_regs dpll_per_regs;
	105	extern const struct dpll_regs dpll_ddr_regs;
94d77fb6	106
95cb69fa	107	extern struct cm_wkuppll *const cmwkup;
94d77fb6	108
cf04d032 LV	109	const struct dpll_params *get_dpll_mpu_params(void);
	110	const struct dpll_params *get_dpll_core_params(void);
	111	const struct dpll_params *get_dpll_per_params(void);
94d77fb6	112	const struct dpll_params *get_dpll_ddr_params(void);
64ce2fbd	113	void scale_vcores(void);
94d77fb6	114	void do_setup_dpll(const struct dpll_regs , const struct dpll_params );
95cb69fa LV	115	void prcm_init(void);
	116	void enable_basic_clocks(void);
	117	void do_enable_clocks(u32 const , u32 const , u8);
fca45722	118	void do_disable_clocks(u32 const , u32 const , u8);
94d77fb6	119
694607b5	120	void set_mpu_spreadspectrum(int permille);
f87fa62a	121	#endif