projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5655108a CN |
1 | /* |
| 2 | * hardware.h | |
| 3 | * | |
| 4 | * hardware specific header | |
| 5 | * | |
| 3ba65f97 | 6 | * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ |
| 5655108a CN |
7 | * |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | */ | |
| 18 | ||
| 19 | #ifndef __AM33XX_HARDWARE_H | |
| 20 | #define __AM33XX_HARDWARE_H | |
| 21 | ||
| 8b029f22 | 22 | #include <config.h> |
| 41aebf81 | 23 | #include <asm/arch/omap.h> |
| 3ba65f97 MP |
24 | #ifdef CONFIG_AM33XX |
| 25 | #include <asm/arch/hardware_am33xx.h> | |
| 26 | #elif defined(CONFIG_TI814X) | |
| 27 | #include <asm/arch/hardware_ti814x.h> | |
| 28 | #endif | |
| 41aebf81 | 29 | |
| 8b029f22 MP |
30 | /* |
| 31 | * Common hardware definitions | |
| 32 | */ | |
| 5655108a CN |
33 | |
| 34 | /* DM Timer base addresses */ | |
| 35 | #define DM_TIMER0_BASE 0x4802C000 | |
| 36 | #define DM_TIMER1_BASE 0x4802E000 | |
| 37 | #define DM_TIMER2_BASE 0x48040000 | |
| 38 | #define DM_TIMER3_BASE 0x48042000 | |
| 39 | #define DM_TIMER4_BASE 0x48044000 | |
| 40 | #define DM_TIMER5_BASE 0x48046000 | |
| 41 | #define DM_TIMER6_BASE 0x48048000 | |
| 42 | #define DM_TIMER7_BASE 0x4804A000 | |
| 43 | ||
| 44 | /* GPIO Base address */ | |
| 45 | #define GPIO0_BASE 0x48032000 | |
| 46 | #define GPIO1_BASE 0x4804C000 | |
| 5655108a CN |
47 | |
| 48 | /* BCH Error Location Module */ | |
| 49 | #define ELM_BASE 0x48080000 | |
| 50 | ||
| 5655108a CN |
51 | /* EMIF Base address */ |
| 52 | #define EMIF4_0_CFG_BASE 0x4C000000 | |
| 53 | #define EMIF4_1_CFG_BASE 0x4D000000 | |
| 5655108a CN |
54 | |
| 55 | /* PLL related registers */ | |
| 56 | #define CM_PER 0x44E00000 | |
| 57 | #define CM_WKUP 0x44E00400 | |
| 58 | #define CM_DPLL 0x44E00500 | |
| 59 | #define CM_DEVICE 0x44E00700 | |
| 000820b5 | 60 | #define CM_RTC 0x44E00800 |
| 5655108a CN |
61 | #define CM_CEFUSE 0x44E00A00 |
| 62 | #define PRM_DEVICE 0x44E00F00 | |
| 63 | ||
| 64 | /* VTP Base address */ | |
| 3ba65f97 | 65 | #define VTP1_CTRL_ADDR 0x48140E10 |
| 5655108a CN |
66 | |
| 67 | /* DDR Base address */ | |
| 68 | #define DDR_CTRL_ADDR 0x44E10E04 | |
| 69 | #define DDR_CONTROL_BASE_ADDR 0x44E11404 | |
| 3ba65f97 MP |
70 | #define DDR_PHY_CMD_ADDR2 0x47C0C800 |
| 71 | #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 | |
| 5655108a CN |
72 | |
| 73 | /* UART */ | |
| 74 | #define DEFAULT_UART_BASE UART0_BASE | |
| 75 | ||
| 76 | #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) | |
| 77 | #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE | |
| 78 | ||
| 8eb16b7f IY |
79 | /* GPMC Base address */ |
| 80 | #define GPMC_BASE 0x50000000 | |
| 81 | ||
| e79cd8eb | 82 | /* CPSW Config space */ |
| 81df2bab | 83 | #define CPSW_BASE 0x4A100000 |
| 000820b5 | 84 | |
| 7df5cf35 | 85 | /* OTG */ |
| 81df2bab MP |
86 | #define USB0_OTG_BASE 0x47401000 |
| 87 | #define USB1_OTG_BASE 0x47401800 | |
| 7df5cf35 | 88 | |
| 5655108a | 89 | #endif /* __AM33XX_HARDWARE_H */ |