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1 | /* |
2 | * linux/include/asm-arm/arch-netarm/netarm_registers.h | |
3 | * | |
3df5bea0 WD |
4 | * Copyright (C) 2005 |
5 | * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> | |
6 | * | |
2d1a537d WD |
7 | * Copyright (C) 2000, 2001 NETsilicon, Inc. |
8 | * Copyright (C) 2000, 2001 WireSpeed Communications Corporation | |
9 | * | |
10 | * This software is copyrighted by WireSpeed. LICENSEE agrees that | |
11 | * it will not delete this copyright notice, trademarks or protective | |
12 | * notices from any copy made by LICENSEE. | |
13 | * | |
14 | * This software is provided "AS-IS" and any express or implied | |
15 | * warranties or conditions, including but not limited to any | |
16 | * implied warranties of merchantability and fitness for a particular | |
17 | * purpose regarding this software. In no event shall WireSpeed | |
18 | * be liable for any indirect, consequential, or incidental damages, | |
19 | * loss of profits or revenue, loss of use or data, or interruption | |
20 | * of business, whether the alleged damages are labeled in contract, | |
21 | * tort, or indemnity. | |
22 | * | |
23 | * This program is free software; you can redistribute it and/or modify | |
24 | * it under the terms of the GNU General Public License as published by | |
25 | * the Free Software Foundation; either version 2 of the License, or | |
26 | * (at your option) any later version. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
31 | * | |
32 | * author(s) : Joe deBlaquiere | |
3df5bea0 WD |
33 | * |
34 | * Modified to support NS7520 by Art Shipkowski. | |
2d1a537d WD |
35 | */ |
36 | ||
37 | #ifndef __NET_ARM_REGISTERS_H | |
38 | #define __NET_ARM_REGISTERS_H | |
39 | ||
40 | #include <config.h> | |
41 | ||
42 | /* fundamental constants : */ | |
43 | /* the input crystal/clock frequency ( in Hz ) */ | |
44 | #define NETARM_XTAL_FREQ_25MHz (18432000) | |
45 | #define NETARM_XTAL_FREQ_33MHz (23698000) | |
3df5bea0 WD |
46 | #define NETARM_XTAL_FREQ_48MHz (48000000) |
47 | #define NETARM_XTAL_FREQ_55MHz (55000000) | |
2d1a537d WD |
48 | #define NETARM_XTAL_FREQ_EMLIN1 (20000000) |
49 | ||
50 | /* the frequency of SYS_CLK */ | |
51 | #if defined(CONFIG_NETARM_EMLIN) | |
52 | ||
53 | /* EMLIN board: 33 MHz (exp.) */ | |
54 | #define NETARM_PLL_COUNT_VAL 6 | |
55 | #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz | |
56 | ||
57 | #elif defined(CONFIG_NETARM_NET40_REV2) | |
58 | ||
59 | /* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ | |
60 | #define NETARM_PLL_COUNT_VAL 6 | |
61 | #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz | |
62 | ||
63 | #elif defined(CONFIG_NETARM_NET40_REV4) | |
64 | ||
65 | /* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with | |
66 | NETARM_XTAL_FREQ_25MHz) 4 */ | |
67 | #define NETARM_PLL_COUNT_VAL 4 | |
68 | #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz | |
69 | ||
3df5bea0 | 70 | #elif defined(CONFIG_NETARM_NET50) |
2d1a537d WD |
71 | |
72 | /* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ | |
73 | #define NETARM_PLL_COUNT_VAL 8 | |
74 | #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz | |
75 | ||
3df5bea0 WD |
76 | #else /* CONFIG_NETARM_NS7520 */ |
77 | ||
78 | #define NETARM_PLL_COUNT_VAL 0 | |
79 | ||
80 | #if defined(CONFIG_BOARD_UNC20) | |
81 | #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz | |
82 | #else | |
83 | #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz | |
84 | #endif | |
85 | ||
2d1a537d WD |
86 | #endif |
87 | ||
88 | /* #include "arm_registers.h" */ | |
89 | #include <asm/arch/netarm_gen_module.h> | |
90 | #include <asm/arch/netarm_mem_module.h> | |
91 | #include <asm/arch/netarm_ser_module.h> | |
92 | #include <asm/arch/netarm_eni_module.h> | |
93 | #include <asm/arch/netarm_dma_module.h> | |
94 | #include <asm/arch/netarm_eth_module.h> | |
95 | ||
96 | #endif |