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| Commit | Line | Data |
|---|---|---|
| 51100cfc AB |
1 | /* |
| 2 | * (C) Copyright 2011 | |
| 3 | * eInfochips Ltd. <www.einfochips.com> | |
| 4 | * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> | |
| 5 | * | |
| 6 | * (C) Copyright 2010 | |
| 7 | * Marvell Semiconductor <www.marvell.com> | |
| 8 | * | |
| 1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 51100cfc AB |
10 | */ |
| 11 | ||
| 12 | #ifndef __ARMADA100_SPI_H_ | |
| 13 | #define __ARMADA100_SPI_H_ | |
| 14 | ||
| 15 | #include <asm/arch/armada100.h> | |
| 16 | ||
| 17 | #define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE | |
| 18 | #define SSP_REG_BASE(x) CAT_BASE_ADDR(x) | |
| 19 | ||
| 20 | /* | |
| 21 | * SSP Serial Port Registers | |
| 22 | * refer Appendix A.26 | |
| 23 | */ | |
| 24 | struct ssp_reg { | |
| 25 | u32 sscr0; /* SSP Control Register 0 - 0x000 */ | |
| 26 | u32 sscr1; /* SSP Control Register 1 - 0x004 */ | |
| 27 | u32 sssr; /* SSP Status Register - 0x008 */ | |
| 28 | u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ | |
| 29 | u32 ssdr; /* SSP Data Register - 0x010 */ | |
| 30 | u32 pad1[5]; | |
| 31 | u32 ssto; /* SSP Timeout Register - 0x028 */ | |
| 32 | u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ | |
| 33 | u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ | |
| 34 | u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ | |
| 35 | u32 sstss; /* SSP Timeslot Status Register - 0x038 */ | |
| 36 | }; | |
| 37 | ||
| 38 | #define DEFAULT_WORD_LEN 8 | |
| 39 | #define SSP_FLUSH_NUM 0x2000 | |
| 40 | #define RX_THRESH_DEF 8 | |
| 41 | #define TX_THRESH_DEF 8 | |
| 42 | #define TIMEOUT_DEF 1000 | |
| 43 | ||
| 44 | #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ | |
| 45 | #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ | |
| 46 | #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ | |
| 47 | #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity | |
| 48 | setting */ | |
| 49 | #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ | |
| 50 | #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ | |
| 51 | #define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ | |
| 52 | #define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ | |
| 53 | ||
| 54 | #define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ | |
| 55 | #define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ | |
| 56 | #define SSCR1_TINTE (1 << 19) /* Receiver Time-out | |
| 57 | Interrupt enable */ | |
| 58 | ||
| 59 | #define SSCR0_DSS 0x0f /* Data Size Select (mask) */ | |
| 60 | #define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ | |
| 61 | #define SSCR0_FRF 0x30 /* FRame Format (mask) */ | |
| 62 | #define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial | |
| 63 | Peripheral Interface */ | |
| 64 | #define SSCR0_TI (0x1 << 4) /* TI's Synchronous | |
| 65 | Serial Protocol (SSP) */ | |
| 66 | #define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ | |
| 67 | #define SSCR0_ECS (1 << 6) /* External clock select */ | |
| 68 | #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port | |
| 69 | Enable */ | |
| 70 | ||
| 71 | #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ | |
| 72 | #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ | |
| 73 | #define SSSR_BSY (1 << 4) /* SSP Busy */ | |
| 74 | #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ | |
| 75 | #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ | |
| 76 | #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ | |
| 77 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ | |
| 78 | ||
| 79 | #endif /* __ARMADA100_SPI_H_ */ |