[people/ms/u-boot.git] / arch / arm / include / asm / arch-at91 / at91_pio.h

/*
 * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
 *
 * Copyright (C) 2005 Ivan Kokshaysky
 * Copyright (C) SAN People
 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
 *
 * Parallel I/O Controller (PIO) - System peripherals registers.
 * Based on AT91RM9200 datasheet revision E.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef AT91_PIO_H
#define AT91_PIO_H


#define AT91_ASM_PIO_RANGE	0x200
#define AT91_ASM_PIOC_ASR	\
	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
#define AT91_ASM_PIOC_BSR	\
	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
#define AT91_ASM_PIOC_PDR	\
	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
#define AT91_ASM_PIOC_PUDR	\
	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)

#define AT91_ASM_PIOD_PDR	\
	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
#define AT91_ASM_PIOD_PUDR	\
	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
#define AT91_ASM_PIOD_ASR	\
	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)

#ifndef __ASSEMBLY__

typedef struct at91_port {
	u32	per;		/* 0x00 PIO Enable Register */
	u32	pdr;		/* 0x04 PIO Disable Register */
	u32	psr;		/* 0x08 PIO Status Register */
	u32	reserved0;
	u32	oer;		/* 0x10 Output Enable Register */
	u32	odr;		/* 0x14 Output Disable Registerr */
	u32	osr;		/* 0x18 Output Status Register */
	u32	reserved1;
	u32	ifer;		/* 0x20 Input Filter Enable Register */
	u32	ifdr;		/* 0x24 Input Filter Disable Register */
	u32	ifsr;		/* 0x28 Input Filter Status Register */
	u32	reserved2;
	u32	sodr;		/* 0x30 Set Output Data Register */
	u32	codr;		/* 0x34 Clear Output Data Register */
	u32	odsr;		/* 0x38 Output Data Status Register */
	u32	pdsr;		/* 0x3C Pin Data Status Register */
	u32	ier;		/* 0x40 Interrupt Enable Register */
	u32	idr;		/* 0x44 Interrupt Disable Register */
	u32	imr;		/* 0x48 Interrupt Mask Register */
	u32	isr;		/* 0x4C Interrupt Status Register */
	u32	mder;		/* 0x50 Multi-driver Enable Register */
	u32	mddr;		/* 0x54 Multi-driver Disable Register */
	u32	mdsr;		/* 0x58 Multi-driver Status Register */
	u32	reserved3;
	u32	pudr;		/* 0x60 Pull-up Disable Register */
	u32	puer;		/* 0x64 Pull-up Enable Register */
	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
	u32	reserved4;
#if defined(CPU_HAS_PIO3)
	u32	abcdsr1;	/* 0x70 Peripheral ABCD Select Register 1 */
	u32	abcdsr2;	/* 0x74 Peripheral ABCD Select Register 2 */
	u32	reserved5[2];
	u32	ifscdr;		/* 0x80 Input Filter SCLK Disable Register */
	u32	ifscer;		/* 0x84 Input Filter SCLK Enable Register */
	u32	ifscsr;		/* 0x88 Input Filter SCLK Status Register */
	u32	scdr;		/* 0x8C SCLK Divider Debouncing Register */
	u32	ppddr;		/* 0x90 Pad Pull-down Disable Register */
	u32	ppder;		/* 0x94 Pad Pull-down Enable Register */
	u32	ppdsr;		/* 0x98 Pad Pull-down Status Register */
	u32	reserved6;	/*  */
#else
	u32	asr;		/* 0x70 Select A Register */
	u32	bsr;		/* 0x74 Select B Register */
	u32	absr;		/* 0x78 AB Select Status Register */
	u32	reserved5[9];	/*  */
#endif
	u32	ower;		/* 0xA0 Output Write Enable Register */
	u32	owdr;		/* 0xA4 Output Write Disable Register */
	u32	owsr;		/* OxA8 Output Write Status Register */
#if defined(CPU_HAS_PIO3)
	u32	reserved7;	/*  */
	u32	aimer;		/* 0xB0 Additional INT Modes Enable Register */
	u32	aimdr;		/* 0xB4 Additional INT Modes Disable Register */
	u32	aimmr;		/* 0xB8 Additional INT Modes Mask Register */
	u32	reserved8;	/* */
	u32	esr;		/* 0xC0 Edge Select Register */
	u32	lsr;		/* 0xC4 Level Select Register */
	u32	elsr;		/* 0xC8 Edge/Level Status Register */
	u32	reserved9;	/* 0xCC */
	u32	fellsr;		/* 0xD0 Falling /Low Level Select Register */
	u32	rehlsr;		/* 0xD4 Rising /High Level Select Register */
	u32	frlhsr;		/* 0xD8 Fall/Rise - Low/High Status Register */
	u32	reserved10;	/* */
	u32	locksr;		/* 0xE0 Lock Status */
	u32	wpmr;		/* 0xE4 Write Protect Mode Register */
	u32	wpsr;		/* 0xE8 Write Protect Status Register */
	u32	reserved11[5];	/* */
	u32	schmitt;	/* 0x100 Schmitt Trigger Register */
	u32	reserved12[63];
#else
	u32	reserved6[85];
#endif
} at91_port_t;

typedef union at91_pio {
	struct {
		at91_port_t	pioa;
		at91_port_t	piob;
		at91_port_t	pioc;
	#if (ATMEL_PIO_PORTS > 3)
		at91_port_t	piod;
	#endif
	#if (ATMEL_PIO_PORTS > 4)
		at91_port_t	pioe;
	#endif
	} ;
	at91_port_t port[ATMEL_PIO_PORTS];
} at91_pio_t;

#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
#if defined(CPU_HAS_PIO3)
int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);
int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
int at91_set_pio_value(unsigned port, unsigned pin, int value);
int at91_get_pio_value(unsigned port, unsigned pin);
#endif
#endif

#define	AT91_PIO_PORTA		0x0
#define	AT91_PIO_PORTB		0x1
#define	AT91_PIO_PORTC		0x2
#define	AT91_PIO_PORTD		0x3
#define	AT91_PIO_PORTE		0x4

#ifdef CONFIG_AT91_LEGACY

#define PIO_PER		0x00	/* Enable Register */
#define PIO_PDR		0x04	/* Disable Register */
#define PIO_PSR		0x08	/* Status Register */
#define PIO_OER		0x10	/* Output Enable Register */
#define PIO_ODR		0x14	/* Output Disable Register */
#define PIO_OSR		0x18	/* Output Status Register */
#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
#define PIO_SODR	0x30	/* Set Output Data Register */
#define PIO_CODR	0x34	/* Clear Output Data Register */
#define PIO_ODSR	0x38	/* Output Data Status Register */
#define PIO_PDSR	0x3c	/* Pin Data Status Register */
#define PIO_IER		0x40	/* Interrupt Enable Register */
#define PIO_IDR		0x44	/* Interrupt Disable Register */
#define PIO_IMR		0x48	/* Interrupt Mask Register */
#define PIO_ISR		0x4c	/* Interrupt Status Register */
#define PIO_MDER	0x50	/* Multi-driver Enable Register */
#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
#define PIO_MDSR	0x58	/* Multi-driver Status Register */
#define PIO_PUDR	0x60	/* Pull-up Disable Register */
#define PIO_PUER	0x64	/* Pull-up Enable Register */
#define PIO_PUSR	0x68	/* Pull-up Status Register */
#define PIO_ASR		0x70	/* Peripheral A Select Register */
#define PIO_BSR		0x74	/* Peripheral B Select Register */
#define PIO_ABSR	0x78	/* AB Status Register */
#define PIO_OWER	0xa0	/* Output Write Enable Register */
#define PIO_OWDR	0xa4	/* Output Write Disable Register */
#define PIO_OWSR	0xa8	/* Output Write Status Register */
#endif

#endif
Commit	Line	Data
6d1dbbbf	1	/*
9606b3c8	2	* [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
6d1dbbbf SP	3	*
	4	* Copyright (C) 2005 Ivan Kokshaysky
	5	* Copyright (C) SAN People
5d8e359c	6	* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
6d1dbbbf SP	7	*
	8	* Parallel I/O Controller (PIO) - System peripherals registers.
	9	* Based on AT91RM9200 datasheet revision E.
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
6d1dbbbf SP	12	*/
	13
	14	#ifndef AT91_PIO_H
	15	#define AT91_PIO_H
	16
5d8e359c JS	17
5d8e359c JS	18	#define AT91_ASM_PIO_RANGE 0x200
98250e8e	19	#define AT91_ASM_PIOC_ASR \
96fd9906	20	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
98250e8e	21	#define AT91_ASM_PIOC_BSR \
96fd9906	22	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
5d8e359c	23	#define AT91_ASM_PIOC_PDR \
96fd9906	24	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
5d8e359c	25	#define AT91_ASM_PIOC_PUDR \
96fd9906	26	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
5d8e359c JS	27
5d8e359c JS	28	#define AT91_ASM_PIOD_PDR \
96fd9906	29	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
5d8e359c	30	#define AT91_ASM_PIOD_PUDR \
96fd9906	31	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
5d8e359c	32	#define AT91_ASM_PIOD_ASR \
96fd9906	33	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
5d8e359c JS	34
	35	#ifndef __ASSEMBLY__
	36
	37	typedef struct at91_port {
	38	u32 per; /* 0x00 PIO Enable Register */
	39	u32 pdr; /* 0x04 PIO Disable Register */
	40	u32 psr; /* 0x08 PIO Status Register */
	41	u32 reserved0;
	42	u32 oer; /* 0x10 Output Enable Register */
	43	u32 odr; /* 0x14 Output Disable Registerr */
	44	u32 osr; /* 0x18 Output Status Register */
	45	u32 reserved1;
	46	u32 ifer; /* 0x20 Input Filter Enable Register */
	47	u32 ifdr; /* 0x24 Input Filter Disable Register */
	48	u32 ifsr; /* 0x28 Input Filter Status Register */
	49	u32 reserved2;
	50	u32 sodr; /* 0x30 Set Output Data Register */
	51	u32 codr; /* 0x34 Clear Output Data Register */
	52	u32 odsr; /* 0x38 Output Data Status Register */
	53	u32 pdsr; /* 0x3C Pin Data Status Register */
	54	u32 ier; /* 0x40 Interrupt Enable Register */
	55	u32 idr; /* 0x44 Interrupt Disable Register */
	56	u32 imr; /* 0x48 Interrupt Mask Register */
	57	u32 isr; /* 0x4C Interrupt Status Register */
	58	u32 mder; /* 0x50 Multi-driver Enable Register */
	59	u32 mddr; /* 0x54 Multi-driver Disable Register */
	60	u32 mdsr; /* 0x58 Multi-driver Status Register */
	61	u32 reserved3;
	62	u32 pudr; /* 0x60 Pull-up Disable Register */
	63	u32 puer; /* 0x64 Pull-up Enable Register */
	64	u32 pusr; /* 0x68 Pad Pull-up Status Register */
	65	u32 reserved4;
2b3b1c66 BS	66	#if defined(CPU_HAS_PIO3)
	67	u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
	68	u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
	69	u32 reserved5[2];
	70	u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
	71	u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
	72	u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
	73	u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
	74	u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
	75	u32 ppder; /* 0x94 Pad Pull-down Enable Register */
	76	u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
	77	u32 reserved6; /* */
	78	#else
5d8e359c JS	79	u32 asr; /* 0x70 Select A Register */
	80	u32 bsr; /* 0x74 Select B Register */
	81	u32 absr; /* 0x78 AB Select Status Register */
	82	u32 reserved5[9]; /* */
2b3b1c66	83	#endif
5d8e359c JS	84	u32 ower; /* 0xA0 Output Write Enable Register */
5d8e359c JS	85	u32 owdr; /* 0xA4 Output Write Disable Register */
2b3b1c66 BS	86	u32 owsr; /* OxA8 Output Write Status Register */
	87	#if defined(CPU_HAS_PIO3)
	88	u32 reserved7; /* */
	89	u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
	90	u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
	91	u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */
	92	u32 reserved8; /* */
	93	u32 esr; /* 0xC0 Edge Select Register */
	94	u32 lsr; /* 0xC4 Level Select Register */
	95	u32 elsr; /* 0xC8 Edge/Level Status Register */
	96	u32 reserved9; /* 0xCC */
	97	u32 fellsr; /* 0xD0 Falling /Low Level Select Register */
	98	u32 rehlsr; /* 0xD4 Rising /High Level Select Register */
	99	u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
	100	u32 reserved10; /* */
	101	u32 locksr; /* 0xE0 Lock Status */
	102	u32 wpmr; /* 0xE4 Write Protect Mode Register */
	103	u32 wpsr; /* 0xE8 Write Protect Status Register */
	104	u32 reserved11[5]; /* */
	105	u32 schmitt; /* 0x100 Schmitt Trigger Register */
	106	u32 reserved12[63];
	107	#else
5d8e359c	108	u32 reserved6[85];
2b3b1c66	109	#endif
5d8e359c JS	110	} at91_port_t;
5d8e359c JS	111
5d8e359c JS	112	typedef union at91_pio {
	113	struct {
	114	at91_port_t pioa;
	115	at91_port_t piob;
	116	at91_port_t pioc;
83f1072e	117	#if (ATMEL_PIO_PORTS > 3)
5d8e359c JS	118	at91_port_t piod;
5d8e359c JS	119	#endif
83f1072e	120	#if (ATMEL_PIO_PORTS > 4)
5d8e359c JS	121	at91_port_t pioe;
	122	#endif
	123	} ;
83f1072e	124	at91_port_t port[ATMEL_PIO_PORTS];
5d8e359c JS	125	} at91_pio_t;
5d8e359c JS	126
ea8fbba7 JS	127	#ifdef CONFIG_AT91_GPIO
	128	int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
	129	int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
2b3b1c66 BS	130	#if defined(CPU_HAS_PIO3)
	131	int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
	132	int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
	133	int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
	134	int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
	135	int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
	136	#endif
ea8fbba7 JS	137	int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
	138	int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
	139	int at91_set_pio_output(unsigned port, unsigned pin, int value);
	140	int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
	141	int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
	142	int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
	143	int at91_set_pio_value(unsigned port, unsigned pin, int value);
	144	int at91_get_pio_value(unsigned port, unsigned pin);
	145	#endif
5d8e359c JS	146	#endif
5d8e359c JS	147
5d8e359c JS	148	#define AT91_PIO_PORTA 0x0
	149	#define AT91_PIO_PORTB 0x1
	150	#define AT91_PIO_PORTC 0x2
	151	#define AT91_PIO_PORTD 0x3
	152	#define AT91_PIO_PORTE 0x4
	153
	154	#ifdef CONFIG_AT91_LEGACY
	155
6d1dbbbf SP	156	#define PIO_PER 0x00 /* Enable Register */
	157	#define PIO_PDR 0x04 /* Disable Register */
	158	#define PIO_PSR 0x08 /* Status Register */
	159	#define PIO_OER 0x10 /* Output Enable Register */
	160	#define PIO_ODR 0x14 /* Output Disable Register */
	161	#define PIO_OSR 0x18 /* Output Status Register */
	162	#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
	163	#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
	164	#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
	165	#define PIO_SODR 0x30 /* Set Output Data Register */
	166	#define PIO_CODR 0x34 /* Clear Output Data Register */
	167	#define PIO_ODSR 0x38 /* Output Data Status Register */
	168	#define PIO_PDSR 0x3c /* Pin Data Status Register */
	169	#define PIO_IER 0x40 /* Interrupt Enable Register */
	170	#define PIO_IDR 0x44 /* Interrupt Disable Register */
	171	#define PIO_IMR 0x48 /* Interrupt Mask Register */
	172	#define PIO_ISR 0x4c /* Interrupt Status Register */
	173	#define PIO_MDER 0x50 /* Multi-driver Enable Register */
	174	#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
	175	#define PIO_MDSR 0x58 /* Multi-driver Status Register */
	176	#define PIO_PUDR 0x60 /* Pull-up Disable Register */
	177	#define PIO_PUER 0x64 /* Pull-up Enable Register */
	178	#define PIO_PUSR 0x68 /* Pull-up Status Register */
	179	#define PIO_ASR 0x70 /* Peripheral A Select Register */
	180	#define PIO_BSR 0x74 /* Peripheral B Select Register */
	181	#define PIO_ABSR 0x78 /* AB Status Register */
	182	#define PIO_OWER 0xa0 /* Output Write Enable Register */
	183	#define PIO_OWDR 0xa4 /* Output Write Disable Register */
	184	#define PIO_OWSR 0xa8 /* Output Write Status Register */
5d8e359c	185	#endif
6d1dbbbf SP	186
6d1dbbbf SP	187	#endif