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6d1dbbbf | 1 | /* |
9606b3c8 SP |
2 | * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] |
3 | * | |
4 | * Copyright (C) 2007 Andrew Victor | |
5 | * Copyright (C) 2007 Atmel Corporation. | |
6d1dbbbf SP |
6 | * |
7 | * Reset Controller (RSTC) - System peripherals regsters. | |
8 | * Based on AT91SAM9261 datasheet revision D. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
6d1dbbbf SP |
11 | */ |
12 | ||
13 | #ifndef AT91_RSTC_H | |
14 | #define AT91_RSTC_H | |
15 | ||
fd2f5658 | 16 | #define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08) |
5d8e359c JS |
17 | |
18 | #ifndef __ASSEMBLY__ | |
19 | ||
20 | typedef struct at91_rstc { | |
21 | u32 cr; /* Reset Controller Control Register */ | |
22 | u32 sr; /* Reset Controller Status Register */ | |
23 | u32 mr; /* Reset Controller Mode Register */ | |
24 | } at91_rstc_t; | |
25 | ||
26 | #endif /* __ASSEMBLY__ */ | |
27 | ||
28 | #define AT91_RSTC_KEY 0xA5000000 | |
29 | ||
30 | #define AT91_RSTC_CR_PROCRST 0x00000001 | |
31 | #define AT91_RSTC_CR_PERRST 0x00000004 | |
32 | #define AT91_RSTC_CR_EXTRST 0x00000008 | |
33 | ||
34 | #define AT91_RSTC_MR_URSTEN 0x00000001 | |
35 | #define AT91_RSTC_MR_URSTIEN 0x00000010 | |
36 | #define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) | |
37 | #define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 | |
38 | ||
39 | #define AT91_RSTC_SR_NRSTL 0x00010000 | |
40 | ||
6d1dbbbf | 41 | #endif |