projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6d1dbbbf | 1 | /* |
| 9606b3c8 SP |
2 | * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] |
| 3 | * | |
| 4 | * Copyright (C) 2007 Andrew Victor | |
| 5 | * Copyright (C) 2007 Atmel Corporation. | |
| 6d1dbbbf SP |
6 | * |
| 7 | * Reset Controller (RSTC) - System peripherals regsters. | |
| 8 | * Based on AT91SAM9261 datasheet revision D. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; either version 2 of the License, or | |
| 13 | * (at your option) any later version. | |
| 14 | */ | |
| 15 | ||
| 16 | #ifndef AT91_RSTC_H | |
| 17 | #define AT91_RSTC_H | |
| 18 | ||
| 5d8e359c JS |
19 | #define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08) |
| 20 | ||
| 21 | #ifndef __ASSEMBLY__ | |
| 22 | ||
| 23 | typedef struct at91_rstc { | |
| 24 | u32 cr; /* Reset Controller Control Register */ | |
| 25 | u32 sr; /* Reset Controller Status Register */ | |
| 26 | u32 mr; /* Reset Controller Mode Register */ | |
| 27 | } at91_rstc_t; | |
| 28 | ||
| 29 | #endif /* __ASSEMBLY__ */ | |
| 30 | ||
| 31 | #define AT91_RSTC_KEY 0xA5000000 | |
| 32 | ||
| 33 | #define AT91_RSTC_CR_PROCRST 0x00000001 | |
| 34 | #define AT91_RSTC_CR_PERRST 0x00000004 | |
| 35 | #define AT91_RSTC_CR_EXTRST 0x00000008 | |
| 36 | ||
| 37 | #define AT91_RSTC_MR_URSTEN 0x00000001 | |
| 38 | #define AT91_RSTC_MR_URSTIEN 0x00000010 | |
| 39 | #define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) | |
| 40 | #define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 | |
| 41 | ||
| 42 | #define AT91_RSTC_SR_NRSTL 0x00010000 | |
| 43 | ||
| 44 | #ifdef CONFIG_AT91_LEGACY | |
| 45 | ||
| 6d1dbbbf SP |
46 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ |
| 47 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | |
| 48 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | |
| 49 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | |
| 6d1dbbbf SP |
50 | |
| 51 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | |
| 52 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | |
| 53 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | |
| 54 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | |
| 55 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) | |
| 56 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) | |
| 57 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) | |
| 58 | #define AT91_RSTC_RSTTYP_USER (4 << 8) | |
| 59 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | |
| 60 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | |
| 61 | ||
| 62 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | |
| 63 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | |
| 64 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | |
| 65 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | |
| 66 | ||
| 5d8e359c JS |
67 | #endif /* CONFIG_AT91_LEGACY */ |
| 68 | ||
| 6d1dbbbf | 69 | #endif |