[people/ms/u-boot.git] / arch / arm / include / asm / arch-at91 / at91cap9.h

/*
 * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
 *
 *  Copyright (C) 2007 Stelian Pop <stelian@popies.net>
 *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
 *  Copyright (C) 2007 Atmel Corporation.
 *
 * Common definitions.
 * Based on AT91CAP9 datasheet revision B (Preliminary).
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef AT91CAP9_H
#define AT91CAP9_H

/*
 * Peripheral identifiers/interrupts.
 */
#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS		1	/* System Peripherals */
#define AT91CAP9_ID_PIOABCD	2	/* Parallel IO Controller A, B, C and D */
#define AT91CAP9_ID_MPB0	3	/* MP Block Peripheral 0 */
#define AT91CAP9_ID_MPB1	4	/* MP Block Peripheral 1 */
#define AT91CAP9_ID_MPB2	5	/* MP Block Peripheral 2 */
#define AT91CAP9_ID_MPB3	6	/* MP Block Peripheral 3 */
#define AT91CAP9_ID_MPB4	7	/* MP Block Peripheral 4 */
#define AT91CAP9_ID_US0		8	/* USART 0 */
#define AT91CAP9_ID_US1		9	/* USART 1 */
#define AT91CAP9_ID_US2		10	/* USART 2 */
#define AT91CAP9_ID_MCI0	11	/* Multimedia Card Interface 0 */
#define AT91CAP9_ID_MCI1	12	/* Multimedia Card Interface 1 */
#define AT91CAP9_ID_CAN		13	/* CAN */
#define AT91CAP9_ID_TWI		14	/* Two-Wire Interface */
#define AT91CAP9_ID_SPI0	15	/* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SPI1	16	/* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SSC0	17	/* Serial Synchronous Controller 0 */
#define AT91CAP9_ID_SSC1	18	/* Serial Synchronous Controller 1 */
#define AT91CAP9_ID_AC97C	19	/* AC97 Controller */
#define AT91CAP9_ID_TCB		20	/* Timer Counter 0, 1 and 2 */
#define AT91CAP9_ID_PWMC	21	/* Pulse Width Modulation Controller */
#define AT91CAP9_ID_EMAC	22	/* Ethernet */
#define AT91CAP9_ID_AESTDES	23	/* Advanced Encryption Standard, Triple DES */
#define AT91CAP9_ID_ADC		24	/* Analog-to-Digital Converter */
#define AT91CAP9_ID_ISI		25	/* Image Sensor Interface */
#define AT91CAP9_ID_LCDC	26	/* LCD Controller */
#define AT91CAP9_ID_DMA		27	/* DMA Controller */
#define AT91CAP9_ID_UDPHS	28	/* USB High Speed Device Port */
#define AT91CAP9_ID_UHP		29	/* USB Host Port */
#define AT91CAP9_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
#define AT91CAP9_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */

#define AT91_PIO_BASE	0xfffff200
#define AT91_PMC_BASE	0xfffffc00
#define AT91_RSTC_BASE	0xfffffd00
#define AT91_PIT_BASE	0xfffffd30

#ifdef CONFIG_AT91_LEGACY

/*
 * User Peripheral physical base addresses.
 */
#define AT91CAP9_BASE_UDPHS		0xfff78000
#define AT91CAP9_BASE_TCB0		0xfff7c000
#define AT91CAP9_BASE_TC0		0xfff7c000
#define AT91CAP9_BASE_TC1		0xfff7c040
#define AT91CAP9_BASE_TC2		0xfff7c080
#define AT91CAP9_BASE_MCI0		0xfff80000
#define AT91CAP9_BASE_MCI1		0xfff84000
#define AT91CAP9_BASE_TWI		0xfff88000
#define AT91CAP9_BASE_US0		0xfff8c000
#define AT91CAP9_BASE_US1		0xfff90000
#define AT91CAP9_BASE_US2		0xfff94000
#define AT91CAP9_BASE_SSC0		0xfff98000
#define AT91CAP9_BASE_SSC1		0xfff9c000
#define AT91CAP9_BASE_AC97C		0xfffa0000
#define AT91CAP9_BASE_SPI0		0xfffa4000
#define AT91CAP9_BASE_SPI1		0xfffa8000
#define AT91CAP9_BASE_CAN		0xfffac000
#define AT91CAP9_BASE_PWMC		0xfffb8000
#define AT91CAP9_BASE_EMAC		0xfffbc000
#define AT91CAP9_BASE_ADC		0xfffc0000
#define AT91CAP9_BASE_ISI		0xfffc4000
#define AT91_BASE_SYS			0xffffe200

/*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
#define AT91_ECC	(0xffffe200 - AT91_BASE_SYS)
#define AT91_BCRAMC	(0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC	(0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC	(0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX	(0xffffea00 - AT91_BASE_SYS)
#define AT91_CCFG	(0xffffeb10 - AT91_BASE_SYS)
#define AT91_DMA	(0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU	(0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA	(0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB	(0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC	(0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD	(0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
#define AT91_SCKCR	(0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVB	(0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVC	(0xfffffd60 - AT91_BASE_SYS)

#define AT91_USART0	AT91CAP9_BASE_US0
#define AT91_USART1	AT91CAP9_BASE_US1
#define AT91_USART2	AT91CAP9_BASE_US2

/*
 * SCKCR flags
 */
#define AT91CAP9_SCKCR_RCEN	(1 << 0)	/* RC Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32EN	(1 << 1)	/* 32kHz Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32BYP	(1 << 2)	/* 32kHz Oscillator Bypass */
#define AT91CAP9_SCKCR_OSCSEL	(1 << 3)	/* Slow Clock Selector */
#define		AT91CAP9_SCKCR_OSCSEL_RC	(0 << 3)
#define		AT91CAP9_SCKCR_OSCSEL_32	(1 << 3)

#endif /* CONFIG_AT91_LEGACY */
/*
 * Internal Memory.
 */
#define AT91CAP9_SRAM_BASE	0x00100000	/* Internal SRAM base address */
#define AT91CAP9_SRAM_SIZE	(32 * SZ_1K)	/* Internal SRAM size (32Kb) */

#define AT91CAP9_ROM_BASE	0x00400000	/* Internal ROM base address */
#define AT91CAP9_ROM_SIZE	(32 * SZ_1K)	/* Internal ROM size (32Kb) */

#define AT91CAP9_LCDC_BASE	0x00500000	/* LCD Controller */
#define AT91CAP9_UDPHS_BASE	0x00600000	/* USB High Speed Device Port */
#define AT91CAP9_UHP_BASE	0x00700000	/* USB Host controller */

#define CONFIG_DRAM_BASE	AT91_CHIPSELECT_6

/*
 * Cpu Name
 */
#define CONFIG_SYS_AT91_CPU_NAME	"AT91CAP9"

#endif
Commit	Line	Data
6d1dbbbf	1	/*
4f6c8101	2	* [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
6d1dbbbf	3	*
c9e798d3	4	* Copyright (C) 2007 Stelian Pop <stelian@popies.net>
6d1dbbbf SP	5	* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
	6	* Copyright (C) 2007 Atmel Corporation.
	7	*
	8	* Common definitions.
	9	* Based on AT91CAP9 datasheet revision B (Preliminary).
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
6d1dbbbf SP	12	*/
	13
	14	#ifndef AT91CAP9_H
	15	#define AT91CAP9_H
	16
	17	/*
	18	* Peripheral identifiers/interrupts.
	19	*/
	20	#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
	21	#define AT91_ID_SYS 1 /* System Peripherals */
	22	#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
	23	#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
	24	#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
	25	#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
	26	#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
	27	#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
	28	#define AT91CAP9_ID_US0 8 /* USART 0 */
	29	#define AT91CAP9_ID_US1 9 /* USART 1 */
	30	#define AT91CAP9_ID_US2 10 /* USART 2 */
	31	#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
	32	#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
	33	#define AT91CAP9_ID_CAN 13 /* CAN */
	34	#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
	35	#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
	36	#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
	37	#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
	38	#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
	39	#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
	40	#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
	41	#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
	42	#define AT91CAP9_ID_EMAC 22 /* Ethernet */
	43	#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
	44	#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
	45	#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
	46	#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
	47	#define AT91CAP9_ID_DMA 27 /* DMA Controller */
	48	#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
	49	#define AT91CAP9_ID_UHP 29 /* USB Host Port */
	50	#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
	51	#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
	52
5d8e359c JS	53	#define AT91_PIO_BASE 0xfffff200
	54	#define AT91_PMC_BASE 0xfffffc00
	55	#define AT91_RSTC_BASE 0xfffffd00
	56	#define AT91_PIT_BASE 0xfffffd30
	57
	58	#ifdef CONFIG_AT91_LEGACY
	59
6d1dbbbf SP	60	/*
	61	* User Peripheral physical base addresses.
	62	*/
	63	#define AT91CAP9_BASE_UDPHS 0xfff78000
	64	#define AT91CAP9_BASE_TCB0 0xfff7c000
	65	#define AT91CAP9_BASE_TC0 0xfff7c000
	66	#define AT91CAP9_BASE_TC1 0xfff7c040
	67	#define AT91CAP9_BASE_TC2 0xfff7c080
	68	#define AT91CAP9_BASE_MCI0 0xfff80000
	69	#define AT91CAP9_BASE_MCI1 0xfff84000
	70	#define AT91CAP9_BASE_TWI 0xfff88000
	71	#define AT91CAP9_BASE_US0 0xfff8c000
	72	#define AT91CAP9_BASE_US1 0xfff90000
	73	#define AT91CAP9_BASE_US2 0xfff94000
	74	#define AT91CAP9_BASE_SSC0 0xfff98000
	75	#define AT91CAP9_BASE_SSC1 0xfff9c000
	76	#define AT91CAP9_BASE_AC97C 0xfffa0000
	77	#define AT91CAP9_BASE_SPI0 0xfffa4000
	78	#define AT91CAP9_BASE_SPI1 0xfffa8000
	79	#define AT91CAP9_BASE_CAN 0xfffac000
	80	#define AT91CAP9_BASE_PWMC 0xfffb8000
	81	#define AT91CAP9_BASE_EMAC 0xfffbc000
	82	#define AT91CAP9_BASE_ADC 0xfffc0000
	83	#define AT91CAP9_BASE_ISI 0xfffc4000
	84	#define AT91_BASE_SYS 0xffffe200
	85
	86	/*
	87	* System Peripherals (offset from AT91_BASE_SYS)
	88	*/
	89	#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
	90	#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
	91	#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
	92	#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
	93	#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
	94	#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
	95	#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
	96	#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
	97	#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
	98	#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
	99	#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
	100	#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
	101	#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
	102	#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
	103	#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
	104	#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
	105	#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
	106	#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
	107	#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
19883aed SP	108	#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
	109	#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
	110	#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
6d1dbbbf SP	111
	112	#define AT91_USART0 AT91CAP9_BASE_US0
	113	#define AT91_USART1 AT91CAP9_BASE_US1
	114	#define AT91_USART2 AT91CAP9_BASE_US2
	115
19883aed SP	116	/*
	117	* SCKCR flags
	118	*/
	119	#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
	120	#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
	121	#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
	122	#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
	123	#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
	124	#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
	125
5d8e359c	126	#endif /* CONFIG_AT91_LEGACY */
6d1dbbbf SP	127	/*
	128	* Internal Memory.
	129	*/
	130	#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
	131	#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
	132
	133	#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
	134	#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
	135
	136	#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
	137	#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
	138	#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
	139
	140	#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
	141
b32e1890 JCPV	142	/*
	143	* Cpu Name
	144	*/
7c966a8b	145	#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
b32e1890	146
6d1dbbbf	147	#endif