[people/ms/u-boot.git] / arch / arm / include / asm / arch-davinci / emac_defs.h

/*
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Based on:
 *
 * ----------------------------------------------------------------------------
 *
 * dm644x_emac.h
 *
 * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
 *
 * Copyright (C) 2005 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------

 * Modifications:
 * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
 *
 */

#ifndef _DM644X_EMAC_H_
#define _DM644X_EMAC_H_

#include <asm/arch/hardware.h>

#ifdef CONFIG_SOC_DM365
#define EMAC_BASE_ADDR			(0x01d07000)
#define EMAC_WRAPPER_BASE_ADDR		(0x01d0a000)
#define EMAC_WRAPPER_RAM_ADDR		(0x01d08000)
#define EMAC_MDIO_BASE_ADDR		(0x01d0b000)
#define DAVINCI_EMAC_VERSION2
#elif defined(CONFIG_SOC_DA8XX)
#define EMAC_BASE_ADDR			DAVINCI_EMAC_CNTRL_REGS_BASE
#define EMAC_WRAPPER_BASE_ADDR		DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
#define EMAC_WRAPPER_RAM_ADDR		DAVINCI_EMAC_WRAPPER_RAM_BASE
#define EMAC_MDIO_BASE_ADDR		DAVINCI_MDIO_CNTRL_REGS_BASE
#define DAVINCI_EMAC_VERSION2
#else
#define EMAC_BASE_ADDR			(0x01c80000)
#define EMAC_WRAPPER_BASE_ADDR		(0x01c81000)
#define EMAC_WRAPPER_RAM_ADDR		(0x01c82000)
#define EMAC_MDIO_BASE_ADDR		(0x01c84000)
#endif

#ifdef CONFIG_SOC_DM646X
#define DAVINCI_EMAC_VERSION2
#define DAVINCI_EMAC_GIG_ENABLE
#endif

#ifdef CONFIG_SOC_DM646X
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ		76500000
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ		2500000		/* 2.5 MHz */
#elif defined(CONFIG_SOC_DM365)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ		121500000
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ		2200000		/* 2.2 MHz */
#elif defined(CONFIG_SOC_DA8XX)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ		clk_get(DAVINCI_MDIO_CLKID)
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
#else
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ		99000000	/* PLL/6 - 99 MHz */
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
#endif

/* PHY mask - set only those phy number bits where phy is/can be connected */
#define EMAC_MDIO_PHY_NUM           1
#define EMAC_MDIO_PHY_MASK          (1 << EMAC_MDIO_PHY_NUM)

/* Ethernet Min/Max packet size */
#define EMAC_MIN_ETHERNET_PKT_SIZE	60
#define EMAC_MAX_ETHERNET_PKT_SIZE	1518
#define EMAC_PKT_ALIGN			18	/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */

/* Number of RX packet buffers
 * NOTE: Only 1 buffer supported as of now
 */
#define EMAC_MAX_RX_BUFFERS		10


/***********************************************
 ******** Internally used macros ***************
 ***********************************************/

#define EMAC_CH_TX			1
#define EMAC_CH_RX			0

/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
 * reserve space for 64 descriptors max
 */
#define EMAC_RX_DESC_BASE		0x0
#define EMAC_TX_DESC_BASE		0x1000

/* EMAC Teardown value */
#define EMAC_TEARDOWN_VALUE		0xfffffffc

/* MII Status Register */
#define MII_STATUS_REG			1

/* Number of statistics registers */
#define EMAC_NUM_STATS			36


/* EMAC Descriptor */
typedef volatile struct _emac_desc
{
	u_int32_t	next;		/* Pointer to next descriptor in chain */
	u_int8_t	*buffer;	/* Pointer to data buffer */
	u_int32_t	buff_off_len;	/* Buffer Offset(MSW) and Length(LSW) */
	u_int32_t	pkt_flag_len;	/* Packet Flags(MSW) and Length(LSW) */
} emac_desc;

/* CPPI bit positions */
#define EMAC_CPPI_SOP_BIT		(0x80000000)
#define EMAC_CPPI_EOP_BIT		(0x40000000)
#define EMAC_CPPI_OWNERSHIP_BIT		(0x20000000)
#define EMAC_CPPI_EOQ_BIT		(0x10000000)
#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT	(0x08000000)
#define EMAC_CPPI_PASS_CRC_BIT		(0x04000000)

#define EMAC_CPPI_RX_ERROR_FRAME	(0x03fc0000)

#define EMAC_MACCONTROL_MIIEN_ENABLE		(0x20)
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	(0x1)
#define EMAC_MACCONTROL_GIGABIT_ENABLE		(1 << 7)
#define EMAC_MACCONTROL_GIGFORCE		(1 << 17)
#define EMAC_MACCONTROL_RMIISPEED_100		(1 << 15)

#define EMAC_MAC_ADDR_MATCH		(1 << 19)
#define EMAC_MAC_ADDR_IS_VALID		(1 << 20)

#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE	(0x200000)
#define EMAC_RXMBPENABLE_RXBROADEN	(0x2000)


#define MDIO_CONTROL_IDLE		(0x80000000)
#define MDIO_CONTROL_ENABLE		(0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE	(0x40000)
#define MDIO_CONTROL_FAULT		(0x80000)
#define MDIO_USERACCESS0_GO		(0x80000000)
#define MDIO_USERACCESS0_WRITE_READ	(0x0)
#define MDIO_USERACCESS0_WRITE_WRITE	(0x40000000)
#define MDIO_USERACCESS0_ACK		(0x20000000)

/* Ethernet MAC Registers Structure */
typedef struct  {
	dv_reg		TXIDVER;
	dv_reg		TXCONTROL;
	dv_reg		TXTEARDOWN;
	u_int8_t	RSVD0[4];
	dv_reg		RXIDVER;
	dv_reg		RXCONTROL;
	dv_reg		RXTEARDOWN;
	u_int8_t	RSVD1[100];
	dv_reg		TXINTSTATRAW;
	dv_reg		TXINTSTATMASKED;
	dv_reg		TXINTMASKSET;
	dv_reg		TXINTMASKCLEAR;
	dv_reg		MACINVECTOR;
	u_int8_t	RSVD2[12];
	dv_reg		RXINTSTATRAW;
	dv_reg		RXINTSTATMASKED;
	dv_reg		RXINTMASKSET;
	dv_reg		RXINTMASKCLEAR;
	dv_reg		MACINTSTATRAW;
	dv_reg		MACINTSTATMASKED;
	dv_reg		MACINTMASKSET;
	dv_reg		MACINTMASKCLEAR;
	u_int8_t	RSVD3[64];
	dv_reg		RXMBPENABLE;
	dv_reg		RXUNICASTSET;
	dv_reg		RXUNICASTCLEAR;
	dv_reg		RXMAXLEN;
	dv_reg		RXBUFFEROFFSET;
	dv_reg		RXFILTERLOWTHRESH;
	u_int8_t	RSVD4[8];
	dv_reg		RX0FLOWTHRESH;
	dv_reg		RX1FLOWTHRESH;
	dv_reg		RX2FLOWTHRESH;
	dv_reg		RX3FLOWTHRESH;
	dv_reg		RX4FLOWTHRESH;
	dv_reg		RX5FLOWTHRESH;
	dv_reg		RX6FLOWTHRESH;
	dv_reg		RX7FLOWTHRESH;
	dv_reg		RX0FREEBUFFER;
	dv_reg		RX1FREEBUFFER;
	dv_reg		RX2FREEBUFFER;
	dv_reg		RX3FREEBUFFER;
	dv_reg		RX4FREEBUFFER;
	dv_reg		RX5FREEBUFFER;
	dv_reg		RX6FREEBUFFER;
	dv_reg		RX7FREEBUFFER;
	dv_reg		MACCONTROL;
	dv_reg		MACSTATUS;
	dv_reg		EMCONTROL;
	dv_reg		FIFOCONTROL;
	dv_reg		MACCONFIG;
	dv_reg		SOFTRESET;
	u_int8_t	RSVD5[88];
	dv_reg		MACSRCADDRLO;
	dv_reg		MACSRCADDRHI;
	dv_reg		MACHASH1;
	dv_reg		MACHASH2;
	dv_reg		BOFFTEST;
	dv_reg		TPACETEST;
	dv_reg		RXPAUSE;
	dv_reg		TXPAUSE;
	u_int8_t	RSVD6[16];
	dv_reg		RXGOODFRAMES;
	dv_reg		RXBCASTFRAMES;
	dv_reg		RXMCASTFRAMES;
	dv_reg		RXPAUSEFRAMES;
	dv_reg		RXCRCERRORS;
	dv_reg		RXALIGNCODEERRORS;
	dv_reg		RXOVERSIZED;
	dv_reg		RXJABBER;
	dv_reg		RXUNDERSIZED;
	dv_reg		RXFRAGMENTS;
	dv_reg		RXFILTERED;
	dv_reg		RXQOSFILTERED;
	dv_reg		RXOCTETS;
	dv_reg		TXGOODFRAMES;
	dv_reg		TXBCASTFRAMES;
	dv_reg		TXMCASTFRAMES;
	dv_reg		TXPAUSEFRAMES;
	dv_reg		TXDEFERRED;
	dv_reg		TXCOLLISION;
	dv_reg		TXSINGLECOLL;
	dv_reg		TXMULTICOLL;
	dv_reg		TXEXCESSIVECOLL;
	dv_reg		TXLATECOLL;
	dv_reg		TXUNDERRUN;
	dv_reg		TXCARRIERSENSE;
	dv_reg		TXOCTETS;
	dv_reg		FRAME64;
	dv_reg		FRAME65T127;
	dv_reg		FRAME128T255;
	dv_reg		FRAME256T511;
	dv_reg		FRAME512T1023;
	dv_reg		FRAME1024TUP;
	dv_reg		NETOCTETS;
	dv_reg		RXSOFOVERRUNS;
	dv_reg		RXMOFOVERRUNS;
	dv_reg		RXDMAOVERRUNS;
	u_int8_t	RSVD7[624];
	dv_reg		MACADDRLO;
	dv_reg		MACADDRHI;
	dv_reg		MACINDEX;
	u_int8_t	RSVD8[244];
	dv_reg		TX0HDP;
	dv_reg		TX1HDP;
	dv_reg		TX2HDP;
	dv_reg		TX3HDP;
	dv_reg		TX4HDP;
	dv_reg		TX5HDP;
	dv_reg		TX6HDP;
	dv_reg		TX7HDP;
	dv_reg		RX0HDP;
	dv_reg		RX1HDP;
	dv_reg		RX2HDP;
	dv_reg		RX3HDP;
	dv_reg		RX4HDP;
	dv_reg		RX5HDP;
	dv_reg		RX6HDP;
	dv_reg		RX7HDP;
	dv_reg		TX0CP;
	dv_reg		TX1CP;
	dv_reg		TX2CP;
	dv_reg		TX3CP;
	dv_reg		TX4CP;
	dv_reg		TX5CP;
	dv_reg		TX6CP;
	dv_reg		TX7CP;
	dv_reg		RX0CP;
	dv_reg		RX1CP;
	dv_reg		RX2CP;
	dv_reg		RX3CP;
	dv_reg		RX4CP;
	dv_reg		RX5CP;
	dv_reg		RX6CP;
	dv_reg		RX7CP;
} emac_regs;

/* EMAC Wrapper Registers Structure */
typedef struct  {
#ifdef DAVINCI_EMAC_VERSION2
	dv_reg		idver;
	dv_reg		softrst;
	dv_reg		emctrl;
	dv_reg		c0rxthreshen;
	dv_reg		c0rxen;
	dv_reg		c0txen;
	dv_reg		c0miscen;
	dv_reg		c1rxthreshen;
	dv_reg		c1rxen;
	dv_reg		c1txen;
	dv_reg		c1miscen;
	dv_reg		c2rxthreshen;
	dv_reg		c2rxen;
	dv_reg		c2txen;
	dv_reg		c2miscen;
	dv_reg		c0rxthreshstat;
	dv_reg		c0rxstat;
	dv_reg		c0txstat;
	dv_reg		c0miscstat;
	dv_reg		c1rxthreshstat;
	dv_reg		c1rxstat;
	dv_reg		c1txstat;
	dv_reg		c1miscstat;
	dv_reg		c2rxthreshstat;
	dv_reg		c2rxstat;
	dv_reg		c2txstat;
	dv_reg		c2miscstat;
	dv_reg		c0rximax;
	dv_reg		c0tximax;
	dv_reg		c1rximax;
	dv_reg		c1tximax;
	dv_reg		c2rximax;
	dv_reg		c2tximax;
#else
	u_int8_t	RSVD0[4100];
	dv_reg		EWCTL;
	dv_reg		EWINTTCNT;
#endif
} ewrap_regs;

/* EMAC MDIO Registers Structure */
typedef struct  {
	dv_reg		VERSION;
	dv_reg		CONTROL;
	dv_reg		ALIVE;
	dv_reg		LINK;
	dv_reg		LINKINTRAW;
	dv_reg		LINKINTMASKED;
	u_int8_t	RSVD0[8];
	dv_reg		USERINTRAW;
	dv_reg		USERINTMASKED;
	dv_reg		USERINTMASKSET;
	dv_reg		USERINTMASKCLEAR;
	u_int8_t	RSVD1[80];
	dv_reg		USERACCESS0;
	dv_reg		USERPHYSEL0;
	dv_reg		USERACCESS1;
	dv_reg		USERPHYSEL1;
} mdio_regs;

int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
void davinci_eth_set_mac_addr(const u_int8_t *addr);

typedef struct
{
	char	name[64];
	int	(*init)(int phy_addr);
	int	(*is_phy_connected)(int phy_addr);
	int	(*get_link_speed)(int phy_addr);
	int	(*auto_negotiate)(int phy_addr);
} phy_t;

#define PHY_LXT972	(0x001378e2)
int lxt972_is_phy_connected(int phy_addr);
int lxt972_get_link_speed(int phy_addr);
int lxt972_init_phy(int phy_addr);
int lxt972_auto_negotiate(int phy_addr);

#define PHY_DP83848	(0x20005c90)
int dp83848_is_phy_connected(int phy_addr);
int dp83848_get_link_speed(int phy_addr);
int dp83848_init_phy(int phy_addr);
int dp83848_auto_negotiate(int phy_addr);

#endif  /* _DM644X_EMAC_H_ */
Commit	Line	Data
c74b2108 SK	1	/*
	2	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	3	*
	4	* Based on:
	5	*
	6	* ----------------------------------------------------------------------------
	7	*
	8	* dm644x_emac.h
	9	*
	10	* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
	11	*
	12	* Copyright (C) 2005 Texas Instruments.
	13	*
	14	* ----------------------------------------------------------------------------
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License as published by
	18	* the Free Software Foundation; either version 2 of the License, or
	19	* (at your option) any later version.
	20	*
	21	* This program is distributed in the hope that it will be useful,
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* You should have received a copy of the GNU General Public License
	27	* along with this program; if not, write to the Free Software
	28	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	29	* ----------------------------------------------------------------------------
	30
	31	* Modifications:
	32	* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
	33	*
	34	*/
	35
	36	#ifndef _DM644X_EMAC_H_
	37	#define _DM644X_EMAC_H_
	38
	39	#include <asm/arch/hardware.h>
	40
7835f4b9 SP	41	#ifdef CONFIG_SOC_DM365
	42	#define EMAC_BASE_ADDR (0x01d07000)
	43	#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
	44	#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
	45	#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
d7e35437 NT	46	#define DAVINCI_EMAC_VERSION2
	47	#elif defined(CONFIG_SOC_DA8XX)
	48	#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
	49	#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
	50	#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
	51	#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
	52	#define DAVINCI_EMAC_VERSION2
7835f4b9	53	#else
c74b2108 SK	54	#define EMAC_BASE_ADDR (0x01c80000)
	55	#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
	56	#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
	57	#define EMAC_MDIO_BASE_ADDR (0x01c84000)
7835f4b9	58	#endif
c74b2108	59
d7e35437 NT	60	#ifdef CONFIG_SOC_DM646X
	61	#define DAVINCI_EMAC_VERSION2
	62	#define DAVINCI_EMAC_GIG_ENABLE
	63	#endif
	64
95ae803a	65	#ifdef CONFIG_SOC_DM646X
7835f4b9 SP	66	/* MDIO module input frequency */
	67	#define EMAC_MDIO_BUS_FREQ 76500000
	68	/* MDIO clock output frequency */
	69	#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
	70	#elif defined(CONFIG_SOC_DM365)
	71	/* MDIO module input frequency */
	72	#define EMAC_MDIO_BUS_FREQ 121500000
	73	/* MDIO clock output frequency */
	74	#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
d7e35437 NT	75	#elif defined(CONFIG_SOC_DA8XX)
	76	/* MDIO module input frequency */
	77	#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
	78	/* MDIO clock output frequency */
	79	#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
7835f4b9	80	#else
c74b2108 SK	81	/* MDIO module input frequency */
	82	#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
	83	/* MDIO clock output frequency */
	84	#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
7835f4b9 SP	85	#endif
	86
	87	/* PHY mask - set only those phy number bits where phy is/can be connected */
	88	#define EMAC_MDIO_PHY_NUM 1
	89	#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM)
c74b2108 SK	90
	91	/* Ethernet Min/Max packet size */
	92	#define EMAC_MIN_ETHERNET_PKT_SIZE 60
	93	#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
	94	#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
	95
	96	/* Number of RX packet buffers
	97	* NOTE: Only 1 buffer supported as of now
	98	*/
	99	#define EMAC_MAX_RX_BUFFERS 10
	100
	101
	102	/***********************************************
	103	****** Internally used macros *************
	104	***********************************************/
	105
	106	#define EMAC_CH_TX 1
	107	#define EMAC_CH_RX 0
	108
	109	/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
	110	* reserve space for 64 descriptors max
	111	*/
	112	#define EMAC_RX_DESC_BASE 0x0
	113	#define EMAC_TX_DESC_BASE 0x1000
	114
	115	/* EMAC Teardown value */
	116	#define EMAC_TEARDOWN_VALUE 0xfffffffc
	117
	118	/* MII Status Register */
	119	#define MII_STATUS_REG 1
	120
	121	/* Number of statistics registers */
	122	#define EMAC_NUM_STATS 36
	123
	124
	125	/* EMAC Descriptor */
	126	typedef volatile struct _emac_desc
	127	{
	128	u_int32_t next; /* Pointer to next descriptor in chain */
	129	u_int8_t buffer; / Pointer to data buffer */
	130	u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
	131	u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
	132	} emac_desc;
	133
	134	/* CPPI bit positions */
	135	#define EMAC_CPPI_SOP_BIT (0x80000000)
	136	#define EMAC_CPPI_EOP_BIT (0x40000000)
	137	#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
	138	#define EMAC_CPPI_EOQ_BIT (0x10000000)
	139	#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
	140	#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
	141
	142	#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
	143
	144	#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
	145	#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
7835f4b9 SP	146	#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
7835f4b9 SP	147	#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
d7e35437 NT	148	#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
	149
	150	#define EMAC_MAC_ADDR_MATCH (1 << 19)
	151	#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
c74b2108 SK	152
	153	#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
	154	#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
	155
	156
	157	#define MDIO_CONTROL_IDLE (0x80000000)
	158	#define MDIO_CONTROL_ENABLE (0x40000000)
	159	#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
	160	#define MDIO_CONTROL_FAULT (0x80000)
	161	#define MDIO_USERACCESS0_GO (0x80000000)
	162	#define MDIO_USERACCESS0_WRITE_READ (0x0)
	163	#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
	164	#define MDIO_USERACCESS0_ACK (0x20000000)
	165
	166	/* Ethernet MAC Registers Structure */
	167	typedef struct {
	168	dv_reg TXIDVER;
	169	dv_reg TXCONTROL;
	170	dv_reg TXTEARDOWN;
	171	u_int8_t RSVD0[4];
	172	dv_reg RXIDVER;
	173	dv_reg RXCONTROL;
	174	dv_reg RXTEARDOWN;
	175	u_int8_t RSVD1[100];
	176	dv_reg TXINTSTATRAW;
	177	dv_reg TXINTSTATMASKED;
	178	dv_reg TXINTMASKSET;
	179	dv_reg TXINTMASKCLEAR;
	180	dv_reg MACINVECTOR;
	181	u_int8_t RSVD2[12];
	182	dv_reg RXINTSTATRAW;
	183	dv_reg RXINTSTATMASKED;
	184	dv_reg RXINTMASKSET;
	185	dv_reg RXINTMASKCLEAR;
	186	dv_reg MACINTSTATRAW;
	187	dv_reg MACINTSTATMASKED;
	188	dv_reg MACINTMASKSET;
	189	dv_reg MACINTMASKCLEAR;
	190	u_int8_t RSVD3[64];
	191	dv_reg RXMBPENABLE;
	192	dv_reg RXUNICASTSET;
	193	dv_reg RXUNICASTCLEAR;
	194	dv_reg RXMAXLEN;
	195	dv_reg RXBUFFEROFFSET;
	196	dv_reg RXFILTERLOWTHRESH;
	197	u_int8_t RSVD4[8];
	198	dv_reg RX0FLOWTHRESH;
	199	dv_reg RX1FLOWTHRESH;
	200	dv_reg RX2FLOWTHRESH;
	201	dv_reg RX3FLOWTHRESH;
	202	dv_reg RX4FLOWTHRESH;
	203	dv_reg RX5FLOWTHRESH;
	204	dv_reg RX6FLOWTHRESH;
	205	dv_reg RX7FLOWTHRESH;
	206	dv_reg RX0FREEBUFFER;
	207	dv_reg RX1FREEBUFFER;
	208	dv_reg RX2FREEBUFFER;
	209	dv_reg RX3FREEBUFFER;
	210	dv_reg RX4FREEBUFFER;
	211	dv_reg RX5FREEBUFFER;
	212	dv_reg RX6FREEBUFFER;
	213	dv_reg RX7FREEBUFFER;
	214	dv_reg MACCONTROL;
	215	dv_reg MACSTATUS;
216	dv_reg EMCONTROL;
217	dv_reg FIFOCONTROL;
218	dv_reg MACCONFIG;
219	dv_reg SOFTRESET;
220	u_int8_t RSVD5[88];
221	dv_reg MACSRCADDRLO;
222	dv_reg MACSRCADDRHI;
223	dv_reg MACHASH1;
224	dv_reg MACHASH2;
225	dv_reg BOFFTEST;
226	dv_reg TPACETEST;
227	dv_reg RXPAUSE;
228	dv_reg TXPAUSE;
229	u_int8_t RSVD6[16];
230	dv_reg RXGOODFRAMES;
231	dv_reg RXBCASTFRAMES;
232	dv_reg RXMCASTFRAMES;
233	dv_reg RXPAUSEFRAMES;
234	dv_reg RXCRCERRORS;
235	dv_reg RXALIGNCODEERRORS;
236	dv_reg RXOVERSIZED;
237	dv_reg RXJABBER;
238	dv_reg RXUNDERSIZED;
239	dv_reg RXFRAGMENTS;
240	dv_reg RXFILTERED;
241	dv_reg RXQOSFILTERED;
242	dv_reg RXOCTETS;
243	dv_reg TXGOODFRAMES;
244	dv_reg TXBCASTFRAMES;
245	dv_reg TXMCASTFRAMES;
246	dv_reg TXPAUSEFRAMES;
247	dv_reg TXDEFERRED;
248	dv_reg TXCOLLISION;
249	dv_reg TXSINGLECOLL;
250	dv_reg TXMULTICOLL;
251	dv_reg TXEXCESSIVECOLL;
252	dv_reg TXLATECOLL;
253	dv_reg TXUNDERRUN;
254	dv_reg TXCARRIERSENSE;
255	dv_reg TXOCTETS;
256	dv_reg FRAME64;
257	dv_reg FRAME65T127;
258	dv_reg FRAME128T255;
259	dv_reg FRAME256T511;
260	dv_reg FRAME512T1023;
261	dv_reg FRAME1024TUP;
262	dv_reg NETOCTETS;
263	dv_reg RXSOFOVERRUNS;
264	dv_reg RXMOFOVERRUNS;
265	dv_reg RXDMAOVERRUNS;
266	u_int8_t RSVD7[624];
267	dv_reg MACADDRLO;
268	dv_reg MACADDRHI;
269	dv_reg MACINDEX;
270	u_int8_t RSVD8[244];
271	dv_reg TX0HDP;
272	dv_reg TX1HDP;
273	dv_reg TX2HDP;
274	dv_reg TX3HDP;
275	dv_reg TX4HDP;
276	dv_reg TX5HDP;
277	dv_reg TX6HDP;
278	dv_reg TX7HDP;
279	dv_reg RX0HDP;
280	dv_reg RX1HDP;
281	dv_reg RX2HDP;
282	dv_reg RX3HDP;
283	dv_reg RX4HDP;
284	dv_reg RX5HDP;
285	dv_reg RX6HDP;
286	dv_reg RX7HDP;
287	dv_reg TX0CP;
288	dv_reg TX1CP;
289	dv_reg TX2CP;
290	dv_reg TX3CP;
291	dv_reg TX4CP;
292	dv_reg TX5CP;
293	dv_reg TX6CP;
294	dv_reg TX7CP;
295	dv_reg RX0CP;
296	dv_reg RX1CP;
297	dv_reg RX2CP;
298	dv_reg RX3CP;
299	dv_reg RX4CP;
300	dv_reg RX5CP;
301	dv_reg RX6CP;
302	dv_reg RX7CP;
303	} emac_regs;
304
305	/* EMAC Wrapper Registers Structure */
306	typedef struct {
d7e35437 NT	307	#ifdef DAVINCI_EMAC_VERSION2
	308	dv_reg idver;
	309	dv_reg softrst;
	310	dv_reg emctrl;
	311	dv_reg c0rxthreshen;
	312	dv_reg c0rxen;
	313	dv_reg c0txen;
	314	dv_reg c0miscen;
	315	dv_reg c1rxthreshen;
	316	dv_reg c1rxen;
	317	dv_reg c1txen;
	318	dv_reg c1miscen;
	319	dv_reg c2rxthreshen;
	320	dv_reg c2rxen;
	321	dv_reg c2txen;
	322	dv_reg c2miscen;
	323	dv_reg c0rxthreshstat;
	324	dv_reg c0rxstat;
	325	dv_reg c0txstat;
	326	dv_reg c0miscstat;
	327	dv_reg c1rxthreshstat;
	328	dv_reg c1rxstat;
	329	dv_reg c1txstat;
	330	dv_reg c1miscstat;
	331	dv_reg c2rxthreshstat;
	332	dv_reg c2rxstat;
	333	dv_reg c2txstat;
	334	dv_reg c2miscstat;
	335	dv_reg c0rximax;
	336	dv_reg c0tximax;
	337	dv_reg c1rximax;
	338	dv_reg c1tximax;
	339	dv_reg c2rximax;
	340	dv_reg c2tximax;
7835f4b9	341	#else
c74b2108 SK	342	u_int8_t RSVD0[4100];
	343	dv_reg EWCTL;
	344	dv_reg EWINTTCNT;
7835f4b9	345	#endif
c74b2108 SK	346	} ewrap_regs;
c74b2108 SK	347
c74b2108 SK	348	/* EMAC MDIO Registers Structure */
	349	typedef struct {
	350	dv_reg VERSION;
	351	dv_reg CONTROL;
	352	dv_reg ALIVE;
	353	dv_reg LINK;
	354	dv_reg LINKINTRAW;
	355	dv_reg LINKINTMASKED;
	356	u_int8_t RSVD0[8];
	357	dv_reg USERINTRAW;
	358	dv_reg USERINTMASKED;
	359	dv_reg USERINTMASKSET;
	360	dv_reg USERINTMASKCLEAR;
	361	u_int8_t RSVD1[80];
	362	dv_reg USERACCESS0;
	363	dv_reg USERPHYSEL0;
	364	dv_reg USERACCESS1;
	365	dv_reg USERPHYSEL1;
	366	} mdio_regs;
	367
d6e04258 JCPV	368	int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
d6e04258 JCPV	369	int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
37cffdad	370	void davinci_eth_set_mac_addr(const u_int8_t *addr);
c74b2108 SK	371
	372	typedef struct
	373	{
	374	char name[64];
	375	int (*init)(int phy_addr);
	376	int (*is_phy_connected)(int phy_addr);
	377	int (*get_link_speed)(int phy_addr);
	378	int (*auto_negotiate)(int phy_addr);
	379	} phy_t;
	380
	381	#define PHY_LXT972 (0x001378e2)
	382	int lxt972_is_phy_connected(int phy_addr);
	383	int lxt972_get_link_speed(int phy_addr);
	384	int lxt972_init_phy(int phy_addr);
	385	int lxt972_auto_negotiate(int phy_addr);
	386
	387	#define PHY_DP83848 (0x20005c90)
	388	int dp83848_is_phy_connected(int phy_addr);
	389	int dp83848_get_link_speed(int phy_addr);
	390	int dp83848_init_phy(int phy_addr);
	391	int dp83848_auto_negotiate(int phy_addr);
	392
	393	#endif /* _DM644X_EMAC_H_ */