[people/ms/u-boot.git] / arch / arm / include / asm / arch-exynos / dp_info.h

/*
 * Copyright (C) 2012 Samsung Electronics
 *
 * Author: Donghwa Lee <dh09.lee@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef _DP_INFO_H
#define _DP_INFO_H

#define msleep(a)			udelay(a * 1000)

#define DP_TIMEOUT_LOOP_COUNT		100
#define MAX_CR_LOOP			5
#define MAX_EQ_LOOP			4

#define EXYNOS_DP_SUCCESS		0

enum {
	DP_DISABLE,
	DP_ENABLE,
};

struct edp_disp_info {
	char *name;
	unsigned int h_total;
	unsigned int h_res;
	unsigned int h_sync_width;
	unsigned int h_back_porch;
	unsigned int h_front_porch;
	unsigned int v_total;
	unsigned int v_res;
	unsigned int v_sync_width;
	unsigned int v_back_porch;
	unsigned int v_front_porch;

	unsigned int v_sync_rate;
};

struct edp_link_train_info {
	unsigned int lt_status;

	unsigned int ep_loop;
	unsigned int cr_loop[4];

};

struct edp_video_info {
	unsigned int master_mode;
	unsigned int bist_mode;
	unsigned int bist_pattern;

	unsigned int h_sync_polarity;
	unsigned int v_sync_polarity;
	unsigned int interlaced;

	unsigned int color_space;
	unsigned int dynamic_range;
	unsigned int ycbcr_coeff;
	unsigned int color_depth;
};

struct edp_device_info {
	struct edp_disp_info disp_info;
	struct edp_link_train_info lt_info;
	struct edp_video_info video_info;

	/*below info get from panel during training*/
	unsigned char lane_bw;
	unsigned char lane_cnt;
	unsigned char dpcd_rev;
	/*support enhanced frame cap */
	unsigned char dpcd_efc;
};

enum analog_power_block {
	AUX_BLOCK,
	CH0_BLOCK,
	CH1_BLOCK,
	CH2_BLOCK,
	CH3_BLOCK,
	ANALOG_TOTAL,
	POWER_ALL
};

enum pll_status {
	PLL_UNLOCKED = 0,
	PLL_LOCKED
};

enum {
	COLOR_RGB,
	COLOR_YCBCR422,
	COLOR_YCBCR444
};

enum {
	VESA,
	CEA
};

enum {
	COLOR_YCBCR601,
	COLOR_YCBCR709
};

enum {
	COLOR_6,
	COLOR_8,
	COLOR_10,
	COLOR_12
};

enum {
	DP_LANE_BW_1_62 = 0x06,
	DP_LANE_BW_2_70 = 0x0a,
};

enum {
	DP_LANE_CNT_1 = 1,
	DP_LANE_CNT_2 = 2,
	DP_LANE_CNT_4 = 4,
};

enum {
	DP_DPCD_REV_10 = 0x10,
	DP_DPCD_REV_11 = 0x11,
};

enum {
	DP_LT_NONE,
	DP_LT_START,
	DP_LT_CR,
	DP_LT_ET,
	DP_LT_FINISHED,
	DP_LT_FAIL,
};

enum  {
	PRE_EMPHASIS_LEVEL_0,
	PRE_EMPHASIS_LEVEL_1,
	PRE_EMPHASIS_LEVEL_2,
	PRE_EMPHASIS_LEVEL_3,
};

enum {
	PRBS7,
	D10_2,
	TRAINING_PTN1,
	TRAINING_PTN2,
	DP_NONE
};

enum {
	VOLTAGE_LEVEL_0,
	VOLTAGE_LEVEL_1,
	VOLTAGE_LEVEL_2,
	VOLTAGE_LEVEL_3,
};

enum pattern_type {
	NO_PATTERN,
	COLOR_RAMP,
	BALCK_WHITE_V_LINES,
	COLOR_SQUARE,
	INVALID_PATTERN,
	COLORBAR_32,
	COLORBAR_64,
	WHITE_GRAY_BALCKBAR_32,
	WHITE_GRAY_BALCKBAR_64,
	MOBILE_WHITEBAR_32,
	MOBILE_WHITEBAR_64
};

enum {
	CALCULATED_M,
	REGISTER_M
};

enum {
	VIDEO_TIMING_FROM_CAPTURE,
	VIDEO_TIMING_FROM_REGISTER
};


struct exynos_dp_platform_data {
	struct edp_device_info *edp_dev_info;
};

#ifdef CONFIG_EXYNOS_DP
unsigned int exynos_init_dp(void);
#else
unsigned int exynos_init_dp(void)
{
	return 0;
}
#endif

void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);

#endif /* _DP_INFO_H */
Commit	Line	Data
d2a6982f DL	1	/*
	2	* Copyright (C) 2012 Samsung Electronics
	3	*
	4	* Author: Donghwa Lee <dh09.lee@samsung.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
d2a6982f DL	7	*/
	8
	9	#ifndef _DP_INFO_H
	10	#define _DP_INFO_H
	11
	12	#define msleep(a) udelay(a * 1000)
	13
	14	#define DP_TIMEOUT_LOOP_COUNT 100
	15	#define MAX_CR_LOOP 5
	16	#define MAX_EQ_LOOP 4
	17
	18	#define EXYNOS_DP_SUCCESS 0
	19
	20	enum {
	21	DP_DISABLE,
	22	DP_ENABLE,
	23	};
	24
	25	struct edp_disp_info {
	26	char *name;
	27	unsigned int h_total;
	28	unsigned int h_res;
	29	unsigned int h_sync_width;
	30	unsigned int h_back_porch;
	31	unsigned int h_front_porch;
	32	unsigned int v_total;
	33	unsigned int v_res;
	34	unsigned int v_sync_width;
	35	unsigned int v_back_porch;
	36	unsigned int v_front_porch;
	37
	38	unsigned int v_sync_rate;
	39	};
	40
	41	struct edp_link_train_info {
	42	unsigned int lt_status;
	43
	44	unsigned int ep_loop;
	45	unsigned int cr_loop[4];
	46
	47	};
	48
	49	struct edp_video_info {
	50	unsigned int master_mode;
	51	unsigned int bist_mode;
	52	unsigned int bist_pattern;
	53
	54	unsigned int h_sync_polarity;
	55	unsigned int v_sync_polarity;
	56	unsigned int interlaced;
	57
	58	unsigned int color_space;
	59	unsigned int dynamic_range;
	60	unsigned int ycbcr_coeff;
	61	unsigned int color_depth;
	62	};
	63
	64	struct edp_device_info {
	65	struct edp_disp_info disp_info;
	66	struct edp_link_train_info lt_info;
	67	struct edp_video_info video_info;
	68
	69	/below info get from panel during training/
	70	unsigned char lane_bw;
71	unsigned char lane_cnt;
72	unsigned char dpcd_rev;
73	/support enhanced frame cap /
74	unsigned char dpcd_efc;
75	};
76
77	enum analog_power_block {
78	AUX_BLOCK,
79	CH0_BLOCK,
80	CH1_BLOCK,
81	CH2_BLOCK,
82	CH3_BLOCK,
83	ANALOG_TOTAL,
84	POWER_ALL
85	};
86
87	enum pll_status {
88	PLL_UNLOCKED = 0,
89	PLL_LOCKED
90	};
91
92	enum {
93	COLOR_RGB,
94	COLOR_YCBCR422,
95	COLOR_YCBCR444
96	};
97
98	enum {
99	VESA,
100	CEA
101	};
102
103	enum {
104	COLOR_YCBCR601,
105	COLOR_YCBCR709
106	};
107
108	enum {
109	COLOR_6,
110	COLOR_8,
111	COLOR_10,
112	COLOR_12
113	};
114
115	enum {
116	DP_LANE_BW_1_62 = 0x06,
117	DP_LANE_BW_2_70 = 0x0a,
118	};
119
120	enum {
121	DP_LANE_CNT_1 = 1,
122	DP_LANE_CNT_2 = 2,
123	DP_LANE_CNT_4 = 4,
124	};
125
126	enum {
127	DP_DPCD_REV_10 = 0x10,
128	DP_DPCD_REV_11 = 0x11,
129	};
130
131	enum {
132	DP_LT_NONE,
133	DP_LT_START,
134	DP_LT_CR,
135	DP_LT_ET,
136	DP_LT_FINISHED,
137	DP_LT_FAIL,
138	};
139
140	enum {
141	PRE_EMPHASIS_LEVEL_0,
142	PRE_EMPHASIS_LEVEL_1,
143	PRE_EMPHASIS_LEVEL_2,
144	PRE_EMPHASIS_LEVEL_3,
145	};
146
147	enum {
148	PRBS7,
149	D10_2,
150	TRAINING_PTN1,
151	TRAINING_PTN2,
152	DP_NONE
153	};
154
155	enum {
156	VOLTAGE_LEVEL_0,
157	VOLTAGE_LEVEL_1,
158	VOLTAGE_LEVEL_2,
159	VOLTAGE_LEVEL_3,
160	};
161
162	enum pattern_type {
163	NO_PATTERN,
164	COLOR_RAMP,
165	BALCK_WHITE_V_LINES,
166	COLOR_SQUARE,
167	INVALID_PATTERN,
168	COLORBAR_32,
169	COLORBAR_64,
170	WHITE_GRAY_BALCKBAR_32,
171	WHITE_GRAY_BALCKBAR_64,
172	MOBILE_WHITEBAR_32,
173	MOBILE_WHITEBAR_64
174	};
175
176	enum {
177	CALCULATED_M,
178	REGISTER_M
179	};
180
181	enum {
182	VIDEO_TIMING_FROM_CAPTURE,
183	VIDEO_TIMING_FROM_REGISTER
184	};
185
186
187	struct exynos_dp_platform_data {
188	struct edp_device_info *edp_dev_info;
d2a6982f DL	189	};
	190
	191	#ifdef CONFIG_EXYNOS_DP
	192	unsigned int exynos_init_dp(void);
	193	#else
	194	unsigned int exynos_init_dp(void)
	195	{
	196	return 0;
	197	}
	198	#endif
	199
9b572852 AK	200	void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
9b572852 AK	201
d2a6982f	202	#endif /* _DP_INFO_H */