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| Commit | Line | Data |
|---|---|---|
| b0ad8621 CK |
1 | /* |
| 2 | * (C) Copyright 2010 Samsung Electronics | |
| 3 | * Naveen Krishna Ch <ch.naveen@samsung.com> | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| b0ad8621 CK |
6 | * |
| 7 | * Note: This file contains the register description for SROMC | |
| b0ad8621 CK |
8 | */ |
| 9 | ||
| 10 | #ifndef __ASM_ARCH_SROMC_H_ | |
| 11 | #define __ASM_ARCH_SROMC_H_ | |
| 12 | ||
| 13 | #define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) | |
| 14 | #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ | |
| 15 | /* 1-> Byte base address*/ | |
| 16 | #define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) | |
| 17 | #define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) | |
| 18 | ||
| 19 | #define SROMC_BC_TACS(x) (x << 28) /* address set-up */ | |
| 20 | #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ | |
| 21 | #define SROMC_BC_TACC(x) (x << 16) /* access cycle */ | |
| 22 | #define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ | |
| 23 | #define SROMC_BC_TAH(x) (x << 8) /* address holding time */ | |
| 24 | #define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ | |
| 25 | #define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ | |
| 26 | ||
| 27 | #ifndef __ASSEMBLY__ | |
| 28 | struct s5p_sromc { | |
| 29 | unsigned int bw; | |
| 30 | unsigned int bc[4]; | |
| 31 | }; | |
| 32 | #endif /* __ASSEMBLY__ */ | |
| 33 | ||
| 34 | /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ | |
| 35 | void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); | |
| 36 | ||
| 3ea93948 HR |
37 | enum { |
| 38 | FDT_SROM_PMC, | |
| 39 | FDT_SROM_TACP, | |
| 40 | FDT_SROM_TAH, | |
| 41 | FDT_SROM_TCOH, | |
| 42 | FDT_SROM_TACC, | |
| 43 | FDT_SROM_TCOS, | |
| 44 | FDT_SROM_TACS, | |
| 45 | ||
| 46 | FDT_SROM_TIMING_COUNT, | |
| 47 | }; | |
| 48 | ||
| 49 | struct fdt_sromc { | |
| 50 | u8 bank; /* srom bank number */ | |
| 51 | u8 width; /* bus width in bytes */ | |
| 52 | unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ | |
| 53 | }; | |
| 54 | ||
| b0ad8621 | 55 | #endif /* __ASM_ARCH_SROMC_H_ */ |