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| Commit | Line | Data |
|---|---|---|
| 9f3183d2 MH |
1 | /* |
| 2 | * Copyright 2015, Freescale Semiconductor | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ | |
| 8 | #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ | |
| 9 | ||
| da28e58a | 10 | #include <linux/kconfig.h> |
| 9f3183d2 MH |
11 | #include <fsl_ddrc_version.h> |
| 12 | ||
| a8c9d66c SX |
13 | #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 |
| 14 | ||
| c107c0c0 YS |
15 | /* |
| 16 | * Reserve secure memory | |
| 17 | * To be aligned with MMU block size | |
| 18 | */ | |
| 19 | #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ | |
| 20 | ||
| 3c1d218a | 21 | #ifdef CONFIG_LS2080A |
| 9f3183d2 MH |
22 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } |
| 23 | #define SRDS_MAX_LANES 8 | |
| 9f3183d2 | 24 | #define CONFIG_SYS_PAGE_SIZE 0x10000 |
| 9f3183d2 MH |
25 | #ifndef L1_CACHE_BYTES |
| 26 | #define L1_CACHE_SHIFT 6 | |
| 27 | #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) | |
| 9ae836cd | 28 | #define CONFIG_FSL_TZASC_400 |
| 9f3183d2 MH |
29 | #endif |
| 30 | ||
| 6930be34 HZ |
31 | #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ |
| 32 | #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ | |
| 33 | #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ | |
| 9f3183d2 MH |
34 | |
| 35 | /* DDR */ | |
| 9f3183d2 MH |
36 | #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 37 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE | |
| 38 | ||
| 39 | #define CONFIG_SYS_FSL_CCSR_GUR_LE | |
| 40 | #define CONFIG_SYS_FSL_CCSR_SCFG_LE | |
| 41 | #define CONFIG_SYS_FSL_ESDHC_LE | |
| 42 | #define CONFIG_SYS_FSL_IFC_LE | |
| af523a0d | 43 | #define CONFIG_SYS_FSL_PEX_LUT_LE |
| 9f3183d2 MH |
44 | |
| 45 | #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN | |
| 46 | ||
| 47 | /* Generic Interrupt Controller Definitions */ | |
| 48 | #define GICD_BASE 0x06000000 | |
| 49 | #define GICR_BASE 0x06100000 | |
| 50 | ||
| 51 | /* SMMU Defintions */ | |
| 52 | #define SMMU_BASE 0x05000000 /* GR0 Base */ | |
| 53 | ||
| 3808190a SJ |
54 | /* SFP */ |
| 55 | #define CONFIG_SYS_FSL_SFP_VER_3_4 | |
| 56 | #define CONFIG_SYS_FSL_SFP_LE | |
| 2827d647 SJ |
57 | #define CONFIG_SYS_FSL_SRK_LE |
| 58 | ||
| 2827d647 SJ |
59 | /* Security Monitor */ |
| 60 | #define CONFIG_SYS_FSL_SEC_MON_LE | |
| 61 | ||
| fd6dbc98 SJ |
62 | /* Secure Boot */ |
| 63 | #define CONFIG_ESBC_HDR_LS | |
| 3808190a | 64 | |
| 809d343a SJ |
65 | /* DCFG - GUR */ |
| 66 | #define CONFIG_SYS_FSL_CCSR_GUR_LE | |
| 67 | ||
| 9f3183d2 MH |
68 | /* Cache Coherent Interconnect */ |
| 69 | #define CCI_MN_BASE 0x04000000 | |
| 70 | #define CCI_MN_RNF_NODEID_LIST 0x180 | |
| 71 | #define CCI_MN_DVM_DOMAIN_CTL 0x200 | |
| 72 | #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 | |
| 73 | ||
| 61bd2f75 YS |
74 | #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) |
| 75 | #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) | |
| 76 | #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ | |
| 77 | #define CCN_HN_F_SAM_NODEID_MASK 0x7f | |
| 78 | #define CCN_HN_F_SAM_NODEID_DDR0 0x4 | |
| 79 | #define CCN_HN_F_SAM_NODEID_DDR1 0xe | |
| 80 | ||
| 9f3183d2 MH |
81 | #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) |
| 82 | #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) | |
| 83 | #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) | |
| 84 | #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) | |
| 85 | #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) | |
| 86 | #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) | |
| 87 | ||
| 88 | #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) | |
| 89 | #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) | |
| 90 | #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) | |
| 91 | ||
| 2b690b98 PK |
92 | #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) |
| 93 | ||
| 9f3183d2 MH |
94 | /* TZ Protection Controller Definitions */ |
| 95 | #define TZPC_BASE 0x02200000 | |
| 96 | #define TZPCR0SIZE_BASE (TZPC_BASE) | |
| 97 | #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) | |
| 98 | #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) | |
| 99 | #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) | |
| 100 | #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) | |
| 101 | #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) | |
| 102 | #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) | |
| 103 | #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) | |
| 104 | #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) | |
| 105 | #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) | |
| 106 | ||
| b4017364 PK |
107 | #define DCSR_CGACRE5 0x700070914ULL |
| 108 | #define EPU_EPCMPR5 0x700060914ULL | |
| 109 | #define EPU_EPCCR5 0x700060814ULL | |
| 110 | #define EPU_EPSMCR5 0x700060228ULL | |
| 111 | #define EPU_EPECR5 0x700060314ULL | |
| 112 | #define EPU_EPCTR5 0x700060a14ULL | |
| 113 | #define EPU_EPGCR 0x700060000ULL | |
| 114 | ||
| 9f3183d2 | 115 | #define CONFIG_SYS_FSL_ERRATUM_A008751 |
| a994b3de | 116 | |
| 2ea3a448 | 117 | /* ARM A57 CORE ERRATA */ |
| 7711cc0a A |
118 | #define CONFIG_ARM_ERRATA_826974 |
| 119 | #define CONFIG_ARM_ERRATA_828024 | |
| 2ea3a448 A |
120 | #define CONFIG_ARM_ERRATA_829520 |
| 121 | #define CONFIG_ARM_ERRATA_833471 | |
| 122 | ||
| 404bf454 | 123 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |
| 86336e60 | 124 | #elif defined(CONFIG_FSL_LSCH2) |
| 8281c58f | 125 | #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ |
| 6930be34 HZ |
126 | #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ |
| 127 | #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ | |
| 8281c58f | 128 | |
| 3b6bf811 HZ |
129 | #define DCSR_DCFG_SBEESR2 0x20140534 |
| 130 | #define DCSR_DCFG_MBEESR2 0x20140544 | |
| 131 | ||
| 8281c58f | 132 | #define CONFIG_SYS_FSL_CCSR_SCFG_BE |
| 8281c58f MH |
133 | #define CONFIG_SYS_FSL_ESDHC_BE |
| 134 | #define CONFIG_SYS_FSL_WDOG_BE | |
| 135 | #define CONFIG_SYS_FSL_DSPI_BE | |
| 136 | #define CONFIG_SYS_FSL_QSPI_BE | |
| 86336e60 | 137 | #define CONFIG_SYS_FSL_CCSR_GUR_BE |
| af523a0d | 138 | #define CONFIG_SYS_FSL_PEX_LUT_BE |
| 86336e60 | 139 | |
| 86336e60 QG |
140 | /* SoC related */ |
| 141 | #ifdef CONFIG_LS1043A | |
| 86336e60 QG |
142 | #define CONFIG_SYS_FMAN_V3 |
| 143 | #define CONFIG_SYS_NUM_FMAN 1 | |
| 144 | #define CONFIG_SYS_NUM_FM1_DTSEC 7 | |
| 145 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
| 86336e60 QG |
146 | #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 147 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE | |
| 8281c58f MH |
148 | |
| 149 | #define QE_MURAM_SIZE 0x6000UL | |
| 150 | #define MAX_QE_RISC 1 | |
| 151 | #define QE_NUM_OF_SNUM 28 | |
| 152 | ||
| 86336e60 | 153 | #define CONFIG_SYS_FSL_IFC_BE |
| 8281c58f | 154 | #define CONFIG_SYS_FSL_SFP_VER_3_2 |
| 9711f528 | 155 | #define CONFIG_SYS_FSL_SEC_MON_BE |
| 8281c58f MH |
156 | #define CONFIG_SYS_FSL_SFP_BE |
| 157 | #define CONFIG_SYS_FSL_SRK_LE | |
| 158 | #define CONFIG_KEY_REVOCATION | |
| 159 | ||
| 160 | /* SMMU Defintions */ | |
| 161 | #define SMMU_BASE 0x09000000 | |
| 162 | ||
| 163 | /* Generic Interrupt Controller Definitions */ | |
| 164 | #define GICD_BASE 0x01401000 | |
| 165 | #define GICC_BASE 0x01402000 | |
| fa18ed76 WS |
166 | #define GICH_BASE 0x01404000 |
| 167 | #define GICV_BASE 0x01406000 | |
| 168 | #define GICD_SIZE 0x1000 | |
| 169 | #define GICC_SIZE 0x2000 | |
| 170 | #define GICH_SIZE 0x2000 | |
| 171 | #define GICV_SIZE 0x2000 | |
| 172 | #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN | |
| 173 | #define GICD_BASE_64K 0x01410000 | |
| 174 | #define GICC_BASE_64K 0x01420000 | |
| 175 | #define GICH_BASE_64K 0x01440000 | |
| 176 | #define GICV_BASE_64K 0x01460000 | |
| 177 | #define GICD_SIZE_64K 0x10000 | |
| 178 | #define GICC_SIZE_64K 0x20000 | |
| 179 | #define GICH_SIZE_64K 0x20000 | |
| 180 | #define GICV_SIZE_64K 0x20000 | |
| 181 | #endif | |
| 182 | ||
| 183 | #define DCFG_CCSR_SVR 0x1ee00a4 | |
| 184 | #define REV1_0 0x10 | |
| 185 | #define REV1_1 0x11 | |
| 186 | #define GIC_ADDR_BIT 31 | |
| 187 | #define SCFG_GIC400_ALIGN 0x1570188 | |
| 8281c58f | 188 | |
| 404bf454 | 189 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |
| b7f2bbff | 190 | |
| d26e34c4 | 191 | #elif defined(CONFIG_ARCH_LS1012A) |
| b7f2bbff PK |
192 | #define GICD_BASE 0x01401000 |
| 193 | #define GICC_BASE 0x01402000 | |
| d26e34c4 | 194 | |
| 7d559604 PK |
195 | #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 196 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE | |
| 197 | ||
| da28e58a | 198 | #elif defined(CONFIG_ARCH_LS1046A) |
| b528b937 MH |
199 | #define CONFIG_SYS_FMAN_V3 |
| 200 | #define CONFIG_SYS_NUM_FMAN 1 | |
| 201 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 | |
| 202 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
| b528b937 MH |
203 | #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 204 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE | |
| 205 | ||
| b528b937 MH |
206 | #define CONFIG_SYS_FSL_IFC_BE |
| 207 | #define CONFIG_SYS_FSL_SFP_VER_3_2 | |
| 208 | #define CONFIG_SYS_FSL_SNVS_LE | |
| 209 | #define CONFIG_SYS_FSL_SFP_BE | |
| 210 | #define CONFIG_SYS_FSL_SRK_LE | |
| 211 | #define CONFIG_KEY_REVOCATION | |
| 212 | ||
| 213 | /* SMMU Defintions */ | |
| 214 | #define SMMU_BASE 0x09000000 | |
| 215 | ||
| 216 | /* Generic Interrupt Controller Definitions */ | |
| 217 | #define GICD_BASE 0x01410000 | |
| 218 | #define GICC_BASE 0x01420000 | |
| 219 | ||
| 220 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 | |
| 5f5e8d92 | 221 | |
| 9f3183d2 MH |
222 | #else |
| 223 | #error SoC not defined | |
| 224 | #endif | |
| 86336e60 | 225 | #endif |
| 9f3183d2 MH |
226 | |
| 227 | #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ |