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Commit | Line | Data |
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6a99f03d FE |
1 | /* |
2 | * (C) Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
c398e750 PF |
7 | #define MXC_CPU_MX23 0x23 |
8 | #define MXC_CPU_MX25 0x25 | |
9 | #define MXC_CPU_MX27 0x27 | |
10 | #define MXC_CPU_MX28 0x28 | |
11 | #define MXC_CPU_MX31 0x31 | |
12 | #define MXC_CPU_MX35 0x35 | |
6a99f03d FE |
13 | #define MXC_CPU_MX51 0x51 |
14 | #define MXC_CPU_MX53 0x53 | |
15 | #define MXC_CPU_MX6SL 0x60 | |
16 | #define MXC_CPU_MX6DL 0x61 | |
05d54b82 | 17 | #define MXC_CPU_MX6SX 0x62 |
6a99f03d | 18 | #define MXC_CPU_MX6Q 0x63 |
8631c06e | 19 | #define MXC_CPU_MX6UL 0x64 |
65ce54be PF |
20 | #define MXC_CPU_MX6ULL 0x65 |
21 | #define MXC_CPU_MX6SOLO 0x66 /* dummy */ | |
7ce6d3c8 PF |
22 | #define MXC_CPU_MX6SLL 0x67 |
23 | #define MXC_CPU_MX6D 0x6A | |
d0acd993 PF |
24 | #define MXC_CPU_MX6DP 0x68 |
25 | #define MXC_CPU_MX6QP 0x69 | |
e25a0656 | 26 | #define MXC_CPU_MX7S 0x71 /* dummy ID */ |
c5752f73 | 27 | #define MXC_CPU_MX7D 0x72 |
37cf2152 | 28 | #define MXC_CPU_VF610 0xF6 /* dummy ID */ |
32c81ea6 | 29 | |
15c52b3d | 30 | #define MXC_SOC_MX6 0x60 |
c5752f73 | 31 | #define MXC_SOC_MX7 0x70 |
15c52b3d | 32 | |
fc5ad477 AA |
33 | #define CHIP_REV_1_0 0x10 |
34 | #define CHIP_REV_1_1 0x11 | |
35 | #define CHIP_REV_1_2 0x12 | |
36 | #define CHIP_REV_1_5 0x15 | |
37 | #define CHIP_REV_2_0 0x20 | |
38 | #define CHIP_REV_2_5 0x25 | |
39 | #define CHIP_REV_3_0 0x30 | |
40 | ||
41 | #define BOARD_REV_1_0 0x0 | |
42 | #define BOARD_REV_2_0 0x1 | |
43 | #define BOARD_VER_OFFSET 0x8 | |
44 | ||
32c81ea6 FE |
45 | #define CS0_128 0 |
46 | #define CS0_64M_CS1_64M 1 | |
47 | #define CS0_64M_CS1_32M_CS2_32M 2 | |
48 | #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 | |
11c2e505 EN |
49 | |
50 | u32 get_imx_reset_cause(void); |