[people/ms/u-boot.git] / arch / arm / include / asm / arch-kirkwood / config.h

/*
 * (C) Copyright 2011
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Lei Wen <leiwen@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file should be included in board config header file.
 *
 * It supports common definitions for Kirkwood platform
 */

#ifndef _KW_CONFIG_H
#define _KW_CONFIG_H

#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)
#include <asm/arch/kw88f6192.h>
#else
#error "SOC Name not defined"
#endif /* CONFIG_KW88F6281 */

#include <asm/arch/kirkwood.h>
#define CONFIG_ARM926EJS	1	/* Basic Architecture */
#define CONFIG_SYS_CACHELINE_SIZE	32
				/* default Dcache Line length for kirkwood */
#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */

/*
 * By default kwbimage.cfg from board specific folder is used
 * If for some board, different configuration file need to be used,
 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
 */
#ifndef CONFIG_SYS_KWD_CONFIG
#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */

/* Kirkwood has 2k of Security SRAM, use it for SP */
#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
#define CONFIG_NR_DRAM_BANKS_MAX	2

#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
#define MV_SATA_BASE		KW_SATA_BASE
#define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
#define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET

/*
 * NAND configuration
 */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_KIRKWOOD
#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL		1
#endif

/*
 * SPI Flash configuration
 */
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI			1
#define CONFIG_KIRKWOOD_SPI		1
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS		0
#endif
#ifndef CONFIG_ENV_SPI_CS
# define CONFIG_ENV_SPI_CS		0
#endif
#ifndef CONFIG_ENV_SPI_MAX_HZ
# define CONFIG_ENV_SPI_MAX_HZ		50000000
#endif
#endif

/*
 * Ethernet Driver configuration
 */
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define CONFIG_MII		/* expose smi ove miiphy interface */
#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
#endif /* CONFIG_CMD_NET */

/*
 * USB/EHCI
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MARVELL
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */

/*
 * IDE Support on SATA ports
 */
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_CMD_EXT2
#define CONFIG_MVSATA_IDE
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE		4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS		2
#define CONFIG_SYS_IDE_MAXDEVICE	2
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
#endif /* CONFIG_CMD_IDE */

/*
 * I2C related stuff
 */
#ifdef CONFIG_CMD_I2C
#ifndef CONFIG_SOFT_I2C
#define CONFIG_I2C_MVTWSI
#endif
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000
#endif

#endif /* _KW_CONFIG_H */
Commit	Line	Data
cf946c6d LW	1	/*
	2	* (C) Copyright 2011
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Lei Wen <leiwen@marvell.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
cf946c6d LW	7	*/
	8
	9	/*
	10	* This file should be included in board config header file.
	11	*
	12	* It supports common definitions for Kirkwood platform
	13	*/
	14
	15	#ifndef _KW_CONFIG_H
	16	#define _KW_CONFIG_H
	17
	18	#if defined (CONFIG_KW88F6281)
	19	#include <asm/arch/kw88f6281.h>
	20	#elif defined (CONFIG_KW88F6192)
	21	#include <asm/arch/kw88f6192.h>
	22	#else
	23	#error "SOC Name not defined"
	24	#endif /* CONFIG_KW88F6281 */
	25
a7efd719	26	#include <asm/arch/kirkwood.h>
cf946c6d	27	#define CONFIG_ARM926EJS 1 /* Basic Architecture */
f779d739 MW	28	#define CONFIG_SYS_CACHELINE_SIZE 32
f779d739 MW	29	/* default Dcache Line length for kirkwood */
cf946c6d LW	30	#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
	31	#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
	32	#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
	33	#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
	34
	35	/*
	36	* By default kwbimage.cfg from board specific folder is used
	37	* If for some board, different configuration file need to be used,
	38	* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
	39	*/
	40	#ifndef CONFIG_SYS_KWD_CONFIG
	41	#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
	42	#endif /* CONFIG_SYS_KWD_CONFIG */
	43
	44	/* Kirkwood has 2k of Security SRAM, use it for SP */
	45	#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
	46	#define CONFIG_NR_DRAM_BANKS_MAX 2
	47
	48	#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
	49	#define MV_UART_CONSOLE_BASE KW_UART0_BASE
	50	#define MV_SATA_BASE KW_SATA_BASE
	51	#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
	52	#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
	53
	54	/*
	55	* NAND configuration
	56	*/
	57	#ifdef CONFIG_CMD_NAND
	58	#define CONFIG_NAND_KIRKWOOD
	59	#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
	60	#define NAND_ALLOW_ERASE_ALL 1
	61	#endif
	62
	63	/*
	64	* SPI Flash configuration
	65	*/
	66	#ifdef CONFIG_CMD_SF
	67	#define CONFIG_HARD_SPI 1
	68	#define CONFIG_KIRKWOOD_SPI 1
dacc8c6f VL	69	#ifndef CONFIG_ENV_SPI_BUS
	70	# define CONFIG_ENV_SPI_BUS 0
	71	#endif
	72	#ifndef CONFIG_ENV_SPI_CS
	73	# define CONFIG_ENV_SPI_CS 0
	74	#endif
	75	#ifndef CONFIG_ENV_SPI_MAX_HZ
	76	# define CONFIG_ENV_SPI_MAX_HZ 50000000
	77	#endif
cf946c6d LW	78	#endif
	79
	80	/*
	81	* Ethernet Driver configuration
	82	*/
	83	#ifdef CONFIG_CMD_NET
	84	#define CONFIG_CMD_MII
	85	#define CONFIG_NETCONSOLE /* include NetConsole support */
cf946c6d LW	86	#define CONFIG_MII /* expose smi ove miiphy interface */
	87	#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
	88	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
	89	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
	90	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
	91	#endif /* CONFIG_CMD_NET */
	92
	93	/*
	94	* USB/EHCI
	95	*/
	96	#ifdef CONFIG_CMD_USB
a14bd417	97	#define CONFIG_USB_EHCI_MARVELL
cf946c6d LW	98	#define CONFIG_EHCI_IS_TDI
	99	#endif /* CONFIG_CMD_USB */
	100
	101	/*
	102	* IDE Support on SATA ports
	103	*/
	104	#ifdef CONFIG_CMD_IDE
	105	#define __io
	106	#define CONFIG_CMD_EXT2
	107	#define CONFIG_MVSATA_IDE
	108	#define CONFIG_IDE_PREINIT
	109	#define CONFIG_MVSATA_IDE_USE_PORT1
	110	/* Needs byte-swapping for ATA data register */
	111	#define CONFIG_IDE_SWAP_IO
	112	/* Data, registers and alternate blocks are at the same offset */
	113	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
	114	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
	115	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
	116	/* Each 8-bit ATA register is aligned to a 4-bytes address */
	117	#define CONFIG_SYS_ATA_STRIDE 4
	118	/* Controller supports 48-bits LBA addressing */
	119	#define CONFIG_LBA48
	120	/* CONFIG_CMD_IDE requires some #defines for ATA registers */
	121	#define CONFIG_SYS_IDE_MAXBUS 2
	122	#define CONFIG_SYS_IDE_MAXDEVICE 2
	123	/* ATA registers base is at SATA controller base */
	124	#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
	125	#endif /* CONFIG_CMD_IDE */
	126
	127	/*
	128	* I2C related stuff
	129	*/
	130	#ifdef CONFIG_CMD_I2C
b31a82e9	131	#ifndef CONFIG_SOFT_I2C
cf946c6d	132	#define CONFIG_I2C_MVTWSI
b31a82e9	133	#endif
cf946c6d LW	134	#define CONFIG_SYS_I2C_SLAVE 0x0
	135	#define CONFIG_SYS_I2C_SPEED 100000
	136	#endif
	137
	138	#endif /* _KW_CONFIG_H */