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52f69f81 VZ |
1 | /* |
2 | * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
52f69f81 VZ |
5 | */ |
6 | ||
7 | #ifndef _LPC32XX_CPU_H | |
8 | #define _LPC32XX_CPU_H | |
9 | ||
10 | /* LPC32XX Memory map */ | |
11 | ||
12 | /* AHB physical base addresses */ | |
13 | #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ | |
14 | #define SSP0_BASE 0x20084000 /* SSP0 registers base */ | |
15 | #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ | |
16 | #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ | |
17 | #define DMA_BASE 0x31000000 /* DMA controller registers base */ | |
18 | #define USB_BASE 0x31020000 /* USB registers base */ | |
19 | #define LCD_BASE 0x31040000 /* LCD registers base */ | |
20 | #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ | |
21 | #define EMC_BASE 0x31080000 /* EMC configuration registers base */ | |
22 | ||
23 | /* FAB peripherals base addresses */ | |
24 | #define CLK_PM_BASE 0x40004000 /* System control registers base */ | |
25 | #define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ | |
26 | #define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ | |
27 | #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ | |
28 | #define RTC_BASE 0x40024000 /* RTC registers base */ | |
29 | #define GPIO_BASE 0x40028000 /* GPIO registers base */ | |
30 | #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ | |
31 | #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ | |
32 | #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ | |
33 | #define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ | |
34 | ||
35 | /* APB peripherals base addresses */ | |
36 | #define UART3_BASE 0x40080000 /* UART 3 registers base */ | |
37 | #define UART4_BASE 0x40088000 /* UART 4 registers base */ | |
38 | #define UART5_BASE 0x40090000 /* UART 5 registers base */ | |
39 | #define UART6_BASE 0x40098000 /* UART 6 registers base */ | |
40 | ||
41 | /* External SDRAM Memory Bank base addresses */ | |
42 | #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ | |
43 | #define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ | |
44 | ||
45 | /* External Static Memory Bank base addresses */ | |
46 | #define EMC_CS0_BASE 0xE0000000 | |
47 | #define EMC_CS1_BASE 0xE1000000 | |
48 | #define EMC_CS2_BASE 0xE2000000 | |
49 | #define EMC_CS3_BASE 0xE3000000 | |
50 | ||
51 | #endif /* _LPC32XX_CPU_H */ |