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1/*
2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
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5 */
6
7#ifndef _LPC32XX_WDT_H
8#define _LPC32XX_WDT_H
9
10#include <asm/types.h>
11
12/* Watchdog Timer Registers */
13struct wdt_regs {
14 u32 isr; /* Interrupt Status Register */
15 u32 ctrl; /* Control Register */
16 u32 counter; /* Counter Value Register */
17 u32 mctrl; /* Match Control Register */
18 u32 match0; /* Match 0 Register */
19 u32 emr; /* External Match Control Register */
20 u32 pulse; /* Reset Pulse Length Register */
21 u32 res; /* Reset Source Register */
22};
23
24/* Watchdog Timer Control Register bits */
25#define WDTIM_CTRL_PAUSE_EN (1 << 2)
26#define WDTIM_CTRL_RESET_COUNT (1 << 1)
27#define WDTIM_CTRL_COUNT_ENAB (1 << 0)
28
29/* Watchdog Timer Match Control Register bits */
30#define WDTIM_MCTRL_RESFRC2 (1 << 6)
31#define WDTIM_MCTRL_RESFRC1 (1 << 5)
32#define WDTIM_MCTRL_M_RES2 (1 << 4)
33#define WDTIM_MCTRL_M_RES1 (1 << 3)
34#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2)
35#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1)
36#define WDTIM_MCTRL_MR0_INT (1 << 0)
37
38#endif /* _LPC32XX_WDT_H */