[people/ms/u-boot.git] / arch / arm / include / asm / arch-mx25 / imx-regs.h

/*
 * Copyright (C) 2009, DENX Software Engineering
 * Author: John Rigby <jcrigby@gmail.com
 *
 *   Based on arch-mx31/mx31-regs.h
 *	Copyright (C) 2009 Ilya Yanok,
 *		Emcraft Systems <yanok@emcraft.com>
 *   and arch-mx27/imx-regs.h
 *	Copyright (C) 2007 Pengutronix,
 *		Sascha Hauer <s.hauer@pengutronix.de>
 *	Copyright (C) 2009 Ilya Yanok,
 *		Emcraft Systems <yanok@emcraft.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _IMX_REGS_H
#define _IMX_REGS_H

#ifndef __ASSEMBLY__
#ifdef CONFIG_FEC_MXC
extern void mx25_fec_init_pins(void);
#endif

/* Clock Control Module (CCM) registers */
struct ccm_regs {
	u32 mpctl;	/* Core PLL Control */
	u32 upctl;	/* USB PLL Control */
	u32 cctl;	/* Clock Control */
	u32 cgr0;	/* Clock Gating Control 0 */
	u32 cgr1;	/* Clock Gating Control 1 */
	u32 cgr2;	/* Clock Gating Control 2 */
	u32 pcdr[4];	/* PER Clock Dividers */
	u32 rcsr;	/* CCM Status */
	u32 crdr;	/* CCM Reset and Debug */
	u32 dcvr0;	/* DPTC Comparator Value 0 */
	u32 dcvr1;	/* DPTC Comparator Value 1 */
	u32 dcvr2;	/* DPTC Comparator Value 2 */
	u32 dcvr3;	/* DPTC Comparator Value 3 */
	u32 ltr0;	/* Load Tracking 0 */
	u32 ltr1;	/* Load Tracking 1 */
	u32 ltr2;	/* Load Tracking 2 */
	u32 ltr3;	/* Load Tracking 3 */
	u32 ltbr0;	/* Load Tracking Buffer 0 */
	u32 ltbr1;	/* Load Tracking Buffer 1 */
	u32 pcmr0;	/* Power Management Control 0 */
	u32 pcmr1;	/* Power Management Control 1 */
	u32 pcmr2;	/* Power Management Control 2 */
	u32 mcr;	/* Miscellaneous Control */
	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
};

/* Enhanced SDRAM Controller (ESDRAMC) registers */
struct esdramc_regs {
	u32 ctl0; 	/* control 0 */
	u32 cfg0; 	/* configuration 0 */
	u32 ctl1; 	/* control 1 */
	u32 cfg1; 	/* configuration 1 */
	u32 misc; 	/* miscellaneous */
	u32 pad[3];
	u32 cdly1;	/* Delay Line 1 configuration debug */
	u32 cdly2;	/* delay line 2 configuration debug */
	u32 cdly3;	/* delay line 3 configuration debug */
	u32 cdly4;	/* delay line 4 configuration debug */
	u32 cdly5;	/* delay line 5 configuration debug */
	u32 cdlyl;	/* delay line cycle length debug */
};

/* GPIO registers */
struct gpio_regs {
	u32 dr;		/* data */
	u32 dir;	/* direction */
	u32 psr;	/* pad satus */
	u32 icr1;	/* interrupt config 1 */
	u32 icr2;	/* interrupt config 2 */
	u32 imr;	/* interrupt mask */
	u32 isr;	/* interrupt status */
	u32 edge_sel;	/* edge select */
};

/* General Purpose Timer (GPT) registers */
struct gpt_regs {
	u32 ctrl;   	/* control */
	u32 pre;    	/* prescaler */
	u32 stat;   	/* status */
	u32 intr;   	/* interrupt */
	u32 cmp[3]; 	/* output compare 1-3 */
	u32 capt[2];	/* input capture 1-2 */
	u32 counter;	/* counter */
};

/* Watchdog Timer (WDOG) registers */
struct wdog_regs {
	u32 wcr;	/* Control */
	u32 wsr;	/* Service */
	u32 wrsr;	/* Reset Status */
	u32 wicr;	/* Interrupt Control */
	u32 wmcr;	/* Misc Control */
};

/* IIM control registers */
struct iim_regs {
	u32 iim_stat;
	u32 iim_statm;
	u32 iim_err;
	u32 iim_emask;
	u32 iim_fctl;
	u32 iim_ua;
	u32 iim_la;
	u32 iim_sdat;
	u32 iim_prev;
	u32 iim_srev;
	u32 iim_prog_p;
	u32 res1[0x1f5];
	u32 iim_bank_area0[0x20];
	u32 res2[0xe0];
	u32 iim_bank_area1[0x20];
	u32 res3[0xe0];
	u32 iim_bank_area2[0x20];
};
#endif

/* AIPS 1 */
#define IMX_AIPS1_BASE		(0x43F00000)
#define IMX_MAX_BASE		(0x43F04000)
#define IMX_CLKCTL_BASE		(0x43F08000)
#define IMX_ETB_SLOT4_BASE	(0x43F0C000)
#define IMX_ETB_SLOT5_BASE	(0x43F10000)
#define IMX_ECT_CTIO_BASE	(0x43F18000)
#define IMX_I2C_BASE		(0x43F80000)
#define IMX_I2C3_BASE		(0x43F84000)
#define IMX_CAN1_BASE		(0x43F88000)
#define IMX_CAN2_BASE		(0x43F8C000)
#define IMX_UART1_BASE		(0x43F90000)
#define IMX_UART2_BASE		(0x43F94000)
#define IMX_I2C2_BASE		(0x43F98000)
#define IMX_OWIRE_BASE		(0x43F9C000)
#define IMX_CSPI1_BASE		(0x43FA4000)
#define IMX_KPP_BASE		(0x43FA8000)
#define IMX_IOPADMUX_BASE	(0x43FAC000)
#define IMX_IOPADCTL_BASE	(0x43FAC22C)
#define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
#define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
#define IMX_AUDMUX_BASE		(0x43FB0000)
#define IMX_ECT_IP1_BASE	(0x43FB8000)
#define IMX_ECT_IP2_BASE	(0x43FBC000)

/* SPBA */
#define IMX_SPBA_BASE		(0x50000000)
#define IMX_CSPI3_BASE		(0x50004000)
#define IMX_UART4_BASE		(0x50008000)
#define IMX_UART3_BASE		(0x5000C000)
#define IMX_CSPI2_BASE		(0x50010000)
#define IMX_SSI2_BASE		(0x50014000)
#define IMX_ESAI_BASE		(0x50018000)
#define IMX_ATA_DMA_BASE	(0x50020000)
#define IMX_SIM1_BASE		(0x50024000)
#define IMX_SIM2_BASE		(0x50028000)
#define IMX_UART5_BASE		(0x5002C000)
#define IMX_TSC_BASE		(0x50030000)
#define IMX_SSI1_BASE		(0x50034000)
#define IMX_FEC_BASE		(0x50038000)
#define IMX_SPBA_CTRL_BASE	(0x5003C000)

/* AIPS 2 */
#define IMX_AIPS2_BASE		(0x53F00000)
#define IMX_CCM_BASE		(0x53F80000)
#define IMX_GPT4_BASE		(0x53F84000)
#define IMX_GPT3_BASE		(0x53F88000)
#define IMX_GPT2_BASE		(0x53F8C000)
#define IMX_GPT1_BASE		(0x53F90000)
#define IMX_EPIT1_BASE		(0x53F94000)
#define IMX_EPIT2_BASE		(0x53F98000)
#define IMX_GPIO4_BASE		(0x53F9C000)
#define IMX_PWM2_BASE		(0x53FA0000)
#define IMX_GPIO3_BASE		(0x53FA4000)
#define IMX_PWM3_BASE		(0x53FA8000)
#define IMX_SCC_BASE		(0x53FAC000)
#define IMX_SCM_BASE		(0x53FAE000)
#define IMX_SMN_BASE		(0x53FAF000)
#define IMX_RNGD_BASE		(0x53FB0000)
#define IMX_MMC_SDHC1_BASE	(0x53FB4000)
#define IMX_MMC_SDHC2_BASE	(0x53FB8000)
#define IMX_LCDC_BASE		(0x53FBC000)
#define IMX_SLCDC_BASE		(0x53FC0000)
#define IMX_PWM4_BASE		(0x53FC8000)
#define IMX_GPIO1_BASE		(0x53FCC000)
#define IMX_GPIO2_BASE		(0x53FD0000)
#define IMX_SDMA_BASE		(0x53FD4000)
#define IMX_WDT_BASE		(0x53FDC000)
#define IMX_PWM1_BASE		(0x53FE0000)
#define IMX_RTIC_BASE		(0x53FEC000)
#define IMX_IIM_BASE		(0x53FF0000)
#define IMX_USB_BASE		(0x53FF4000)
#define IMX_CSI_BASE		(0x53FF8000)
#define IMX_DRYICE_BASE		(0x53FFC000)

#define IMX_ARM926_ROMPATCH	(0x60000000)
#define IMX_ARM926_ASIC		(0x68000000)

/* 128K Internal Static RAM */
#define IMX_RAM_BASE		(0x78000000)

/* SDRAM BANKS */
#define IMX_SDRAM_BANK0_BASE	(0x80000000)
#define IMX_SDRAM_BANK1_BASE	(0x90000000)

#define IMX_WEIM_CS0		(0xA0000000)
#define IMX_WEIM_CS1		(0xA8000000)
#define IMX_WEIM_CS2		(0xB0000000)
#define IMX_WEIM_CS3		(0xB2000000)
#define IMX_WEIM_CS4		(0xB4000000)
#define IMX_ESDRAMC_BASE	(0xB8001000)
#define IMX_WEIM_CTRL_BASE	(0xB8002000)
#define IMX_M3IF_CTRL_BASE	(0xB8003000)
#define IMX_EMI_CTRL_BASE	(0xB8004000)

/* NAND Flash Controller */
#define IMX_NFC_BASE		(0xBB000000)
#define NFC_BASE_ADDR		IMX_NFC_BASE

/* CCM bitfields */
#define CCM_PLL_MFI_SHIFT	10
#define CCM_PLL_MFI_MASK	0xf
#define CCM_PLL_MFN_SHIFT	0
#define CCM_PLL_MFN_MASK	0x3ff
#define CCM_PLL_MFD_SHIFT	16
#define CCM_PLL_MFD_MASK	0x3ff
#define CCM_PLL_PD_SHIFT	26
#define CCM_PLL_PD_MASK		0xf
#define CCM_CCTL_ARM_DIV_SHIFT	30
#define CCM_CCTL_ARM_DIV_MASK	3
#define CCM_CCTL_AHB_DIV_SHIFT	28
#define CCM_CCTL_AHB_DIV_MASK	3
#define CCM_CCTL_ARM_SRC	(1 << 14)
#define CCM_CGR1_GPT1		(1 << 19)
#define CCM_PERCLK_REG(clk)	(clk / 4)
#define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
#define CCM_PERCLK_MASK		0x3f
#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
#define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)

/* ESDRAM Controller register bitfields */
#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
#define ESDCTL_BL		(1 << 7)
#define ESDCTL_FP		(1 << 8)
#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
#define ESDCTL_DSIZ_32		(2 << 16)
#define ESDCTL_COL8		(0 << 20)
#define ESDCTL_COL9		(1 << 20)
#define ESDCTL_COL10		(2 << 20)
#define ESDCTL_ROW11		(0 << 24)
#define ESDCTL_ROW12		(1 << 24)
#define ESDCTL_ROW13		(2 << 24)
#define ESDCTL_ROW14		(3 << 24)
#define ESDCTL_ROW15		(4 << 24)
#define ESDCTL_SP		(1 << 27)
#define ESDCTL_SMODE_NORMAL	(0 << 28)
#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
#define ESDCTL_SMODE_MAN_REF	(4 << 28)
#define ESDCTL_SDE		(1 << 31)

#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
#define ESDCFG_TWR		(1 << 15)
#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
#define ESDCFG_TWTR		(1 << 20)
#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)

#define ESDMISC_RST		(1 << 1)
#define ESDMISC_MDDREN		(1 << 2)
#define ESDMISC_MDDR_DL_RST	(1 << 3)
#define ESDMISC_MDDR_MDIS	(1 << 4)
#define ESDMISC_LHD		(1 << 5)
#define ESDMISC_MA10_SHARE	(1 << 6)
#define ESDMISC_SDRAM_RDY	(1 << 31)

/* GPT bits */
#define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
#define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
#define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
#define GPT_CTRL_TEN		1		/* Timer enable	*/

/* WDOG enable */
#define WCR_WDE 0x04

/* FUSE bank offsets */
#define IIM0_MAC		0x1a

#endif				/* _IMX_REGS_H */
Commit	Line	Data
552ff8f1 JR	1	/*
	2	* Copyright (C) 2009, DENX Software Engineering
	3	* Author: John Rigby <jcrigby@gmail.com
	4	*
	5	* Based on arch-mx31/mx31-regs.h
	6	* Copyright (C) 2009 Ilya Yanok,
	7	* Emcraft Systems <yanok@emcraft.com>
	8	* and arch-mx27/imx-regs.h
	9	* Copyright (C) 2007 Pengutronix,
	10	* Sascha Hauer <s.hauer@pengutronix.de>
	11	* Copyright (C) 2009 Ilya Yanok,
	12	* Emcraft Systems <yanok@emcraft.com>
	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32
	33	#ifndef _IMX_REGS_H
	34	#define _IMX_REGS_H
	35
	36	#ifndef __ASSEMBLY__
	37	#ifdef CONFIG_FEC_MXC
	38	extern void mx25_fec_init_pins(void);
	39	#endif
	40
	41	/* Clock Control Module (CCM) registers */
	42	struct ccm_regs {
	43	u32 mpctl; /* Core PLL Control */
	44	u32 upctl; /* USB PLL Control */
	45	u32 cctl; /* Clock Control */
	46	u32 cgr0; /* Clock Gating Control 0 */
	47	u32 cgr1; /* Clock Gating Control 1 */
	48	u32 cgr2; /* Clock Gating Control 2 */
	49	u32 pcdr[4]; /* PER Clock Dividers */
	50	u32 rcsr; /* CCM Status */
	51	u32 crdr; /* CCM Reset and Debug */
	52	u32 dcvr0; /* DPTC Comparator Value 0 */
	53	u32 dcvr1; /* DPTC Comparator Value 1 */
	54	u32 dcvr2; /* DPTC Comparator Value 2 */
	55	u32 dcvr3; /* DPTC Comparator Value 3 */
	56	u32 ltr0; /* Load Tracking 0 */
	57	u32 ltr1; /* Load Tracking 1 */
	58	u32 ltr2; /* Load Tracking 2 */
	59	u32 ltr3; /* Load Tracking 3 */
	60	u32 ltbr0; /* Load Tracking Buffer 0 */
	61	u32 ltbr1; /* Load Tracking Buffer 1 */
	62	u32 pcmr0; /* Power Management Control 0 */
	63	u32 pcmr1; /* Power Management Control 1 */
	64	u32 pcmr2; /* Power Management Control 2 */
65	u32 mcr; /* Miscellaneous Control */
66	u32 lpimr0; /* Low Power Interrupt Mask 0 */
67	u32 lpimr1; /* Low Power Interrupt Mask 1 */
68	};
69
70	/* Enhanced SDRAM Controller (ESDRAMC) registers */
71	struct esdramc_regs {
72	u32 ctl0; /* control 0 */
73	u32 cfg0; /* configuration 0 */
74	u32 ctl1; /* control 1 */
75	u32 cfg1; /* configuration 1 */
76	u32 misc; /* miscellaneous */
77	u32 pad[3];
78	u32 cdly1; /* Delay Line 1 configuration debug */
79	u32 cdly2; /* delay line 2 configuration debug */
80	u32 cdly3; /* delay line 3 configuration debug */
81	u32 cdly4; /* delay line 4 configuration debug */
82	u32 cdly5; /* delay line 5 configuration debug */
83	u32 cdlyl; /* delay line cycle length debug */
84	};
85
86	/* GPIO registers */
87	struct gpio_regs {
88	u32 dr; /* data */
89	u32 dir; /* direction */
90	u32 psr; /* pad satus */
91	u32 icr1; /* interrupt config 1 */
92	u32 icr2; /* interrupt config 2 */
93	u32 imr; /* interrupt mask */
94	u32 isr; /* interrupt status */
95	u32 edge_sel; /* edge select */
96	};
97
98	/* General Purpose Timer (GPT) registers */
99	struct gpt_regs {
100	u32 ctrl; /* control */
101	u32 pre; /* prescaler */
102	u32 stat; /* status */
103	u32 intr; /* interrupt */
104	u32 cmp[3]; /* output compare 1-3 */
105	u32 capt[2]; /* input capture 1-2 */
106	u32 counter; /* counter */
107	};
108
109	/* Watchdog Timer (WDOG) registers */
110	struct wdog_regs {
111	u32 wcr; /* Control */
112	u32 wsr; /* Service */
113	u32 wrsr; /* Reset Status */
114	u32 wicr; /* Interrupt Control */
115	u32 wmcr; /* Misc Control */
116	};
117
118	/* IIM control registers */
119	struct iim_regs {
120	u32 iim_stat;
121	u32 iim_statm;
122	u32 iim_err;
123	u32 iim_emask;
124	u32 iim_fctl;
125	u32 iim_ua;
126	u32 iim_la;
127	u32 iim_sdat;
128	u32 iim_prev;
129	u32 iim_srev;
130	u32 iim_prog_p;
131	u32 res1[0x1f5];
132	u32 iim_bank_area0[0x20];
133	u32 res2[0xe0];
134	u32 iim_bank_area1[0x20];
135	u32 res3[0xe0];
136	u32 iim_bank_area2[0x20];
137	};
138	#endif
139
140	/* AIPS 1 */
141	#define IMX_AIPS1_BASE (0x43F00000)
142	#define IMX_MAX_BASE (0x43F04000)
143	#define IMX_CLKCTL_BASE (0x43F08000)
144	#define IMX_ETB_SLOT4_BASE (0x43F0C000)
145	#define IMX_ETB_SLOT5_BASE (0x43F10000)
146	#define IMX_ECT_CTIO_BASE (0x43F18000)
147	#define IMX_I2C_BASE (0x43F80000)
148	#define IMX_I2C3_BASE (0x43F84000)
149	#define IMX_CAN1_BASE (0x43F88000)
150	#define IMX_CAN2_BASE (0x43F8C000)
151	#define IMX_UART1_BASE (0x43F90000)
152	#define IMX_UART2_BASE (0x43F94000)
153	#define IMX_I2C2_BASE (0x43F98000)
154	#define IMX_OWIRE_BASE (0x43F9C000)
155	#define IMX_CSPI1_BASE (0x43FA4000)
156	#define IMX_KPP_BASE (0x43FA8000)
157	#define IMX_IOPADMUX_BASE (0x43FAC000)
158	#define IMX_IOPADCTL_BASE (0x43FAC22C)
159	#define IMX_IOPADGRPCTL_BASE (0x43FAC418)
160	#define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
161	#define IMX_AUDMUX_BASE (0x43FB0000)
162	#define IMX_ECT_IP1_BASE (0x43FB8000)
163	#define IMX_ECT_IP2_BASE (0x43FBC000)
164
165	/* SPBA */
166	#define IMX_SPBA_BASE (0x50000000)
167	#define IMX_CSPI3_BASE (0x50004000)
168	#define IMX_UART4_BASE (0x50008000)
169	#define IMX_UART3_BASE (0x5000C000)
170	#define IMX_CSPI2_BASE (0x50010000)
171	#define IMX_SSI2_BASE (0x50014000)
172	#define IMX_ESAI_BASE (0x50018000)
173	#define IMX_ATA_DMA_BASE (0x50020000)
174	#define IMX_SIM1_BASE (0x50024000)
175	#define IMX_SIM2_BASE (0x50028000)
176	#define IMX_UART5_BASE (0x5002C000)
177	#define IMX_TSC_BASE (0x50030000)
178	#define IMX_SSI1_BASE (0x50034000)
179	#define IMX_FEC_BASE (0x50038000)
180	#define IMX_SPBA_CTRL_BASE (0x5003C000)
181
182	/* AIPS 2 */
183	#define IMX_AIPS2_BASE (0x53F00000)
184	#define IMX_CCM_BASE (0x53F80000)
185	#define IMX_GPT4_BASE (0x53F84000)
186	#define IMX_GPT3_BASE (0x53F88000)
187	#define IMX_GPT2_BASE (0x53F8C000)
188	#define IMX_GPT1_BASE (0x53F90000)
189	#define IMX_EPIT1_BASE (0x53F94000)
190	#define IMX_EPIT2_BASE (0x53F98000)
191	#define IMX_GPIO4_BASE (0x53F9C000)
192	#define IMX_PWM2_BASE (0x53FA0000)
193	#define IMX_GPIO3_BASE (0x53FA4000)
194	#define IMX_PWM3_BASE (0x53FA8000)
195	#define IMX_SCC_BASE (0x53FAC000)
196	#define IMX_SCM_BASE (0x53FAE000)
197	#define IMX_SMN_BASE (0x53FAF000)
198	#define IMX_RNGD_BASE (0x53FB0000)
199	#define IMX_MMC_SDHC1_BASE (0x53FB4000)
200	#define IMX_MMC_SDHC2_BASE (0x53FB8000)
201	#define IMX_LCDC_BASE (0x53FBC000)
202	#define IMX_SLCDC_BASE (0x53FC0000)
203	#define IMX_PWM4_BASE (0x53FC8000)
204	#define IMX_GPIO1_BASE (0x53FCC000)
205	#define IMX_GPIO2_BASE (0x53FD0000)
206	#define IMX_SDMA_BASE (0x53FD4000)
207	#define IMX_WDT_BASE (0x53FDC000)
208	#define IMX_PWM1_BASE (0x53FE0000)
209	#define IMX_RTIC_BASE (0x53FEC000)
210	#define IMX_IIM_BASE (0x53FF0000)
211	#define IMX_USB_BASE (0x53FF4000)
212	#define IMX_CSI_BASE (0x53FF8000)
213	#define IMX_DRYICE_BASE (0x53FFC000)
214
215	#define IMX_ARM926_ROMPATCH (0x60000000)
216	#define IMX_ARM926_ASIC (0x68000000)
217
218	/* 128K Internal Static RAM */
219	#define IMX_RAM_BASE (0x78000000)
220
221	/* SDRAM BANKS */
222	#define IMX_SDRAM_BANK0_BASE (0x80000000)
223	#define IMX_SDRAM_BANK1_BASE (0x90000000)
224
225	#define IMX_WEIM_CS0 (0xA0000000)
226	#define IMX_WEIM_CS1 (0xA8000000)
227	#define IMX_WEIM_CS2 (0xB0000000)
228	#define IMX_WEIM_CS3 (0xB2000000)
229	#define IMX_WEIM_CS4 (0xB4000000)
230	#define IMX_ESDRAMC_BASE (0xB8001000)
231	#define IMX_WEIM_CTRL_BASE (0xB8002000)
232	#define IMX_M3IF_CTRL_BASE (0xB8003000)
233	#define IMX_EMI_CTRL_BASE (0xB8004000)
234
235	/* NAND Flash Controller */
236	#define IMX_NFC_BASE (0xBB000000)
237	#define NFC_BASE_ADDR IMX_NFC_BASE
238
239	/* CCM bitfields */
240	#define CCM_PLL_MFI_SHIFT 10
241	#define CCM_PLL_MFI_MASK 0xf
242	#define CCM_PLL_MFN_SHIFT 0
243	#define CCM_PLL_MFN_MASK 0x3ff
244	#define CCM_PLL_MFD_SHIFT 16
245	#define CCM_PLL_MFD_MASK 0x3ff
246	#define CCM_PLL_PD_SHIFT 26
247	#define CCM_PLL_PD_MASK 0xf
248	#define CCM_CCTL_ARM_DIV_SHIFT 30
249	#define CCM_CCTL_ARM_DIV_MASK 3
250	#define CCM_CCTL_AHB_DIV_SHIFT 28
251	#define CCM_CCTL_AHB_DIV_MASK 3
252	#define CCM_CCTL_ARM_SRC (1 << 14)
253	#define CCM_CGR1_GPT1 (1 << 19)
254	#define CCM_PERCLK_REG(clk) (clk / 4)
255	#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
256	#define CCM_PERCLK_MASK 0x3f
257	#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
258	#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
259
260	/* ESDRAM Controller register bitfields */
261	#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
262	#define ESDCTL_BL (1 << 7)
263	#define ESDCTL_FP (1 << 8)
264	#define ESDCTL_PWDT(x) (((x) & 3) << 10)
265	#define ESDCTL_SREFR(x) (((x) & 7) << 13)
266	#define ESDCTL_DSIZ_16_UPPER (0 << 16)
267	#define ESDCTL_DSIZ_16_LOWER (1 << 16)
268	#define ESDCTL_DSIZ_32 (2 << 16)
269	#define ESDCTL_COL8 (0 << 20)
270	#define ESDCTL_COL9 (1 << 20)
271	#define ESDCTL_COL10 (2 << 20)
272	#define ESDCTL_ROW11 (0 << 24)
273	#define ESDCTL_ROW12 (1 << 24)
274	#define ESDCTL_ROW13 (2 << 24)
275	#define ESDCTL_ROW14 (3 << 24)
276	#define ESDCTL_ROW15 (4 << 24)
277	#define ESDCTL_SP (1 << 27)
278	#define ESDCTL_SMODE_NORMAL (0 << 28)
279	#define ESDCTL_SMODE_PRECHARGE (1 << 28)
280	#define ESDCTL_SMODE_AUTO_REF (2 << 28)
281	#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
282	#define ESDCTL_SMODE_MAN_REF (4 << 28)
283	#define ESDCTL_SDE (1 << 31)
284
285	#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
286	#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
287	#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
288	#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
289	#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
290	#define ESDCFG_TWR (1 << 15)
291	#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
292	#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
293	#define ESDCFG_TWTR (1 << 20)
294	#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
295
296	#define ESDMISC_RST (1 << 1)
297	#define ESDMISC_MDDREN (1 << 2)
298	#define ESDMISC_MDDR_DL_RST (1 << 3)
299	#define ESDMISC_MDDR_MDIS (1 << 4)
300	#define ESDMISC_LHD (1 << 5)
301	#define ESDMISC_MA10_SHARE (1 << 6)
302	#define ESDMISC_SDRAM_RDY (1 << 31)
303
304	/* GPT bits */
305	#define GPT_CTRL_SWR (1 << 15) /* Software reset */
306	#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
307	#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
308	#define GPT_CTRL_TEN 1 /* Timer enable */
309
310	/* WDOG enable */
311	#define WCR_WDE 0x04
312
313	/* FUSE bank offsets */
314	#define IIM0_MAC 0x1a
315
316	#endif /* _IMX_REGS_H */