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Commit | Line | Data |
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23608e23 JL |
1 | /* |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
23608e23 JL |
5 | */ |
6 | ||
7 | #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ | |
8 | #define __ASM_ARCH_MX6_IMX_REGS_H__ | |
9 | ||
8e99ecd7 BT |
10 | #define ARCH_MXC |
11 | ||
23608e23 JL |
12 | #define ROMCP_ARB_BASE_ADDR 0x00000000 |
13 | #define ROMCP_ARB_END_ADDR 0x000FFFFF | |
25b4aa14 FE |
14 | |
15 | #ifdef CONFIG_MX6SL | |
16 | #define GPU_2D_ARB_BASE_ADDR 0x02200000 | |
17 | #define GPU_2D_ARB_END_ADDR 0x02203FFF | |
18 | #define OPENVG_ARB_BASE_ADDR 0x02204000 | |
19 | #define OPENVG_ARB_END_ADDR 0x02207FFF | |
bc32fc69 | 20 | #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) |
05d54b82 FE |
21 | #define CAAM_ARB_BASE_ADDR 0x00100000 |
22 | #define CAAM_ARB_END_ADDR 0x00107FFF | |
23 | #define GPU_ARB_BASE_ADDR 0x01800000 | |
24 | #define GPU_ARB_END_ADDR 0x01803FFF | |
25 | #define APBH_DMA_ARB_BASE_ADDR 0x01804000 | |
26 | #define APBH_DMA_ARB_END_ADDR 0x0180BFFF | |
27 | #define M4_BOOTROM_BASE_ADDR 0x007F8000 | |
28 | ||
56612bf6 | 29 | #elif !defined(CONFIG_MX6SLL) |
23608e23 JL |
30 | #define CAAM_ARB_BASE_ADDR 0x00100000 |
31 | #define CAAM_ARB_END_ADDR 0x00103FFF | |
32 | #define APBH_DMA_ARB_BASE_ADDR 0x00110000 | |
33 | #define APBH_DMA_ARB_END_ADDR 0x00117FFF | |
34 | #define HDMI_ARB_BASE_ADDR 0x00120000 | |
35 | #define HDMI_ARB_END_ADDR 0x00128FFF | |
36 | #define GPU_3D_ARB_BASE_ADDR 0x00130000 | |
37 | #define GPU_3D_ARB_END_ADDR 0x00133FFF | |
38 | #define GPU_2D_ARB_BASE_ADDR 0x00134000 | |
39 | #define GPU_2D_ARB_END_ADDR 0x00137FFF | |
40 | #define DTCP_ARB_BASE_ADDR 0x00138000 | |
41 | #define DTCP_ARB_END_ADDR 0x0013BFFF | |
25b4aa14 | 42 | #endif /* CONFIG_MX6SL */ |
99193e30 SR |
43 | |
44 | #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR | |
45 | #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) | |
46 | #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) | |
47 | ||
23608e23 | 48 | /* GPV - PL301 configuration ports */ |
56612bf6 PF |
49 | #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ |
50 | defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) | |
25b4aa14 | 51 | #define GPV2_BASE_ADDR 0x00D00000 |
05d54b82 FE |
52 | #define GPV3_BASE_ADDR 0x00E00000 |
53 | #define GPV4_BASE_ADDR 0x00F00000 | |
54 | #define GPV5_BASE_ADDR 0x01000000 | |
55 | #define GPV6_BASE_ADDR 0x01100000 | |
56 | #define PCIE_ARB_BASE_ADDR 0x08000000 | |
57 | #define PCIE_ARB_END_ADDR 0x08FFFFFF | |
58 | ||
59 | #else | |
56612bf6 | 60 | #define GPV2_BASE_ADDR 0x00200000 |
23608e23 JL |
61 | #define GPV3_BASE_ADDR 0x00300000 |
62 | #define GPV4_BASE_ADDR 0x00800000 | |
05d54b82 FE |
63 | #define PCIE_ARB_BASE_ADDR 0x01000000 |
64 | #define PCIE_ARB_END_ADDR 0x01FFFFFF | |
65 | #endif | |
66 | ||
23608e23 JL |
67 | #define IRAM_BASE_ADDR 0x00900000 |
68 | #define SCU_BASE_ADDR 0x00A00000 | |
69 | #define IC_INTERFACES_BASE_ADDR 0x00A00100 | |
70 | #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 | |
71 | #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 | |
72 | #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 | |
6d73c234 | 73 | #define L2_PL310_BASE 0x00A02000 |
23608e23 JL |
74 | #define GPV0_BASE_ADDR 0x00B00000 |
75 | #define GPV1_BASE_ADDR 0x00C00000 | |
23608e23 JL |
76 | |
77 | #define AIPS1_ARB_BASE_ADDR 0x02000000 | |
78 | #define AIPS1_ARB_END_ADDR 0x020FFFFF | |
79 | #define AIPS2_ARB_BASE_ADDR 0x02100000 | |
80 | #define AIPS2_ARB_END_ADDR 0x021FFFFF | |
bc32fc69 | 81 | /* AIPS3 only on i.MX6SX */ |
e8cdeefc YL |
82 | #define AIPS3_ARB_BASE_ADDR 0x02200000 |
83 | #define AIPS3_ARB_END_ADDR 0x022FFFFF | |
bc32fc69 | 84 | #ifdef CONFIG_MX6SX |
05d54b82 FE |
85 | #define WEIM_ARB_BASE_ADDR 0x50000000 |
86 | #define WEIM_ARB_END_ADDR 0x57FFFFFF | |
b93ab2ee PF |
87 | #define QSPI0_AMBA_BASE 0x60000000 |
88 | #define QSPI0_AMBA_END 0x6FFFFFFF | |
89 | #define QSPI1_AMBA_BASE 0x70000000 | |
90 | #define QSPI1_AMBA_END 0x7FFFFFFF | |
bc32fc69 PF |
91 | #elif defined(CONFIG_MX6UL) |
92 | #define WEIM_ARB_BASE_ADDR 0x50000000 | |
93 | #define WEIM_ARB_END_ADDR 0x57FFFFFF | |
94 | #define QSPI0_AMBA_BASE 0x60000000 | |
95 | #define QSPI0_AMBA_END 0x6FFFFFFF | |
56612bf6 | 96 | #elif !defined(CONFIG_MX6SLL) |
23608e23 JL |
97 | #define SATA_ARB_BASE_ADDR 0x02200000 |
98 | #define SATA_ARB_END_ADDR 0x02203FFF | |
99 | #define OPENVG_ARB_BASE_ADDR 0x02204000 | |
100 | #define OPENVG_ARB_END_ADDR 0x02207FFF | |
101 | #define HSI_ARB_BASE_ADDR 0x02208000 | |
102 | #define HSI_ARB_END_ADDR 0x0220BFFF | |
103 | #define IPU1_ARB_BASE_ADDR 0x02400000 | |
104 | #define IPU1_ARB_END_ADDR 0x027FFFFF | |
105 | #define IPU2_ARB_BASE_ADDR 0x02800000 | |
106 | #define IPU2_ARB_END_ADDR 0x02BFFFFF | |
107 | #define WEIM_ARB_BASE_ADDR 0x08000000 | |
108 | #define WEIM_ARB_END_ADDR 0x0FFFFFFF | |
05d54b82 | 109 | #endif |
23608e23 | 110 | |
56612bf6 PF |
111 | #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ |
112 | defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) | |
25b4aa14 FE |
113 | #define MMDC0_ARB_BASE_ADDR 0x80000000 |
114 | #define MMDC0_ARB_END_ADDR 0xFFFFFFFF | |
115 | #define MMDC1_ARB_BASE_ADDR 0xC0000000 | |
116 | #define MMDC1_ARB_END_ADDR 0xFFFFFFFF | |
117 | #else | |
23608e23 JL |
118 | #define MMDC0_ARB_BASE_ADDR 0x10000000 |
119 | #define MMDC0_ARB_END_ADDR 0x7FFFFFFF | |
120 | #define MMDC1_ARB_BASE_ADDR 0x80000000 | |
121 | #define MMDC1_ARB_END_ADDR 0xFFFFFFFF | |
25b4aa14 | 122 | #endif |
23608e23 | 123 | |
05d54b82 | 124 | #ifndef CONFIG_MX6SX |
05d4df1d FE |
125 | #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR |
126 | #define IPU_SOC_OFFSET 0x00200000 | |
05d54b82 | 127 | #endif |
05d4df1d | 128 | |
23608e23 JL |
129 | /* Defines for Blocks connected via AIPS (SkyBlue) */ |
130 | #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR | |
131 | #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR | |
50a082a8 | 132 | #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR |
23608e23 JL |
133 | #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR |
134 | #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR | |
50a082a8 | 135 | #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR |
23608e23 JL |
136 | |
137 | #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) | |
138 | #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) | |
139 | #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) | |
140 | #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) | |
141 | #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) | |
56612bf6 PF |
142 | |
143 | #define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) | |
144 | #define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) | |
145 | #define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) | |
146 | #define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) | |
147 | #define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) | |
148 | #define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) | |
149 | #define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) | |
150 | #define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) | |
151 | #define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) | |
152 | ||
05d54b82 | 153 | #ifndef CONFIG_MX6SX |
23608e23 | 154 | #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) |
05d54b82 | 155 | #endif |
56612bf6 | 156 | #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) |
23608e23 JL |
157 | #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) |
158 | #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) | |
51560f0b | 159 | #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) |
23608e23 JL |
160 | #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) |
161 | #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) | |
162 | #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) | |
163 | #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) | |
25b4aa14 | 164 | |
05d54b82 | 165 | #ifndef CONFIG_MX6SX |
23608e23 JL |
166 | #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) |
167 | #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) | |
05d54b82 | 168 | #endif |
23608e23 JL |
169 | #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) |
170 | ||
171 | #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) | |
172 | #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) | |
173 | #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) | |
174 | #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) | |
175 | #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) | |
176 | #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) | |
177 | #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) | |
56612bf6 PF |
178 | /* QOSC on i.MX6SLL */ |
179 | #define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) | |
23608e23 JL |
180 | #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) |
181 | #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) | |
182 | #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) | |
183 | #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) | |
184 | #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) | |
185 | #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) | |
07e1c0ae | 186 | #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) |
23608e23 JL |
187 | #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) |
188 | #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) | |
189 | #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) | |
190 | #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) | |
191 | #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) | |
3f467529 WG |
192 | #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) |
193 | #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) | |
194 | #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) | |
23608e23 | 195 | #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) |
23608e23 JL |
196 | #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) |
197 | #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) | |
198 | #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) | |
199 | #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) | |
200 | #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) | |
201 | #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) | |
56612bf6 PF |
202 | #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) |
203 | #ifdef CONFIG_MX6SLL | |
204 | #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) | |
205 | #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) | |
206 | #define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) | |
207 | #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) | |
208 | #define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) | |
209 | #elif defined(CONFIG_MX6SL) | |
25b4aa14 FE |
210 | #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) |
211 | #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) | |
212 | #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) | |
56612bf6 | 213 | #elif defined(CONFIG_MX6SX) |
05d54b82 FE |
214 | #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) |
215 | #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) | |
216 | #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) | |
217 | #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) | |
218 | #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) | |
219 | #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) | |
25b4aa14 | 220 | #else |
23608e23 JL |
221 | #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) |
222 | #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) | |
223 | #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) | |
25b4aa14 | 224 | #endif |
23608e23 | 225 | |
56612bf6 PF |
226 | #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) |
227 | #define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) | |
228 | ||
23608e23 JL |
229 | #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) |
230 | #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) | |
50a082a8 AA |
231 | #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) |
232 | #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) | |
23608e23 JL |
233 | #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) |
234 | #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) | |
0200020b | 235 | |
e99d7193 AP |
236 | #define CONFIG_SYS_FSL_SEC_OFFSET 0 |
237 | #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ | |
238 | CONFIG_SYS_FSL_SEC_OFFSET) | |
239 | #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 | |
240 | #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ | |
241 | CONFIG_SYS_FSL_JR0_OFFSET) | |
242 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 | |
0200020b | 243 | |
5546ad07 YL |
244 | #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) |
245 | #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) | |
25b4aa14 | 246 | |
23608e23 | 247 | #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) |
25b4aa14 FE |
248 | #ifdef CONFIG_MX6SL |
249 | #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) | |
250 | #else | |
23608e23 | 251 | #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) |
25b4aa14 FE |
252 | #endif |
253 | ||
23608e23 JL |
254 | #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) |
255 | #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) | |
256 | #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) | |
257 | #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) | |
258 | #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) | |
259 | #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) | |
260 | #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) | |
261 | #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) | |
262 | #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) | |
56612bf6 | 263 | /* i.MX6SL/SLL */ |
25b4aa14 | 264 | #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) |
bc32fc69 PF |
265 | #ifdef CONFIG_MX6UL |
266 | #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) | |
25b4aa14 | 267 | #else |
bc32fc69 PF |
268 | /* i.MX6SX */ |
269 | #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) | |
25b4aa14 | 270 | #endif |
bc32fc69 PF |
271 | /* i.MX6DQ/SDL */ |
272 | #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) | |
25b4aa14 | 273 | |
23608e23 JL |
274 | #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) |
275 | #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) | |
276 | #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) | |
56612bf6 PF |
277 | #ifdef CONFIG_MX6SLL |
278 | #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) | |
279 | #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) | |
280 | #endif | |
23608e23 JL |
281 | #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) |
282 | #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) | |
b1ce1fb5 | 283 | #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) |
bdfb2d4d | 284 | #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) |
05d54b82 FE |
285 | #ifdef CONFIG_MX6SX |
286 | #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) | |
287 | #else | |
23608e23 | 288 | #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) |
05d54b82 | 289 | #endif |
23608e23 | 290 | #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) |
bc32fc69 PF |
291 | #ifdef CONFIG_MX6UL |
292 | #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) | |
9999fc09 | 293 | #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) |
bc32fc69 | 294 | #elif defined(CONFIG_MX6SX) |
05d54b82 | 295 | #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) |
23608e23 | 296 | #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) |
05d54b82 | 297 | #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) |
b93ab2ee PF |
298 | #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) |
299 | #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) | |
05d54b82 | 300 | #else |
bc32fc69 | 301 | #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) |
23608e23 JL |
302 | #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) |
303 | #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) | |
304 | #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) | |
05d54b82 | 305 | #endif |
bc32fc69 | 306 | #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) |
23608e23 JL |
307 | #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) |
308 | #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) | |
309 | #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) | |
310 | #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) | |
21a26940 | 311 | #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) |
23608e23 JL |
312 | #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) |
313 | #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) | |
56612bf6 PF |
314 | /* i.MX6SLL */ |
315 | #define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) | |
23608e23 | 316 | |
05d54b82 FE |
317 | #ifdef CONFIG_MX6SX |
318 | #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) | |
319 | #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) | |
320 | #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) | |
321 | #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) | |
322 | #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) | |
323 | #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) | |
05d54b82 FE |
324 | #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) |
325 | #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) | |
326 | #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) | |
327 | #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) | |
328 | #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) | |
329 | #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) | |
05d54b82 FE |
330 | #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) |
331 | #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) | |
332 | #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) | |
333 | #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) | |
334 | #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) | |
335 | #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) | |
336 | #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) | |
337 | #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) | |
338 | #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) | |
339 | #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) | |
bdfb2d4d PF |
340 | #elif defined(CONFIG_MX6ULL) |
341 | #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) | |
342 | #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) | |
343 | #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) | |
344 | #define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) | |
345 | #define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) | |
346 | #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) | |
347 | #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) | |
05d54b82 | 348 | #endif |
b1ce1fb5 PF |
349 | /* Only for i.MX6SX */ |
350 | #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) | |
351 | #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) | |
bc32fc69 PF |
352 | #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) |
353 | ||
56612bf6 PF |
354 | #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ |
355 | defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) | |
23608e23 | 356 | #define IRAM_SIZE 0x00040000 |
05d54b82 FE |
357 | #else |
358 | #define IRAM_SIZE 0x00020000 | |
359 | #endif | |
28774cba | 360 | #define FEC_QUIRK_ENET_MAC |
23608e23 | 361 | |
552a848e | 362 | #include <asm/mach-imx/regs-lcdif.h> |
23608e23 JL |
363 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
364 | #include <asm/types.h> | |
365 | ||
b1ce1fb5 | 366 | /* only for i.MX6SX/UL */ |
bdfb2d4d | 367 | #define WDOG3_BASE_ADDR ((is_mx6ul() ? \ |
0c890879 | 368 | MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) |
56612bf6 PF |
369 | #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \ |
370 | MX6SLL_LCDIF_BASE_ADDR : \ | |
371 | (is_cpu_type(MXC_CPU_MX6SL)) ? \ | |
372 | MX6SL_LCDIF_BASE_ADDR : \ | |
373 | ((is_cpu_type(MXC_CPU_MX6UL)) ? \ | |
bdfb2d4d PF |
374 | MX6UL_LCDIF1_BASE_ADDR : \ |
375 | ((is_mx6ull()) ? \ | |
56612bf6 | 376 | MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) |
b1ce1fb5 PF |
377 | |
378 | ||
be252b65 | 379 | extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); |
23608e23 | 380 | |
a76df709 GH |
381 | #define SRC_SCR_CORE_1_RESET_OFFSET 14 |
382 | #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) | |
383 | #define SRC_SCR_CORE_2_RESET_OFFSET 15 | |
384 | #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) | |
385 | #define SRC_SCR_CORE_3_RESET_OFFSET 16 | |
386 | #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) | |
387 | #define SRC_SCR_CORE_1_ENABLE_OFFSET 22 | |
388 | #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) | |
389 | #define SRC_SCR_CORE_2_ENABLE_OFFSET 23 | |
390 | #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) | |
391 | #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 | |
392 | #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) | |
393 | ||
613e0106 PF |
394 | struct rdc_regs { |
395 | u32 vir; /* Version information */ | |
396 | u32 reserved1[8]; | |
397 | u32 stat; /* Status */ | |
398 | u32 intctrl; /* Interrupt and Control */ | |
399 | u32 intstat; /* Interrupt Status */ | |
400 | u32 reserved2[116]; | |
401 | u32 mda[32]; /* Master Domain Assignment */ | |
402 | u32 reserved3[96]; | |
403 | u32 pdap[104]; /* Peripheral Domain Access Permissions */ | |
404 | u32 reserved4[88]; | |
405 | struct { | |
406 | u32 mrsa; /* Memory Region Start Address */ | |
407 | u32 mrea; /* Memory Region End Address */ | |
408 | u32 mrc; /* Memory Region Control */ | |
409 | u32 mrvs; /* Memory Region Violation Status */ | |
410 | } mem_region[55]; | |
411 | }; | |
412 | ||
413 | struct rdc_sema_regs { | |
414 | u8 gate[64]; /* Gate */ | |
415 | u16 rstgt; /* Reset Gate */ | |
416 | }; | |
417 | ||
573960ac FE |
418 | /* WEIM registers */ |
419 | struct weim { | |
420 | u32 cs0gcr1; | |
421 | u32 cs0gcr2; | |
422 | u32 cs0rcr1; | |
423 | u32 cs0rcr2; | |
424 | u32 cs0wcr1; | |
425 | u32 cs0wcr2; | |
426 | ||
427 | u32 cs1gcr1; | |
428 | u32 cs1gcr2; | |
429 | u32 cs1rcr1; | |
430 | u32 cs1rcr2; | |
431 | u32 cs1wcr1; | |
432 | u32 cs1wcr2; | |
433 | ||
434 | u32 cs2gcr1; | |
435 | u32 cs2gcr2; | |
436 | u32 cs2rcr1; | |
437 | u32 cs2rcr2; | |
438 | u32 cs2wcr1; | |
439 | u32 cs2wcr2; | |
440 | ||
441 | u32 cs3gcr1; | |
442 | u32 cs3gcr2; | |
443 | u32 cs3rcr1; | |
444 | u32 cs3rcr2; | |
445 | u32 cs3wcr1; | |
446 | u32 cs3wcr2; | |
447 | ||
448 | u32 unused[12]; | |
449 | ||
450 | u32 wcr; | |
451 | u32 wiar; | |
452 | u32 ear; | |
453 | }; | |
454 | ||
23608e23 JL |
455 | /* System Reset Controller (SRC) */ |
456 | struct src { | |
457 | u32 scr; | |
458 | u32 sbmr1; | |
459 | u32 srsr; | |
460 | u32 reserved1[2]; | |
461 | u32 sisr; | |
462 | u32 simr; | |
463 | u32 sbmr2; | |
464 | u32 gpr1; | |
465 | u32 gpr2; | |
466 | u32 gpr3; | |
467 | u32 gpr4; | |
468 | u32 gpr5; | |
469 | u32 gpr6; | |
470 | u32 gpr7; | |
471 | u32 gpr8; | |
472 | u32 gpr9; | |
473 | u32 gpr10; | |
474 | }; | |
475 | ||
7b54f5a8 JT |
476 | #define src_base ((struct src *)SRC_BASE_ADDR) |
477 | ||
0623d375 PF |
478 | #define SRC_SCR_M4_ENABLE_OFFSET 22 |
479 | #define SRC_SCR_M4_ENABLE_MASK (1 << 22) | |
480 | #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4 | |
481 | #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4) | |
482 | ||
3a217731 | 483 | /* GPR1 bitfields */ |
d62f2f8c HS |
484 | #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) |
485 | #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) | |
486 | #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) | |
487 | #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) | |
488 | #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) | |
489 | #define IOMUXC_GPR1_DPI_OFF BIT(24) | |
490 | #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) | |
3a217731 FE |
491 | #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 |
492 | #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) | |
d62f2f8c HS |
493 | #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) |
494 | #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) | |
495 | #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) | |
496 | #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) | |
497 | #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) | |
498 | #define IOMUXC_GPR1_USB_EXP_MODE BIT(15) | |
499 | #define IOMUXC_GPR1_PCIE_INT BIT(14) | |
4a4d3a7d HS |
500 | #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 |
501 | #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) | |
d62f2f8c HS |
502 | #define IOMUXC_GPR1_GINT BIT(12) |
503 | #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) | |
504 | #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) | |
505 | #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) | |
506 | #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) | |
507 | #define IOMUXC_GPR1_ACT_CS3 BIT(9) | |
508 | #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) | |
509 | #define IOMUXC_GPR1_ACT_CS2 BIT(6) | |
510 | #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) | |
511 | #define IOMUXC_GPR1_ACT_CS1 BIT(3) | |
512 | #define IOMUXC_GPR1_ADDRS0_OFFSET (1) | |
513 | #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) | |
514 | #define IOMUXC_GPR1_ACT_CS0 BIT(0) | |
3a217731 | 515 | |
a83e1b7b EN |
516 | /* GPR3 bitfields */ |
517 | #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 | |
518 | #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) | |
519 | #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 | |
520 | #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) | |
521 | #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 | |
522 | #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) | |
523 | #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 | |
524 | #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) | |
525 | #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 | |
526 | #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) | |
527 | #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 | |
528 | #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) | |
529 | #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 | |
530 | #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) | |
531 | #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 | |
532 | #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) | |
533 | #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 | |
534 | #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) | |
535 | #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 | |
536 | #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) | |
537 | #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 | |
538 | #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) | |
539 | #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 | |
540 | #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) | |
541 | #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 | |
542 | #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) | |
543 | #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 | |
544 | #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) | |
545 | ||
546 | #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 | |
547 | #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 | |
548 | #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 | |
549 | #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 | |
550 | ||
551 | #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 | |
552 | #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) | |
553 | ||
554 | #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 | |
555 | #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | |
556 | ||
557 | #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 | |
558 | #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) | |
559 | ||
560 | #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 | |
561 | #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) | |
562 | ||
d62f2f8c HS |
563 | /* gpr12 bitfields */ |
564 | #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) | |
565 | #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) | |
566 | #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) | |
567 | #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) | |
568 | #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) | |
569 | #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) | |
570 | #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) | |
a83e1b7b | 571 | |
de710a14 | 572 | struct iomuxc { |
bc32fc69 | 573 | #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) |
aeadf065 FE |
574 | u8 reserved[0x4000]; |
575 | #endif | |
de710a14 | 576 | u32 gpr[14]; |
de710a14 EN |
577 | }; |
578 | ||
ac17dcf6 FE |
579 | struct gpc { |
580 | u32 cntr; | |
581 | u32 pgr; | |
582 | u32 imr1; | |
583 | u32 imr2; | |
584 | u32 imr3; | |
585 | u32 imr4; | |
586 | u32 isr1; | |
587 | u32 isr2; | |
588 | u32 isr3; | |
589 | u32 isr4; | |
590 | }; | |
591 | ||
de710a14 EN |
592 | #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 |
593 | #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) | |
594 | #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 | |
595 | #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) | |
596 | ||
597 | #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 | |
598 | #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) | |
599 | #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) | |
600 | #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) | |
601 | #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 | |
602 | #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 | |
603 | ||
604 | #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 | |
605 | #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) | |
606 | #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) | |
607 | #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) | |
608 | ||
609 | #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 | |
610 | #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) | |
611 | #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) | |
612 | #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) | |
613 | ||
614 | #define IOMUXC_GPR2_BITMAP_SPWG 0 | |
615 | #define IOMUXC_GPR2_BITMAP_JEIDA 1 | |
616 | ||
617 | #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 | |
618 | #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) | |
619 | #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) | |
620 | #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) | |
621 | ||
622 | #define IOMUXC_GPR2_DATA_WIDTH_18 0 | |
623 | #define IOMUXC_GPR2_DATA_WIDTH_24 1 | |
624 | ||
625 | #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 | |
626 | #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) | |
627 | #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) | |
628 | #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) | |
629 | ||
630 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 | |
631 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) | |
632 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) | |
633 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) | |
634 | ||
635 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 | |
636 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) | |
637 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) | |
638 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) | |
639 | ||
640 | #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 | |
641 | #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) | |
642 | ||
643 | #define IOMUXC_GPR2_MODE_DISABLED 0 | |
644 | #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 | |
7aa1e8bb | 645 | #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 |
de710a14 EN |
646 | |
647 | #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 | |
648 | #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) | |
649 | #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) | |
650 | #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) | |
651 | #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) | |
652 | ||
653 | #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 | |
654 | #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) | |
655 | #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) | |
656 | #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) | |
657 | #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) | |
658 | ||
d5c37c9c EN |
659 | /* ECSPI registers */ |
660 | struct cspi_regs { | |
661 | u32 rxdata; | |
662 | u32 txdata; | |
663 | u32 ctrl; | |
664 | u32 cfg; | |
665 | u32 intr; | |
666 | u32 dma; | |
667 | u32 stat; | |
668 | u32 period; | |
669 | }; | |
670 | ||
671 | /* | |
672 | * CSPI register definitions | |
673 | */ | |
674 | #define MXC_ECSPI | |
675 | #define MXC_CSPICTRL_EN (1 << 0) | |
676 | #define MXC_CSPICTRL_MODE (1 << 1) | |
677 | #define MXC_CSPICTRL_XCH (1 << 2) | |
0f1411bc | 678 | #define MXC_CSPICTRL_MODE_MASK (0xf << 4) |
d5c37c9c EN |
679 | #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) |
680 | #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) | |
681 | #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) | |
682 | #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) | |
683 | #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) | |
684 | #define MXC_CSPICTRL_MAXBITS 0xfff | |
685 | #define MXC_CSPICTRL_TC (1 << 7) | |
686 | #define MXC_CSPICTRL_RXOVF (1 << 6) | |
687 | #define MXC_CSPIPERIOD_32KHZ (1 << 15) | |
688 | #define MAX_SPI_BYTES 32 | |
a0ae0091 | 689 | #define SPI_MAX_NUM 4 |
d5c37c9c EN |
690 | |
691 | /* Bit position inside CTRL register to be associated with SS */ | |
692 | #define MXC_CSPICTRL_CHAN 18 | |
693 | ||
694 | /* Bit position inside CON register to be associated with SS */ | |
d7cbcc76 MN |
695 | #define MXC_CSPICON_PHA 0 /* SCLK phase control */ |
696 | #define MXC_CSPICON_POL 4 /* SCLK polarity */ | |
697 | #define MXC_CSPICON_SSPOL 12 /* SS polarity */ | |
698 | #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ | |
56612bf6 PF |
699 | #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ |
700 | defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) | |
25b4aa14 FE |
701 | #define MXC_SPI_BASE_ADDRESSES \ |
702 | ECSPI1_BASE_ADDR, \ | |
703 | ECSPI2_BASE_ADDR, \ | |
704 | ECSPI3_BASE_ADDR, \ | |
705 | ECSPI4_BASE_ADDR | |
706 | #else | |
d5c37c9c EN |
707 | #define MXC_SPI_BASE_ADDRESSES \ |
708 | ECSPI1_BASE_ADDR, \ | |
709 | ECSPI2_BASE_ADDR, \ | |
710 | ECSPI3_BASE_ADDR, \ | |
711 | ECSPI4_BASE_ADDR, \ | |
712 | ECSPI5_BASE_ADDR | |
25b4aa14 | 713 | #endif |
d5c37c9c | 714 | |
8f3ff11c | 715 | struct ocotp_regs { |
23608e23 JL |
716 | u32 ctrl; |
717 | u32 ctrl_set; | |
718 | u32 ctrl_clr; | |
719 | u32 ctrl_tog; | |
720 | u32 timing; | |
721 | u32 rsvd0[3]; | |
722 | u32 data; | |
723 | u32 rsvd1[3]; | |
724 | u32 read_ctrl; | |
725 | u32 rsvd2[3]; | |
8f3ff11c | 726 | u32 read_fuse_data; |
23608e23 | 727 | u32 rsvd3[3]; |
8f3ff11c | 728 | u32 sw_sticky; |
23608e23 JL |
729 | u32 rsvd4[3]; |
730 | u32 scs; | |
731 | u32 scs_set; | |
732 | u32 scs_clr; | |
733 | u32 scs_tog; | |
734 | u32 crc_addr; | |
735 | u32 rsvd5[3]; | |
736 | u32 crc_value; | |
737 | u32 rsvd6[3]; | |
738 | u32 version; | |
bd2e27c0 | 739 | u32 rsvd7[0xdb]; |
23608e23 | 740 | |
7296a023 | 741 | /* fuse banks */ |
23608e23 JL |
742 | struct fuse_bank { |
743 | u32 fuse_regs[0x20]; | |
7296a023 | 744 | } bank[0]; |
23608e23 JL |
745 | }; |
746 | ||
6adbd302 BT |
747 | struct fuse_bank0_regs { |
748 | u32 lock; | |
749 | u32 rsvd0[3]; | |
750 | u32 uid_low; | |
751 | u32 rsvd1[3]; | |
752 | u32 uid_high; | |
b83c709e | 753 | u32 rsvd2[3]; |
1730af1b PF |
754 | u32 cfg2; |
755 | u32 rsvd3[3]; | |
756 | u32 cfg3; | |
757 | u32 rsvd4[3]; | |
758 | u32 cfg4; | |
759 | u32 rsvd5[3]; | |
b83c709e SB |
760 | u32 cfg5; |
761 | u32 rsvd6[3]; | |
1730af1b PF |
762 | u32 cfg6; |
763 | u32 rsvd7[3]; | |
6adbd302 BT |
764 | }; |
765 | ||
d43e0ab4 TH |
766 | struct fuse_bank1_regs { |
767 | u32 mem0; | |
768 | u32 rsvd0[3]; | |
769 | u32 mem1; | |
770 | u32 rsvd1[3]; | |
771 | u32 mem2; | |
772 | u32 rsvd2[3]; | |
773 | u32 mem3; | |
774 | u32 rsvd3[3]; | |
775 | u32 mem4; | |
776 | u32 rsvd4[3]; | |
777 | u32 ana0; | |
778 | u32 rsvd5[3]; | |
779 | u32 ana1; | |
780 | u32 rsvd6[3]; | |
781 | u32 ana2; | |
782 | u32 rsvd7[3]; | |
783 | }; | |
784 | ||
05d54b82 FE |
785 | struct fuse_bank4_regs { |
786 | u32 sjc_resp_low; | |
787 | u32 rsvd0[3]; | |
788 | u32 sjc_resp_high; | |
789 | u32 rsvd1[3]; | |
d4d1dd67 | 790 | u32 mac_addr0; |
05d54b82 | 791 | u32 rsvd2[3]; |
d4d1dd67 | 792 | u32 mac_addr1; |
05d54b82 | 793 | u32 rsvd3[3]; |
d4d1dd67 | 794 | u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ |
05d54b82 FE |
795 | u32 rsvd4[7]; |
796 | u32 gp1; | |
bc32fc69 PF |
797 | u32 rsvd5[3]; |
798 | u32 gp2; | |
799 | u32 rsvd6[3]; | |
05d54b82 | 800 | }; |
23608e23 | 801 | |
f2f77458 JL |
802 | struct aipstz_regs { |
803 | u32 mprot0; | |
804 | u32 mprot1; | |
805 | u32 rsvd[0xe]; | |
806 | u32 opacr0; | |
807 | u32 opacr1; | |
808 | u32 opacr2; | |
809 | u32 opacr3; | |
810 | u32 opacr4; | |
811 | }; | |
812 | ||
a7683867 FE |
813 | struct anatop_regs { |
814 | u32 pll_sys; /* 0x000 */ | |
815 | u32 pll_sys_set; /* 0x004 */ | |
816 | u32 pll_sys_clr; /* 0x008 */ | |
817 | u32 pll_sys_tog; /* 0x00c */ | |
818 | u32 usb1_pll_480_ctrl; /* 0x010 */ | |
819 | u32 usb1_pll_480_ctrl_set; /* 0x014 */ | |
820 | u32 usb1_pll_480_ctrl_clr; /* 0x018 */ | |
821 | u32 usb1_pll_480_ctrl_tog; /* 0x01c */ | |
822 | u32 usb2_pll_480_ctrl; /* 0x020 */ | |
823 | u32 usb2_pll_480_ctrl_set; /* 0x024 */ | |
824 | u32 usb2_pll_480_ctrl_clr; /* 0x028 */ | |
825 | u32 usb2_pll_480_ctrl_tog; /* 0x02c */ | |
826 | u32 pll_528; /* 0x030 */ | |
827 | u32 pll_528_set; /* 0x034 */ | |
828 | u32 pll_528_clr; /* 0x038 */ | |
829 | u32 pll_528_tog; /* 0x03c */ | |
830 | u32 pll_528_ss; /* 0x040 */ | |
831 | u32 rsvd0[3]; | |
832 | u32 pll_528_num; /* 0x050 */ | |
833 | u32 rsvd1[3]; | |
834 | u32 pll_528_denom; /* 0x060 */ | |
835 | u32 rsvd2[3]; | |
836 | u32 pll_audio; /* 0x070 */ | |
837 | u32 pll_audio_set; /* 0x074 */ | |
838 | u32 pll_audio_clr; /* 0x078 */ | |
839 | u32 pll_audio_tog; /* 0x07c */ | |
840 | u32 pll_audio_num; /* 0x080 */ | |
841 | u32 rsvd3[3]; | |
842 | u32 pll_audio_denom; /* 0x090 */ | |
843 | u32 rsvd4[3]; | |
844 | u32 pll_video; /* 0x0a0 */ | |
845 | u32 pll_video_set; /* 0x0a4 */ | |
846 | u32 pll_video_clr; /* 0x0a8 */ | |
847 | u32 pll_video_tog; /* 0x0ac */ | |
848 | u32 pll_video_num; /* 0x0b0 */ | |
849 | u32 rsvd5[3]; | |
850 | u32 pll_video_denom; /* 0x0c0 */ | |
851 | u32 rsvd6[3]; | |
852 | u32 pll_mlb; /* 0x0d0 */ | |
853 | u32 pll_mlb_set; /* 0x0d4 */ | |
854 | u32 pll_mlb_clr; /* 0x0d8 */ | |
855 | u32 pll_mlb_tog; /* 0x0dc */ | |
856 | u32 pll_enet; /* 0x0e0 */ | |
857 | u32 pll_enet_set; /* 0x0e4 */ | |
858 | u32 pll_enet_clr; /* 0x0e8 */ | |
859 | u32 pll_enet_tog; /* 0x0ec */ | |
860 | u32 pfd_480; /* 0x0f0 */ | |
861 | u32 pfd_480_set; /* 0x0f4 */ | |
862 | u32 pfd_480_clr; /* 0x0f8 */ | |
863 | u32 pfd_480_tog; /* 0x0fc */ | |
864 | u32 pfd_528; /* 0x100 */ | |
865 | u32 pfd_528_set; /* 0x104 */ | |
866 | u32 pfd_528_clr; /* 0x108 */ | |
867 | u32 pfd_528_tog; /* 0x10c */ | |
868 | u32 reg_1p1; /* 0x110 */ | |
869 | u32 reg_1p1_set; /* 0x114 */ | |
870 | u32 reg_1p1_clr; /* 0x118 */ | |
871 | u32 reg_1p1_tog; /* 0x11c */ | |
872 | u32 reg_3p0; /* 0x120 */ | |
873 | u32 reg_3p0_set; /* 0x124 */ | |
874 | u32 reg_3p0_clr; /* 0x128 */ | |
875 | u32 reg_3p0_tog; /* 0x12c */ | |
876 | u32 reg_2p5; /* 0x130 */ | |
877 | u32 reg_2p5_set; /* 0x134 */ | |
878 | u32 reg_2p5_clr; /* 0x138 */ | |
879 | u32 reg_2p5_tog; /* 0x13c */ | |
880 | u32 reg_core; /* 0x140 */ | |
881 | u32 reg_core_set; /* 0x144 */ | |
882 | u32 reg_core_clr; /* 0x148 */ | |
883 | u32 reg_core_tog; /* 0x14c */ | |
884 | u32 ana_misc0; /* 0x150 */ | |
885 | u32 ana_misc0_set; /* 0x154 */ | |
886 | u32 ana_misc0_clr; /* 0x158 */ | |
887 | u32 ana_misc0_tog; /* 0x15c */ | |
888 | u32 ana_misc1; /* 0x160 */ | |
889 | u32 ana_misc1_set; /* 0x164 */ | |
890 | u32 ana_misc1_clr; /* 0x168 */ | |
891 | u32 ana_misc1_tog; /* 0x16c */ | |
892 | u32 ana_misc2; /* 0x170 */ | |
893 | u32 ana_misc2_set; /* 0x174 */ | |
894 | u32 ana_misc2_clr; /* 0x178 */ | |
895 | u32 ana_misc2_tog; /* 0x17c */ | |
896 | u32 tempsense0; /* 0x180 */ | |
897 | u32 tempsense0_set; /* 0x184 */ | |
898 | u32 tempsense0_clr; /* 0x188 */ | |
899 | u32 tempsense0_tog; /* 0x18c */ | |
900 | u32 tempsense1; /* 0x190 */ | |
901 | u32 tempsense1_set; /* 0x194 */ | |
902 | u32 tempsense1_clr; /* 0x198 */ | |
903 | u32 tempsense1_tog; /* 0x19c */ | |
904 | u32 usb1_vbus_detect; /* 0x1a0 */ | |
905 | u32 usb1_vbus_detect_set; /* 0x1a4 */ | |
906 | u32 usb1_vbus_detect_clr; /* 0x1a8 */ | |
907 | u32 usb1_vbus_detect_tog; /* 0x1ac */ | |
908 | u32 usb1_chrg_detect; /* 0x1b0 */ | |
909 | u32 usb1_chrg_detect_set; /* 0x1b4 */ | |
910 | u32 usb1_chrg_detect_clr; /* 0x1b8 */ | |
911 | u32 usb1_chrg_detect_tog; /* 0x1bc */ | |
912 | u32 usb1_vbus_det_stat; /* 0x1c0 */ | |
913 | u32 usb1_vbus_det_stat_set; /* 0x1c4 */ | |
914 | u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ | |
915 | u32 usb1_vbus_det_stat_tog; /* 0x1cc */ | |
916 | u32 usb1_chrg_det_stat; /* 0x1d0 */ | |
917 | u32 usb1_chrg_det_stat_set; /* 0x1d4 */ | |
918 | u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ | |
919 | u32 usb1_chrg_det_stat_tog; /* 0x1dc */ | |
920 | u32 usb1_loopback; /* 0x1e0 */ | |
921 | u32 usb1_loopback_set; /* 0x1e4 */ | |
922 | u32 usb1_loopback_clr; /* 0x1e8 */ | |
923 | u32 usb1_loopback_tog; /* 0x1ec */ | |
924 | u32 usb1_misc; /* 0x1f0 */ | |
925 | u32 usb1_misc_set; /* 0x1f4 */ | |
926 | u32 usb1_misc_clr; /* 0x1f8 */ | |
927 | u32 usb1_misc_tog; /* 0x1fc */ | |
928 | u32 usb2_vbus_detect; /* 0x200 */ | |
929 | u32 usb2_vbus_detect_set; /* 0x204 */ | |
930 | u32 usb2_vbus_detect_clr; /* 0x208 */ | |
931 | u32 usb2_vbus_detect_tog; /* 0x20c */ | |
932 | u32 usb2_chrg_detect; /* 0x210 */ | |
933 | u32 usb2_chrg_detect_set; /* 0x214 */ | |
934 | u32 usb2_chrg_detect_clr; /* 0x218 */ | |
935 | u32 usb2_chrg_detect_tog; /* 0x21c */ | |
936 | u32 usb2_vbus_det_stat; /* 0x220 */ | |
937 | u32 usb2_vbus_det_stat_set; /* 0x224 */ | |
938 | u32 usb2_vbus_det_stat_clr; /* 0x228 */ | |
939 | u32 usb2_vbus_det_stat_tog; /* 0x22c */ | |
940 | u32 usb2_chrg_det_stat; /* 0x230 */ | |
941 | u32 usb2_chrg_det_stat_set; /* 0x234 */ | |
942 | u32 usb2_chrg_det_stat_clr; /* 0x238 */ | |
943 | u32 usb2_chrg_det_stat_tog; /* 0x23c */ | |
944 | u32 usb2_loopback; /* 0x240 */ | |
945 | u32 usb2_loopback_set; /* 0x244 */ | |
946 | u32 usb2_loopback_clr; /* 0x248 */ | |
947 | u32 usb2_loopback_tog; /* 0x24c */ | |
948 | u32 usb2_misc; /* 0x250 */ | |
949 | u32 usb2_misc_set; /* 0x254 */ | |
950 | u32 usb2_misc_clr; /* 0x258 */ | |
951 | u32 usb2_misc_tog; /* 0x25c */ | |
952 | u32 digprog; /* 0x260 */ | |
20332a06 TK |
953 | u32 reserved1[7]; |
954 | u32 digprog_sololite; /* 0x280 */ | |
a7683867 FE |
955 | }; |
956 | ||
3fc4176d EN |
957 | #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) |
958 | #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) | |
959 | #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) | |
960 | #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) | |
961 | #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) | |
962 | #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) | |
e66ad6e7 | 963 | |
76c91e66 FE |
964 | struct wdog_regs { |
965 | u16 wcr; /* Control */ | |
966 | u16 wsr; /* Service */ | |
967 | u16 wrsr; /* Reset Status */ | |
968 | u16 wicr; /* Interrupt Control */ | |
969 | u16 wmcr; /* Miscellaneous Control */ | |
970 | }; | |
971 | ||
aafe4020 HS |
972 | #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) |
973 | #define PWMCR_DOZEEN (1 << 24) | |
974 | #define PWMCR_WAITEN (1 << 23) | |
975 | #define PWMCR_DBGEN (1 << 22) | |
976 | #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) | |
977 | #define PWMCR_CLKSRC_IPG (1 << 16) | |
978 | #define PWMCR_EN (1 << 0) | |
979 | ||
980 | struct pwm_regs { | |
981 | u32 cr; | |
982 | u32 sr; | |
983 | u32 ir; | |
984 | u32 sar; | |
985 | u32 pr; | |
986 | u32 cnr; | |
987 | }; | |
23608e23 JL |
988 | #endif /* __ASSEMBLER__*/ |
989 | #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ |