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ec4836be MV |
1 | /* |
2 | * Freescale i.MX28 LRADC Register Definitions | |
3 | * | |
4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
5 | * on behalf of DENX Software Engineering GmbH | |
6 | * | |
7 | * Based on code from LTIB: | |
8 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
ec4836be MV |
11 | */ |
12 | ||
13 | #ifndef __MX28_REGS_LRADC_H__ | |
14 | #define __MX28_REGS_LRADC_H__ | |
15 | ||
0499218d | 16 | #include <asm/imx-common/regs-common.h> |
ec4836be MV |
17 | |
18 | #ifndef __ASSEMBLY__ | |
9c471142 | 19 | struct mxs_lradc_regs { |
ddcf13b1 OS |
20 | mxs_reg_32(hw_lradc_ctrl0); |
21 | mxs_reg_32(hw_lradc_ctrl1); | |
22 | mxs_reg_32(hw_lradc_ctrl2); | |
23 | mxs_reg_32(hw_lradc_ctrl3); | |
24 | mxs_reg_32(hw_lradc_status); | |
25 | mxs_reg_32(hw_lradc_ch0); | |
26 | mxs_reg_32(hw_lradc_ch1); | |
27 | mxs_reg_32(hw_lradc_ch2); | |
28 | mxs_reg_32(hw_lradc_ch3); | |
29 | mxs_reg_32(hw_lradc_ch4); | |
30 | mxs_reg_32(hw_lradc_ch5); | |
31 | mxs_reg_32(hw_lradc_ch6); | |
32 | mxs_reg_32(hw_lradc_ch7); | |
33 | mxs_reg_32(hw_lradc_delay0); | |
34 | mxs_reg_32(hw_lradc_delay1); | |
35 | mxs_reg_32(hw_lradc_delay2); | |
36 | mxs_reg_32(hw_lradc_delay3); | |
37 | mxs_reg_32(hw_lradc_debug0); | |
38 | mxs_reg_32(hw_lradc_debug1); | |
39 | mxs_reg_32(hw_lradc_conversion); | |
40 | mxs_reg_32(hw_lradc_ctrl4); | |
41 | mxs_reg_32(hw_lradc_treshold0); | |
42 | mxs_reg_32(hw_lradc_treshold1); | |
43 | mxs_reg_32(hw_lradc_version); | |
ec4836be MV |
44 | }; |
45 | #endif | |
46 | ||
47 | #define LRADC_CTRL0_SFTRST (1 << 31) | |
48 | #define LRADC_CTRL0_CLKGATE (1 << 30) | |
49 | #define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) | |
50 | #define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) | |
51 | #define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) | |
52 | #define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) | |
53 | #define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) | |
54 | #define LRADC_CTRL0_YNLRSW (1 << 21) | |
55 | #define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) | |
56 | #define LRADC_CTRL0_YPLLSW_OFFSET 19 | |
57 | #define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) | |
58 | #define LRADC_CTRL0_XNURSW_OFFSET 17 | |
59 | #define LRADC_CTRL0_XPULSW (1 << 16) | |
60 | #define LRADC_CTRL0_SCHEDULE_MASK 0xff | |
61 | #define LRADC_CTRL0_SCHEDULE_OFFSET 0 | |
62 | ||
63 | #define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) | |
64 | #define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) | |
65 | #define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) | |
66 | #define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) | |
67 | #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) | |
68 | #define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) | |
69 | #define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) | |
70 | #define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) | |
71 | #define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) | |
72 | #define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) | |
73 | #define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) | |
74 | #define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) | |
75 | #define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) | |
76 | #define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) | |
77 | #define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) | |
78 | #define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) | |
79 | #define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) | |
80 | #define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) | |
81 | #define LRADC_CTRL1_LRADC7_IRQ (1 << 7) | |
82 | #define LRADC_CTRL1_LRADC6_IRQ (1 << 6) | |
83 | #define LRADC_CTRL1_LRADC5_IRQ (1 << 5) | |
84 | #define LRADC_CTRL1_LRADC4_IRQ (1 << 4) | |
85 | #define LRADC_CTRL1_LRADC3_IRQ (1 << 3) | |
86 | #define LRADC_CTRL1_LRADC2_IRQ (1 << 2) | |
87 | #define LRADC_CTRL1_LRADC1_IRQ (1 << 1) | |
88 | #define LRADC_CTRL1_LRADC0_IRQ (1 << 0) | |
89 | ||
90 | #define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) | |
91 | #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 | |
92 | #define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) | |
93 | #define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) | |
94 | #define LRADC_CTRL2_VTHSENSE_OFFSET 13 | |
95 | #define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) | |
96 | #define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) | |
97 | #define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) | |
98 | #define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) | |
99 | #define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 | |
100 | #define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) | |
101 | #define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) | |
102 | #define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) | |
103 | #define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) | |
104 | #define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) | |
105 | #define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) | |
106 | #define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) | |
107 | #define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) | |
108 | #define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) | |
109 | #define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) | |
110 | #define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) | |
111 | #define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) | |
112 | #define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) | |
113 | #define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) | |
114 | #define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) | |
115 | #define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) | |
116 | #define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) | |
117 | #define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 | |
118 | #define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) | |
119 | #define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) | |
120 | #define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) | |
121 | #define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) | |
122 | #define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) | |
123 | #define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) | |
124 | #define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) | |
125 | #define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) | |
126 | #define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) | |
127 | #define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) | |
128 | #define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) | |
129 | #define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) | |
130 | #define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) | |
131 | #define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) | |
132 | #define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) | |
133 | #define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) | |
134 | ||
135 | #define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) | |
136 | #define LRADC_CTRL3_DISCARD_OFFSET 24 | |
137 | #define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) | |
138 | #define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) | |
139 | #define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) | |
140 | #define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) | |
141 | #define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) | |
142 | #define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) | |
143 | #define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 | |
144 | #define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) | |
145 | #define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) | |
146 | #define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) | |
147 | #define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) | |
148 | #define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) | |
149 | #define LRADC_CTRL3_HIGH_TIME_OFFSET 4 | |
150 | #define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) | |
151 | #define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) | |
152 | #define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) | |
153 | #define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) | |
154 | #define LRADC_CTRL3_DELAY_CLOCK (1 << 1) | |
155 | #define LRADC_CTRL3_INVERT_CLOCK (1 << 0) | |
156 | ||
157 | #define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) | |
158 | #define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) | |
159 | #define LRADC_STATUS_TEMP1_PRESENT (1 << 26) | |
160 | #define LRADC_STATUS_TEMP0_PRESENT (1 << 25) | |
161 | #define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) | |
162 | #define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) | |
163 | #define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) | |
164 | #define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) | |
165 | #define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) | |
166 | #define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) | |
167 | #define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) | |
168 | #define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) | |
169 | #define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) | |
170 | #define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) | |
171 | #define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) | |
172 | #define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) | |
173 | ||
174 | #define LRADC_CH_TOGGLE (1 << 31) | |
175 | #define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) | |
176 | #define LRADC_CH_ACCUMULATE (1 << 29) | |
177 | #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) | |
178 | #define LRADC_CH_NUM_SAMPLES_OFFSET 24 | |
179 | #define LRADC_CH_VALUE_MASK 0x3ffff | |
180 | #define LRADC_CH_VALUE_OFFSET 0 | |
181 | ||
182 | #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) | |
183 | #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 | |
184 | #define LRADC_DELAY_KICK (1 << 20) | |
185 | #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) | |
186 | #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 | |
187 | #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) | |
188 | #define LRADC_DELAY_LOOP_COUNT_OFFSET 11 | |
189 | #define LRADC_DELAY_DELAY_MASK 0x7ff | |
190 | #define LRADC_DELAY_DELAY_OFFSET 0 | |
191 | ||
192 | #define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) | |
193 | #define LRADC_DEBUG0_READONLY_OFFSET 16 | |
194 | #define LRADC_DEBUG0_STATE_MASK (0xfff << 0) | |
195 | #define LRADC_DEBUG0_STATE_OFFSET 0 | |
196 | ||
197 | #define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) | |
198 | #define LRADC_DEBUG1_REQUEST_OFFSET 16 | |
199 | #define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) | |
200 | #define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 | |
201 | #define LRADC_DEBUG1_TESTMODE6 (1 << 2) | |
202 | #define LRADC_DEBUG1_TESTMODE5 (1 << 1) | |
203 | #define LRADC_DEBUG1_TESTMODE (1 << 0) | |
204 | ||
205 | #define LRADC_CONVERSION_AUTOMATIC (1 << 20) | |
206 | #define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) | |
207 | #define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 | |
208 | #define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) | |
209 | #define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) | |
210 | #define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) | |
211 | #define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) | |
212 | #define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff | |
213 | #define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 | |
214 | ||
215 | #define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) | |
216 | #define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 | |
217 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) | |
218 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) | |
219 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) | |
220 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) | |
221 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) | |
222 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) | |
223 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) | |
224 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) | |
225 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) | |
226 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) | |
227 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) | |
228 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) | |
229 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) | |
230 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) | |
231 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) | |
232 | #define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) | |
233 | #define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) | |
234 | #define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 | |
235 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) | |
236 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) | |
237 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) | |
238 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) | |
239 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) | |
240 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) | |
241 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) | |
242 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) | |
243 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) | |
244 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) | |
245 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) | |
246 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) | |
247 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) | |
248 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) | |
249 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) | |
250 | #define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) | |
251 | #define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) | |
252 | #define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 | |
253 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) | |
254 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) | |
255 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) | |
256 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) | |
257 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) | |
258 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) | |
259 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) | |
260 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) | |
261 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) | |
262 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) | |
263 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) | |
264 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) | |
265 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) | |
266 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) | |
267 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) | |
268 | #define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) | |
269 | #define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) | |
270 | #define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 | |
271 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) | |
272 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) | |
273 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) | |
274 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) | |
275 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) | |
276 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) | |
277 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) | |
278 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) | |
279 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) | |
280 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) | |
281 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) | |
282 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) | |
283 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) | |
284 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) | |
285 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) | |
286 | #define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) | |
287 | #define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) | |
288 | #define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 | |
289 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) | |
290 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) | |
291 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) | |
292 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) | |
293 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) | |
294 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) | |
295 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) | |
296 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) | |
297 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) | |
298 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) | |
299 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) | |
300 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) | |
301 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) | |
302 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) | |
303 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) | |
304 | #define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) | |
305 | #define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) | |
306 | #define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 | |
307 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) | |
308 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) | |
309 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) | |
310 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) | |
311 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) | |
312 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) | |
313 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) | |
314 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) | |
315 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) | |
316 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) | |
317 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) | |
318 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) | |
319 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) | |
320 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) | |
321 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) | |
322 | #define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) | |
323 | #define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) | |
324 | #define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 | |
325 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) | |
326 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) | |
327 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) | |
328 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) | |
329 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) | |
330 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) | |
331 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) | |
332 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) | |
333 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) | |
334 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) | |
335 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) | |
336 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) | |
337 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) | |
338 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) | |
339 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) | |
340 | #define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) | |
341 | #define LRADC_CTRL4_LRADC0SELECT_MASK 0xf | |
342 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) | |
343 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) | |
344 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) | |
345 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) | |
346 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) | |
347 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) | |
348 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) | |
349 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) | |
350 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) | |
351 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) | |
352 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) | |
353 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) | |
354 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) | |
355 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) | |
356 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) | |
357 | #define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) | |
358 | ||
359 | #define LRADC_THRESHOLD_ENABLE (1 << 24) | |
360 | #define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) | |
361 | #define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) | |
362 | #define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 | |
363 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) | |
364 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) | |
365 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) | |
366 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) | |
367 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) | |
368 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) | |
369 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) | |
370 | #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) | |
371 | #define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) | |
372 | #define LRADC_THRESHOLD_SETTING_OFFSET 18 | |
373 | #define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) | |
374 | #define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) | |
375 | #define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) | |
376 | #define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) | |
377 | #define LRADC_THRESHOLD_VALUE_MASK 0x3ffff | |
378 | #define LRADC_THRESHOLD_VALUE_OFFSET 0 | |
379 | ||
380 | #define LRADC_VERSION_MAJOR_MASK (0xff << 24) | |
381 | #define LRADC_VERSION_MAJOR_OFFSET 24 | |
382 | #define LRADC_VERSION_MINOR_MASK (0xff << 16) | |
383 | #define LRADC_VERSION_MINOR_OFFSET 16 | |
384 | #define LRADC_VERSION_STEP_MASK 0xffff | |
385 | #define LRADC_VERSION_STEP_OFFSET 0 | |
386 | ||
387 | #endif /* __MX28_REGS_LRADC_H__ */ |