projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6e9a0a39 MV |
1 | /* |
| 2 | * Freescale i.MX28 RTC Register Definitions | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
| 5 | * on behalf of DENX Software Engineering GmbH | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 6e9a0a39 MV |
8 | */ |
| 9 | ||
| 10 | #ifndef __MX28_REGS_RTC_H__ | |
| 11 | #define __MX28_REGS_RTC_H__ | |
| 12 | ||
| 552a848e | 13 | #include <asm/mach-imx/regs-common.h> |
| 6e9a0a39 MV |
14 | |
| 15 | #ifndef __ASSEMBLY__ | |
| 9c471142 | 16 | struct mxs_rtc_regs { |
| ddcf13b1 OS |
17 | mxs_reg_32(hw_rtc_ctrl) |
| 18 | mxs_reg_32(hw_rtc_stat) | |
| 19 | mxs_reg_32(hw_rtc_milliseconds) | |
| 20 | mxs_reg_32(hw_rtc_seconds) | |
| 21 | mxs_reg_32(hw_rtc_rtc_alarm) | |
| 22 | mxs_reg_32(hw_rtc_watchdog) | |
| 23 | mxs_reg_32(hw_rtc_persistent0) | |
| 24 | mxs_reg_32(hw_rtc_persistent1) | |
| 25 | mxs_reg_32(hw_rtc_persistent2) | |
| 26 | mxs_reg_32(hw_rtc_persistent3) | |
| 27 | mxs_reg_32(hw_rtc_persistent4) | |
| 28 | mxs_reg_32(hw_rtc_persistent5) | |
| 29 | mxs_reg_32(hw_rtc_debug) | |
| 30 | mxs_reg_32(hw_rtc_version) | |
| 6e9a0a39 MV |
31 | }; |
| 32 | #endif | |
| 33 | ||
| 34 | #define RTC_CTRL_SFTRST (1 << 31) | |
| 35 | #define RTC_CTRL_CLKGATE (1 << 30) | |
| 36 | #define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) | |
| 37 | #define RTC_CTRL_FORCE_UPDATE (1 << 5) | |
| 38 | #define RTC_CTRL_WATCHDOGEN (1 << 4) | |
| 39 | #define RTC_CTRL_ONEMSEC_IRQ (1 << 3) | |
| 40 | #define RTC_CTRL_ALARM_IRQ (1 << 2) | |
| 41 | #define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) | |
| 42 | #define RTC_CTRL_ALARM_IRQ_EN (1 << 0) | |
| 43 | ||
| 44 | #define RTC_STAT_RTC_PRESENT (1 << 31) | |
| 45 | #define RTC_STAT_ALARM_PRESENT (1 << 30) | |
| 46 | #define RTC_STAT_WATCHDOG_PRESENT (1 << 29) | |
| 47 | #define RTC_STAT_XTAL32000_PRESENT (1 << 28) | |
| 48 | #define RTC_STAT_XTAL32768_PRESENT (1 << 27) | |
| 49 | #define RTC_STAT_STALE_REGS_MASK (0xff << 16) | |
| 50 | #define RTC_STAT_STALE_REGS_OFFSET 16 | |
| 51 | #define RTC_STAT_NEW_REGS_MASK (0xff << 8) | |
| 52 | #define RTC_STAT_NEW_REGS_OFFSET 8 | |
| 53 | ||
| 54 | #define RTC_MILLISECONDS_COUNT_MASK 0xffffffff | |
| 55 | #define RTC_MILLISECONDS_COUNT_OFFSET 0 | |
| 56 | ||
| 57 | #define RTC_SECONDS_COUNT_MASK 0xffffffff | |
| 58 | #define RTC_SECONDS_COUNT_OFFSET 0 | |
| 59 | ||
| 60 | #define RTC_ALARM_VALUE_MASK 0xffffffff | |
| 61 | #define RTC_ALARM_VALUE_OFFSET 0 | |
| 62 | ||
| 63 | #define RTC_WATCHDOG_COUNT_MASK 0xffffffff | |
| 64 | #define RTC_WATCHDOG_COUNT_OFFSET 0 | |
| 65 | ||
| 66 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) | |
| 67 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 | |
| 68 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) | |
| 69 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) | |
| 70 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) | |
| 71 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) | |
| 72 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) | |
| 73 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) | |
| 74 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) | |
| 75 | #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) | |
| 76 | #define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) | |
| 77 | #define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) | |
| 78 | #define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) | |
| 79 | #define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) | |
| 80 | #define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) | |
| 81 | #define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) | |
| 82 | #define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 | |
| 83 | #define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) | |
| 84 | #define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) | |
| 85 | #define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) | |
| 86 | #define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) | |
| 87 | #define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) | |
| 88 | #define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 | |
| 89 | #define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) | |
| 90 | #define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) | |
| 91 | #define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) | |
| 92 | #define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) | |
| 93 | #define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) | |
| 94 | #define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) | |
| 95 | #define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) | |
| 96 | #define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) | |
| 97 | #define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) | |
| 98 | #define RTC_PERSISTENT0_LCK_SECS (1 << 3) | |
| 99 | #define RTC_PERSISTENT0_ALARM_EN (1 << 2) | |
| 100 | #define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) | |
| 101 | #define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) | |
| 102 | ||
| 103 | #define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff | |
| 104 | #define RTC_PERSISTENT1_GENERAL_OFFSET 0 | |
| 105 | #define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 | |
| 106 | #define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 | |
| 107 | #define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 | |
| 108 | #define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 | |
| 109 | #define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 | |
| 110 | #define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 | |
| 111 | ||
| 112 | #define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff | |
| 113 | #define RTC_PERSISTENT2_GENERAL_OFFSET 0 | |
| 114 | ||
| 115 | #define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff | |
| 116 | #define RTC_PERSISTENT3_GENERAL_OFFSET 0 | |
| 117 | ||
| 118 | #define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff | |
| 119 | #define RTC_PERSISTENT4_GENERAL_OFFSET 0 | |
| 120 | ||
| 121 | #define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff | |
| 122 | #define RTC_PERSISTENT5_GENERAL_OFFSET 0 | |
| 123 | ||
| 124 | #define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) | |
| 125 | #define RTC_DEBUG_WATCHDOG_RESET (1 << 0) | |
| 126 | ||
| 127 | #define RTC_VERSION_MAJOR_MASK (0xff << 24) | |
| 128 | #define RTC_VERSION_MAJOR_OFFSET 24 | |
| 129 | #define RTC_VERSION_MINOR_MASK (0xff << 16) | |
| 130 | #define RTC_VERSION_MINOR_OFFSET 16 | |
| 131 | #define RTC_VERSION_STEP_MASK 0xffff | |
| 132 | #define RTC_VERSION_STEP_OFFSET 0 | |
| 133 | ||
| 134 | #endif /* __MX28_REGS_RTC_H__ */ |