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| Commit | Line | Data |
|---|---|---|
| 6e9a0a39 | 1 | /* |
| 6e829b67 | 2 | * Freescale i.MX23/i.MX28 specific functions |
| 6e9a0a39 MV |
3 | * |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
| 5 | * on behalf of DENX Software Engineering GmbH | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 6e9a0a39 MV |
8 | */ |
| 9 | ||
| fc684e87 PF |
10 | #ifndef __MXS_SYS_PROTO_H__ |
| 11 | #define __MXS_SYS_PROTO_H__ | |
| 6e9a0a39 | 12 | |
| 552a848e | 13 | #include <asm/mach-imx/sys_proto.h> |
| 6e9a0a39 | 14 | |
| 90bc2bf2 | 15 | int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); |
| 71a758e1 | 16 | |
| c944a3ef | 17 | #ifdef CONFIG_SPL_BUILD |
| 180f47a8 OS |
18 | |
| 19 | #if defined(CONFIG_MX23) | |
| 20 | #include <asm/arch/iomux-mx23.h> | |
| 21 | #elif defined(CONFIG_MX28) | |
| c944a3ef | 22 | #include <asm/arch/iomux-mx28.h> |
| 180f47a8 OS |
23 | #endif |
| 24 | ||
| 7b8657e2 MV |
25 | void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, |
| 26 | const iomux_cfg_t *iomux_setup, | |
| 27 | const unsigned int iomux_size); | |
| fe21eaf9 MH |
28 | |
| 29 | void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); | |
| c944a3ef MV |
30 | #endif |
| 31 | ||
| fa7a51cb | 32 | struct mxs_pair { |
| f8c4a86b MV |
33 | uint8_t boot_pads; |
| 34 | uint8_t boot_mask; | |
| 35 | const char *mode; | |
| 36 | }; | |
| 37 | ||
| fa7a51cb | 38 | static const struct mxs_pair mxs_boot_modes[] = { |
| a8b2884d OS |
39 | #if defined(CONFIG_MX23) |
| 40 | { 0x00, 0x0f, "USB" }, | |
| 41 | { 0x01, 0x1f, "I2C, master" }, | |
| 42 | { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, | |
| 43 | { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, | |
| 44 | { 0x04, 0x1f, "NAND" }, | |
| 77b0e223 | 45 | { 0x06, 0x1f, "JTAG" }, |
| a8b2884d OS |
46 | { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, |
| 47 | { 0x09, 0x1f, "SSP SD/MMC #0" }, | |
| 48 | { 0x0a, 0x1f, "SSP SD/MMC #1" }, | |
| 49 | { 0x00, 0x00, "Reserved/Unknown/Wrong" }, | |
| 50 | #elif defined(CONFIG_MX28) | |
| f8c4a86b MV |
51 | { 0x00, 0x0f, "USB #0" }, |
| 52 | { 0x01, 0x1f, "I2C #0, master, 3V3" }, | |
| 53 | { 0x11, 0x1f, "I2C #0, master, 1V8" }, | |
| 54 | { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, | |
| 55 | { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, | |
| 56 | { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, | |
| 57 | { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, | |
| 58 | { 0x04, 0x1f, "NAND, 3V3" }, | |
| 59 | { 0x14, 0x1f, "NAND, 1V8" }, | |
| 77b0e223 | 60 | { 0x06, 0x1f, "JTAG" }, |
| f8c4a86b MV |
61 | { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, |
| 62 | { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, | |
| 63 | { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, | |
| 64 | { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, | |
| 65 | { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, | |
| 66 | { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, | |
| 67 | { 0x00, 0x00, "Reserved/Unknown/Wrong" }, | |
| a8b2884d | 68 | #endif |
| f8c4a86b MV |
69 | }; |
| 70 | ||
| 2d6286ab GR |
71 | #define MXS_BM_USB 0x00 |
| 72 | #define MXS_BM_I2C_MASTER_3V3 0x01 | |
| 73 | #define MXS_BM_I2C_MASTER_1V8 0x11 | |
| 74 | #define MXS_BM_SPI2_MASTER_3V3_NOR 0x02 | |
| 75 | #define MXS_BM_SPI2_MASTER_1V8_NOR 0x12 | |
| 76 | #define MXS_BM_SPI3_MASTER_3V3_NOR 0x03 | |
| 77 | #define MXS_BM_SPI3_MASTER_1V8_NOR 0x13 | |
| 78 | #define MXS_BM_NAND_3V3 0x04 | |
| 79 | #define MXS_BM_NAND_1V8 0x14 | |
| 80 | #define MXS_BM_JTAG 0x06 | |
| 81 | #define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08 | |
| 82 | #define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18 | |
| 83 | #define MXS_BM_SDMMC0_3V3 0x09 | |
| 84 | #define MXS_BM_SDMMC0_1V8 0x19 | |
| 85 | #define MXS_BM_SDMMC1_3V3 0x0a | |
| 86 | #define MXS_BM_SDMMC1_1V8 0x1a | |
| 87 | ||
| 1e0cf5c3 | 88 | struct mxs_spl_data { |
| f8c4a86b | 89 | uint8_t boot_mode_idx; |
| 0239c2fb MV |
90 | uint32_t mem_dram_size; |
| 91 | }; | |
| 92 | ||
| 72f8ebf1 | 93 | int mxs_dram_init(void); |
| 5bcc6a89 | 94 | |
| fa7a51cb | 95 | #endif /* __SYS_PROTO_H__ */ |