projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8ed96046 WD |
1 | /* |
| 2 | * (C) Copyright 2004 | |
| 3 | * Texas Instruments, <www.ti.com> | |
| 4 | * Richard Woodruff <r-woodruff2@ti.com> | |
| 5 | * | |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 49a7581c | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 8ed96046 WD |
17 | * GNU General Public License for more details. |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef _OMAP24XX_MEM_H_ | |
| 26 | #define _OMAP24XX_MEM_H_ | |
| 27 | ||
| 49a7581c WD |
28 | #define SDRC_CS0_OSET 0x0 |
| 29 | #define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ | |
| 8ed96046 WD |
30 | |
| 31 | #ifndef __ASSEMBLY__ | |
| 32 | /* struct's for holding data tables for current boards, they are getting used | |
| 33 | early in init when NO global access are there */ | |
| 34 | struct sdrc_data_s { | |
| 35 | u32 sdrc_sharing; | |
| 289f932c WD |
36 | u32 sdrc_mdcfg_0_ddr; |
| 37 | u32 sdrc_mdcfg_0_sdr; | |
| 8ed96046 WD |
38 | u32 sdrc_actim_ctrla_0; |
| 39 | u32 sdrc_actim_ctrlb_0; | |
| 40 | u32 sdrc_rfr_ctrl; | |
| 289f932c WD |
41 | u32 sdrc_mr_0_ddr; |
| 42 | u32 sdrc_mr_0_sdr; | |
| 49a7581c | 43 | u32 sdrc_dllab_ctrl; |
| 8ed96046 WD |
44 | } /*__attribute__ ((packed))*/; |
| 45 | typedef struct sdrc_data_s sdrc_data_t; | |
| 289f932c WD |
46 | |
| 47 | typedef enum { | |
| 48 | STACKED = 0, | |
| 49 | IP_DDR = 1, | |
| 50 | COMBO_DDR = 2, | |
| 49a7581c | 51 | IP_SDR = 3, |
| 289f932c WD |
52 | } mem_t; |
| 53 | ||
| 8ed96046 WD |
54 | #endif |
| 55 | ||
| 56 | /* Slower full frequency range default timings for x32 operation*/ | |
| 49a7581c | 57 | #define H4_2420_SDRC_SHARING 0x00000100 |
| 289f932c WD |
58 | #define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ |
| 59 | #define H4_2420_SDRC_MR_0_SDR 0x00000031 | |
| 60 | #define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ | |
| 61 | #define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ | |
| 62 | #define H4_2420_SDRC_MR_0_DDR 0x00000032 | |
| 63 | ||
| 289f932c WD |
64 | #define H4_2422_SDRC_SHARING 0x00004b00 |
| 65 | #define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ | |
| 289f932c | 66 | #define H4_2422_SDRC_MR_0_DDR 0x00000032 |
| 8ed96046 | 67 | |
| 49a7581c WD |
68 | /* ES1 work around timings */ |
| 69 | #define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ | |
| 70 | #define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 | |
| 71 | #define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ | |
| 72 | ||
| 73 | /* optimized timings good for current shipping parts */ | |
| 289f932c WD |
74 | #define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 |
| 75 | #define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e | |
| 49a7581c WD |
76 | #define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ |
| 77 | #define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ | |
| 78 | #define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 | |
| 79 | #define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 | |
| 80 | #define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ | |
| 81 | #define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ | |
| 82 | ||
| 83 | #ifdef PRCM_CONFIG_II | |
| 84 | # define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz | |
| 85 | # define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz | |
| 86 | # define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz | |
| 87 | # define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz | |
| 88 | # define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz | |
| 89 | # define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz | |
| 90 | # define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz | |
| 91 | # define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz | |
| 92 | #elif PRCM_CONFIG_III | |
| 93 | # define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz | |
| 94 | # define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz | |
| 95 | # define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz | |
| 96 | # define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz | |
| 97 | # define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz | |
| 98 | # define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz | |
| 99 | # define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz | |
| 100 | # define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz | |
| 289f932c | 101 | #endif |
| 8ed96046 WD |
102 | |
| 103 | ||
| 289f932c | 104 | /* GPMC settings */ |
| 49a7581c | 105 | #ifdef PRCM_CONFIG_II /* L3 at 100MHz */ |
| 6d0f6bcf | 106 | # ifdef CONFIG_SYS_NAND_BOOT |
| 49a7581c WD |
107 | # define H4_24XX_GPMC_CONFIG1_0 0x0 |
| 108 | # define H4_24XX_GPMC_CONFIG2_0 0x00141400 | |
| 109 | # define H4_24XX_GPMC_CONFIG3_0 0x00141400 | |
| 110 | # define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 | |
| 111 | # define H4_24XX_GPMC_CONFIG5_0 0x010C1414 | |
| 112 | # define H4_24XX_GPMC_CONFIG6_0 0x00000A80 | |
| 113 | # else /* else NOR */ | |
| 114 | # define H4_24XX_GPMC_CONFIG1_0 0x3 | |
| 115 | # define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 | |
| 116 | # define H4_24XX_GPMC_CONFIG3_0 0x00050502 | |
| 117 | # define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 | |
| 118 | # define H4_24XX_GPMC_CONFIG5_0 0x01131F1F | |
| 6d0f6bcf | 119 | # endif /* endif CONFIG_SYS_NAND_BOOT */ |
| 49a7581c WD |
120 | # define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) |
| 121 | # define H4_24XX_GPMC_CONFIG1_1 0x00011000 | |
| 122 | # define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 | |
| 123 | # define H4_24XX_GPMC_CONFIG3_1 0x00080802 | |
| 124 | # define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 | |
| 125 | # define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F | |
| 126 | # define H4_24XX_GPMC_CONFIG6_1 0x000003C2 | |
| 127 | # define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) | |
| 128 | #endif /* endif PRCM_CONFIG_II */ | |
| 129 | ||
| 130 | #ifdef PRCM_CONFIG_III /* L3 at 133MHz */ | |
| 6d0f6bcf | 131 | # ifdef CONFIG_SYS_NAND_BOOT |
| 49a7581c WD |
132 | # define H4_24XX_GPMC_CONFIG1_0 0x0 |
| 133 | # define H4_24XX_GPMC_CONFIG2_0 0x00141400 | |
| 134 | # define H4_24XX_GPMC_CONFIG3_0 0x00141400 | |
| 135 | # define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 | |
| 136 | # define H4_24XX_GPMC_CONFIG5_0 0x010C1414 | |
| 137 | # define H4_24XX_GPMC_CONFIG6_0 0x00000A80 | |
| 138 | # else /* NOR boot */ | |
| 139 | # define H4_24XX_GPMC_CONFIG1_0 0x3 | |
| 140 | # define H4_24XX_GPMC_CONFIG2_0 0x00151501 | |
| 141 | # define H4_24XX_GPMC_CONFIG3_0 0x00060602 | |
| 142 | # define H4_24XX_GPMC_CONFIG4_0 0x10081008 | |
| 143 | # define H4_24XX_GPMC_CONFIG5_0 0x01131F1F | |
| 144 | # define H4_24XX_GPMC_CONFIG6_0 0x000004c4 | |
| 6d0f6bcf | 145 | # endif /* endif CONFIG_SYS_NAND_BOOT */ |
| 49a7581c WD |
146 | # define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) |
| 147 | # define H4_24XX_GPMC_CONFIG1_1 0x00011000 | |
| 148 | # define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 | |
| 149 | # define H4_24XX_GPMC_CONFIG3_1 0x00080803 | |
| 150 | # define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 | |
| 151 | # define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F | |
| 152 | # define H4_24XX_GPMC_CONFIG6_1 0x000004C4 | |
| 153 | # define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) | |
| 6d0f6bcf | 154 | #endif /* endif CONFIG_SYS_PRCM_III */ |
| 49a7581c WD |
155 | |
| 156 | #endif /* endif _OMAP24XX_MEM_H_ */ |