[people/ms/u-boot.git] / arch / arm / include / asm / arch-omap3 / cpu.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments, <www.ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#ifndef _CPU_H
#define _CPU_H

#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */

/* Register offsets of common modules */
/* Control */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct ctrl {
	u8 res1[0xC0];
	u16 gpmc_nadv_ale;	/* 0xC0 */
	u16 gpmc_noe;		/* 0xC2 */
	u16 gpmc_nwe;		/* 0xC4 */
	u8 res2[0x22A];
	u32 status;		/* 0x2F0 */
	u32 gpstatus;		/* 0x2F4 */
	u8 res3[0x08];
	u32 rpubkey_0;		/* 0x300 */
	u32 rpubkey_1;		/* 0x304 */
	u32 rpubkey_2;		/* 0x308 */
	u32 rpubkey_3;		/* 0x30C */
	u32 rpubkey_4;		/* 0x310 */
	u8 res4[0x04];
	u32 randkey_0;		/* 0x318 */
	u32 randkey_1;		/* 0x31C */
	u32 randkey_2;		/* 0x320 */
	u32 randkey_3;		/* 0x324 */
	u8 res5[0x124];
	u32 ctrl_omap_stat;	/* 0x44C */
};
#else /* __ASSEMBLY__ */
#define CONTROL_STATUS		0x2F0
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct ctrl_id {
	u8 res1[0x4];
	u32 idcode;		/* 0x04 */
	u32 prod_id;		/* 0x08 */
	u32 sku_id;		/* 0x0c */
	u8 res2[0x08];
	u32 die_id_0;		/* 0x18 */
	u32 die_id_1;		/* 0x1C */
	u32 die_id_2;		/* 0x20 */
	u32 die_id_3;		/* 0x24 */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

/* device type */
#define DEVICE_MASK		(0x7 << 8)
#define SYSBOOT_MASK		0x1F
#define TST_DEVICE		0x0
#define EMU_DEVICE		0x1
#define HS_DEVICE		0x2
#define GP_DEVICE		0x3

/* device speed */
#define SKUID_CLK_MASK		0xf
#define SKUID_CLK_600MHZ	0x0
#define SKUID_CLK_720MHZ	0x8

#define GPMC_BASE		(OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0		0x60
#define GPMC_CONFIG_CS0_BASE	(GPMC_BASE + GPMC_CONFIG_CS0)

#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gpmc_cs {
	u32 config1;		/* 0x00 */
	u32 config2;		/* 0x04 */
	u32 config3;		/* 0x08 */
	u32 config4;		/* 0x0C */
	u32 config5;		/* 0x10 */
	u32 config6;		/* 0x14 */
	u32 config7;		/* 0x18 */
	u32 nand_cmd;		/* 0x1C */
	u32 nand_adr;		/* 0x20 */
	u32 nand_dat;		/* 0x24 */
	u8 res[8];		/* blow up to 0x30 byte */
};

struct gpmc {
	u8 res1[0x10];
	u32 sysconfig;		/* 0x10 */
	u8 res2[0x4];
	u32 irqstatus;		/* 0x18 */
	u32 irqenable;		/* 0x1C */
	u8 res3[0x20];
	u32 timeout_control; 	/* 0x40 */
	u8 res4[0xC];
	u32 config;		/* 0x50 */
	u32 status;		/* 0x54 */
	u8 res5[0x8];	/* 0x58 */
	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
	u8 res6[0x14];		/* 0x1E0 */
	u32 ecc_config;		/* 0x1F4 */
	u32 ecc_control;	/* 0x1F8 */
	u32 ecc_size_config;	/* 0x1FC */
	u32 ecc1_result;	/* 0x200 */
	u32 ecc2_result;	/* 0x204 */
	u32 ecc3_result;	/* 0x208 */
	u32 ecc4_result;	/* 0x20C */
	u32 ecc5_result;	/* 0x210 */
	u32 ecc6_result;	/* 0x214 */
	u32 ecc7_result;	/* 0x218 */
	u32 ecc8_result;	/* 0x21C */
	u32 ecc9_result;	/* 0x220 */
};

/* Used for board specific gpmc initialization */
extern struct gpmc *gpmc_cfg;

#else /* __ASSEMBLY__ */
#define GPMC_CONFIG1		0x00
#define GPMC_CONFIG2		0x04
#define GPMC_CONFIG3		0x08
#define GPMC_CONFIG4		0x0C
#define GPMC_CONFIG5		0x10
#define GPMC_CONFIG6		0x14
#define GPMC_CONFIG7		0x18
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

/* GPMC Mapping */
#define FLASH_BASE		0x10000000	/* NOR flash, */
						/* aligned to 256 Meg */
#define FLASH_BASE_SDPV1	0x04000000	/* NOR flash, */
						/* aligned to 64 Meg */
#define FLASH_BASE_SDPV2	0x10000000	/* NOR flash, */
						/* aligned to 256 Meg */
#define DEBUG_BASE		0x08000000	/* debug board */
#define NAND_BASE		0x30000000	/* NAND addr */
						/* (actual size small port) */
#define PISMO2_BASE		0x18000000	/* PISMO2 CS1/2 */
#define ONENAND_MAP		0x20000000	/* OneNand addr */
						/* (actual size small port) */
/* SMS */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct sms {
	u8 res1[0x10];
	u32 sysconfig;		/* 0x10 */
	u8 res2[0x34];
	u32 rg_att0;		/* 0x48 */
	u8 res3[0x84];
	u32 class_arb0;		/* 0xD0 */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

#define BURSTCOMPLETE_GROUP7	(0x1 << 31)

/* SDRC */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct sdrc_cs {
	u32 mcfg;		/* 0x80 || 0xB0 */
	u32 mr;			/* 0x84 || 0xB4 */
	u8 res1[0x4];
	u32 emr2;		/* 0x8C || 0xBC */
	u8 res2[0x14];
	u32 rfr_ctrl;		/* 0x84 || 0xD4 */
	u32 manual;		/* 0xA8 || 0xD8 */
	u8 res3[0x4];
};

struct sdrc_actim {
	u32 ctrla;		/* 0x9C || 0xC4 */
	u32 ctrlb;		/* 0xA0 || 0xC8 */
};

struct sdrc {
	u8 res1[0x10];
	u32 sysconfig;		/* 0x10 */
	u32 status;		/* 0x14 */
	u8 res2[0x28];
	u32 cs_cfg;		/* 0x40 */
	u32 sharing;		/* 0x44 */
	u8 res3[0x18];
	u32 dlla_ctrl;		/* 0x60 */
	u32 dlla_status;	/* 0x64 */
	u32 dllb_ctrl;		/* 0x68 */
	u32 dllb_status;	/* 0x6C */
	u32 power;		/* 0x70 */
	u8 res4[0xC];
	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
};

/* EMIF4 */
typedef struct emif4 {
	unsigned int emif_mod_id_rev;
	unsigned int sdram_sts;
	unsigned int sdram_config;
	unsigned int res1;
	unsigned int sdram_refresh_ctrl;
	unsigned int sdram_refresh_ctrl_shdw;
	unsigned int sdram_time1;
	unsigned int sdram_time1_shdw;
	unsigned int sdram_time2;
	unsigned int sdram_time2_shdw;
	unsigned int sdram_time3;
	unsigned int sdram_time3_shdw;
	unsigned char res2[8];
	unsigned int sdram_pwr_mgmt;
	unsigned int sdram_pwr_mgmt_shdw;
	unsigned char res3[32];
	unsigned int sdram_iodft_tlgc;
	unsigned char res4[128];
	unsigned int ddr_phyctrl1;
	unsigned int ddr_phyctrl1_shdw;
	unsigned int ddr_phyctrl2;
} emif4_t;

#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

#define DLLPHASE_90		(0x1 << 1)
#define LOADDLL			(0x1 << 2)
#define ENADLL			(0x1 << 3)
#define DLL_DELAY_MASK		0xFF00
#define DLL_NO_FILTER_MASK	((0x1 << 9) | (0x1 << 8))

#define PAGEPOLICY_HIGH		(0x1 << 0)
#define SRFRONRESET		(0x1 << 7)
#define PWDNEN			(0x1 << 2)
#define WAKEUPPROC		(0x1 << 26)

#define DDR_SDRAM		(0x1 << 0)
#define DEEPPD			(0x1 << 3)
#define B32NOT16		(0x1 << 4)
#define BANKALLOCATION		(0x2 << 6)
#define RAMSIZE_128		(0x40 << 8) /* RAM size in 2MB chunks */
#define ADDRMUXLEGACY		(0x1 << 19)
#define CASWIDTH_10BITS		(0x5 << 20)
#define RASWIDTH_13BITS		(0x2 << 24)
#define BURSTLENGTH4		(0x2 << 0)
#define CASL3			(0x3 << 4)
#define SDRC_ACTIM_CTRL0_BASE	(OMAP34XX_SDRC_BASE + 0x9C)
#define SDRC_ACTIM_CTRL1_BASE	(OMAP34XX_SDRC_BASE + 0xC4)
#define ARE_ARCV_1		(0x1 << 0)
#define ARCV			(0x4e2 << 8) /* Autorefresh count */
#define OMAP34XX_SDRC_CS0	0x80000000
#define OMAP34XX_SDRC_CS1	0xA0000000
#define CMD_NOP			0x0
#define CMD_PRECHARGE		0x1
#define CMD_AUTOREFRESH		0x2
#define CMD_ENTR_PWRDOWN	0x3
#define CMD_EXIT_PWRDOWN	0x4
#define CMD_ENTR_SRFRSH		0x5
#define CMD_CKE_HIGH		0x6
#define CMD_CKE_LOW		0x7
#define SOFTRESET		(0x1 << 1)
#define SMART_IDLE		(0x2 << 3)
#define REF_ON_IDLE		(0x1 << 6)

/* DMA */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct dma4_chan {
	u32 ccr;
	u32 clnk_ctrl;
	u32 cicr;
	u32 csr;
	u32 csdp;
	u32 cen;
	u32 cfn;
	u32 cssa;
	u32 cdsa;
	u32 csel;
	u32 csfl;
	u32 cdel;
	u32 cdfl;
	u32 csac;
	u32 cdac;
	u32 ccen;
	u32 ccfn;
	u32 color;
};

struct dma4 {
	u32 revision;
	u8 res1[0x4];
	u32 irqstatus_l[0x4];
	u32 irqenable_l[0x4];
	u32 sysstatus;
	u32 ocp_sysconfig;
	u8 res2[0x34];
	u32 caps_0;
	u8 res3[0x4];
	u32 caps_2;
	u32 caps_3;
	u32 caps_4;
	u32 gcr;
	u8 res4[0x4];
	struct dma4_chan chan[32];
};

#endif /*__ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

/* timer regs offsets (32 bit regs) */

#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gptimer {
	u32 tidr;	/* 0x00 r */
	u8 res[0xc];
	u32 tiocp_cfg;	/* 0x10 rw */
	u32 tistat;	/* 0x14 r */
	u32 tisr;	/* 0x18 rw */
	u32 tier;	/* 0x1c rw */
	u32 twer;	/* 0x20 rw */
	u32 tclr;	/* 0x24 rw */
	u32 tcrr;	/* 0x28 rw */
	u32 tldr;	/* 0x2c rw */
	u32 ttgr;	/* 0x30 rw */
	u32 twpc;	/* 0x34 r*/
	u32 tmar;	/* 0x38 rw*/
	u32 tcar1;	/* 0x3c r */
	u32 tcicr;	/* 0x40 rw */
	u32 tcar2;	/* 0x44 r */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

/* enable sys_clk NO-prescale /1 */
#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))

/* Watchdog */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct watchdog {
	u8 res1[0x34];
	u32 wwps;	/* 0x34 r */
	u8 res2[0x10];
	u32 wspr;	/* 0x48 rw */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

#define WD_UNLOCK1		0xAAAA
#define WD_UNLOCK2		0x5555

/* PRCM */
#define PRCM_BASE		0x48004000

#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct prcm {
	u32 fclken_iva2;	/* 0x00 */
	u32 clken_pll_iva2;	/* 0x04 */
	u8 res1[0x1c];
	u32 idlest_pll_iva2;	/* 0x24 */
	u8 res2[0x18];
	u32 clksel1_pll_iva2 ;	/* 0x40 */
	u32 clksel2_pll_iva2;	/* 0x44 */
	u8 res3[0x8bc];
	u32 clken_pll_mpu;	/* 0x904 */
	u8 res4[0x1c];
	u32 idlest_pll_mpu;	/* 0x924 */
	u8 res5[0x18];
	u32 clksel1_pll_mpu;	/* 0x940 */
	u32 clksel2_pll_mpu;	/* 0x944 */
	u8 res6[0xb8];
	u32 fclken1_core;	/* 0xa00 */
	u32 res_fclken2_core;
	u32 fclken3_core;	/* 0xa08 */
	u8 res7[0x4];
	u32 iclken1_core;	/* 0xa10 */
	u32 iclken2_core;	/* 0xa14 */
	u32 iclken3_core;	/* 0xa18 */
	u8 res8[0x24];
	u32 clksel_core;	/* 0xa40 */
	u8 res9[0xbc];
	u32 fclken_gfx;		/* 0xb00 */
	u8 res10[0xc];
	u32 iclken_gfx;		/* 0xb10 */
	u8 res11[0x2c];
	u32 clksel_gfx;		/* 0xb40 */
	u8 res12[0xbc];
	u32 fclken_wkup;	/* 0xc00 */
	u8 res13[0xc];
	u32 iclken_wkup;	/* 0xc10 */
	u8 res14[0xc];
	u32 idlest_wkup;	/* 0xc20 */
	u8 res15[0x1c];
	u32 clksel_wkup;	/* 0xc40 */
	u8 res16[0xbc];
	u32 clken_pll;		/* 0xd00 */
	u32 clken2_pll;	        /* 0xd04 */
	u8 res17[0x18];
	u32 idlest_ckgen;	/* 0xd20 */
	u32 idlest2_ckgen;	/* 0xd24 */
	u8 res18[0x18];
	u32 clksel1_pll;	/* 0xd40 */
	u32 clksel2_pll;	/* 0xd44 */
	u32 clksel3_pll;	/* 0xd48 */
	u32 clksel4_pll;	/* 0xd4c */
	u32 clksel5_pll;	/* 0xd50 */
	u8 res19[0xac];
	u32 fclken_dss;		/* 0xe00 */
	u8 res20[0xc];
	u32 iclken_dss;		/* 0xe10 */
	u8 res21[0x2c];
	u32 clksel_dss;		/* 0xe40 */
	u8 res22[0xbc];
	u32 fclken_cam;		/* 0xf00 */
	u8 res23[0xc];
	u32 iclken_cam;		/* 0xf10 */
	u8 res24[0x2c];
	u32 clksel_cam;		/* 0xf40 */
	u8 res25[0xbc];
	u32 fclken_per;		/* 0x1000 */
	u8 res26[0xc];
	u32 iclken_per;		/* 0x1010 */
	u8 res27[0x2c];
	u32 clksel_per;		/* 0x1040 */
	u8 res28[0xfc];
	u32 clksel1_emu;	/* 0x1140 */
	u8 res29[0x2bc];
	u32 fclken_usbhost;	/* 0x1400 */
	u8 res30[0xc];
	u32 iclken_usbhost;	/* 0x1410 */
};
#else /* __ASSEMBLY__ */
#define CM_CLKSEL_CORE		0x48004a40
#define CM_CLKSEL_GFX		0x48004b40
#define CM_CLKSEL_WKUP		0x48004c40
#define CM_CLKEN_PLL		0x48004d00
#define CM_CLKSEL1_PLL		0x48004d40
#define CM_CLKSEL1_EMU		0x48005140
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

#define PRM_BASE		0x48306000

#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct prm {
	u8 res1[0xd40];
	u32 clksel;		/* 0xd40 */
	u8 res2[0x50c];
	u32 rstctrl;		/* 0x1250 */
	u8 res3[0x1c];
	u32 clksrc_ctrl;	/* 0x1270 */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

#define PRM_RSTCTRL		0x48307250
#define PRM_RSTCTRL_RESET	0x04
#define PRM_RSTST			0x48307258
#define PRM_RSTST_WARM_RESET_MASK	0x7D2
#define SYSCLKDIV_1		(0x1 << 6)
#define SYSCLKDIV_2		(0x1 << 7)

#define CLKSEL_GPT1		(0x1 << 0)

#define EN_GPT1			(0x1 << 0)
#define EN_32KSYNC		(0x1 << 2)

#define ST_WDT2			(0x1 << 5)

#define ST_MPU_CLK		(0x1 << 0)

#define ST_CORE_CLK		(0x1 << 0)

#define ST_PERIPH_CLK		(0x1 << 1)

#define ST_IVA2_CLK		(0x1 << 0)

#define RESETDONE		(0x1 << 0)

#define TCLR_ST			(0x1 << 0)
#define TCLR_AR			(0x1 << 1)
#define TCLR_PRE		(0x1 << 5)

/* SMX-APE */
#define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)
#define PM_GPMC_BASE_ADDR_ARM		(SMX_APE_BASE + 0x12400)
#define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
#define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)

#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct pm {
	u8 res1[0x48];
	u32 req_info_permission_0;	/* 0x48 */
	u8 res2[0x4];
	u32 read_permission_0;		/* 0x50 */
	u8 res3[0x4];
	u32 wirte_permission_0;		/* 0x58 */
	u8 res4[0x4];
	u32 addr_match_1;		/* 0x58 */
	u8 res5[0x4];
	u32 req_info_permission_1;	/* 0x68 */
	u8 res6[0x14];
	u32 addr_match_2;		/* 0x80 */
};
#endif /*__ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

/* Permission values for registers -Full fledged permissions to all */
#define UNLOCK_1			0xFFFFFFFF
#define UNLOCK_2			0x00000000
#define UNLOCK_3			0x0000FFFF

#define NOT_EARLY			0

/* I2C base */
#define I2C_BASE1		(OMAP34XX_CORE_L4_IO_BASE + 0x70000)
#define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
#define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)

/* MUSB base */
#define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)

/* OMAP3 GPIO registers */
#define OMAP_GPIO_REVISION		0x0000
#define OMAP_GPIO_SYSCONFIG		0x0010
#define OMAP_GPIO_SYSSTATUS		0x0014
#define OMAP_GPIO_IRQSTATUS1		0x0018
#define OMAP_GPIO_IRQSTATUS2		0x0028
#define OMAP_GPIO_IRQENABLE2		0x002c
#define OMAP_GPIO_IRQENABLE1		0x001c
#define OMAP_GPIO_WAKE_EN		0x0020
#define OMAP_GPIO_CTRL			0x0030
#define OMAP_GPIO_OE			0x0034
#define OMAP_GPIO_DATAIN		0x0038
#define OMAP_GPIO_DATAOUT		0x003c
#define OMAP_GPIO_LEVELDETECT0		0x0040
#define OMAP_GPIO_LEVELDETECT1		0x0044
#define OMAP_GPIO_RISINGDETECT		0x0048
#define OMAP_GPIO_FALLINGDETECT		0x004c
#define OMAP_GPIO_DEBOUNCE_EN		0x0050
#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
#define OMAP_GPIO_SETIRQENABLE1		0x0064
#define OMAP_GPIO_CLEARWKUENA		0x0080
#define OMAP_GPIO_SETWKUENA		0x0084
#define OMAP_GPIO_CLEARDATAOUT		0x0090
#define OMAP_GPIO_SETDATAOUT		0x0094

#endif /* _CPU_H */
Commit	Line	Data
2c803210 DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#ifndef _CPU_H
	26	#define _CPU_H
	27
a3d1421d DB	28	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
	29	#include <asm/types.h>
	30	#endif /* !(__KERNEL_STRICT_NAMES \|\| __ASSEMBLY__) */
	31
2c803210 DB	32	/* Register offsets of common modules */
2c803210 DB	33	/* Control */
a3d1421d	34	#ifndef __KERNEL_STRICT_NAMES
2c803210	35	#ifndef __ASSEMBLY__
97a099ea	36	struct ctrl {
a3d1421d DB	37	u8 res1[0xC0];
	38	u16 gpmc_nadv_ale; /* 0xC0 */
	39	u16 gpmc_noe; /* 0xC2 */
	40	u16 gpmc_nwe; /* 0xC4 */
	41	u8 res2[0x22A];
	42	u32 status; /* 0x2F0 */
	43	u32 gpstatus; /* 0x2F4 */
	44	u8 res3[0x08];
	45	u32 rpubkey_0; /* 0x300 */
	46	u32 rpubkey_1; /* 0x304 */
	47	u32 rpubkey_2; /* 0x308 */
	48	u32 rpubkey_3; /* 0x30C */
	49	u32 rpubkey_4; /* 0x310 */
	50	u8 res4[0x04];
	51	u32 randkey_0; /* 0x318 */
	52	u32 randkey_1; /* 0x31C */
	53	u32 randkey_2; /* 0x320 */
	54	u32 randkey_3; /* 0x324 */
	55	u8 res5[0x124];
	56	u32 ctrl_omap_stat; /* 0x44C */
97a099ea	57	};
2c803210 DB	58	#else /* __ASSEMBLY__ */
	59	#define CONTROL_STATUS 0x2F0
	60	#endif /* __ASSEMBLY__ */
a3d1421d	61	#endif /* __KERNEL_STRICT_NAMES */
2c803210	62
a3d1421d	63	#ifndef __KERNEL_STRICT_NAMES
e6a6a704	64	#ifndef __ASSEMBLY__
97a099ea	65	struct ctrl_id {
a3d1421d DB	66	u8 res1[0x4];
	67	u32 idcode; /* 0x04 */
	68	u32 prod_id; /* 0x08 */
b2b9169f SS	69	u32 sku_id; /* 0x0c */
b2b9169f SS	70	u8 res2[0x08];
a3d1421d DB	71	u32 die_id_0; /* 0x18 */
	72	u32 die_id_1; /* 0x1C */
	73	u32 die_id_2; /* 0x20 */
	74	u32 die_id_3; /* 0x24 */
97a099ea	75	};
e6a6a704	76	#endif /* __ASSEMBLY__ */
a3d1421d	77	#endif /* __KERNEL_STRICT_NAMES */
e6a6a704	78
2c803210 DB	79	/* device type */
	80	#define DEVICE_MASK (0x7 << 8)
	81	#define SYSBOOT_MASK 0x1F
	82	#define TST_DEVICE 0x0
	83	#define EMU_DEVICE 0x1
	84	#define HS_DEVICE 0x2
	85	#define GP_DEVICE 0x3
	86
b2b9169f SS	87	/* device speed */
	88	#define SKUID_CLK_MASK 0xf
	89	#define SKUID_CLK_600MHZ 0x0
	90	#define SKUID_CLK_720MHZ 0x8
	91
2c803210 DB	92	#define GPMC_BASE (OMAP34XX_GPMC_BASE)
2c803210 DB	93	#define GPMC_CONFIG_CS0 0x60
cd3dcba1	94	#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
2c803210	95
a3d1421d	96	#ifndef __KERNEL_STRICT_NAMES
2c803210	97	#ifndef __ASSEMBLY__
187af954	98	struct gpmc_cs {
a3d1421d DB	99	u32 config1; /* 0x00 */
	100	u32 config2; /* 0x04 */
	101	u32 config3; /* 0x08 */
	102	u32 config4; /* 0x0C */
	103	u32 config5; /* 0x10 */
	104	u32 config6; /* 0x14 */
	105	u32 config7; /* 0x18 */
	106	u32 nand_cmd; /* 0x1C */
	107	u32 nand_adr; /* 0x20 */
	108	u32 nand_dat; /* 0x24 */
	109	u8 res[8]; /* blow up to 0x30 byte */
187af954 ML	110	};
187af954 ML	111
97a099ea	112	struct gpmc {
a3d1421d DB	113	u8 res1[0x10];
	114	u32 sysconfig; /* 0x10 */
	115	u8 res2[0x4];
	116	u32 irqstatus; /* 0x18 */
	117	u32 irqenable; /* 0x1C */
	118	u8 res3[0x20];
	119	u32 timeout_control; /* 0x40 */
	120	u8 res4[0xC];
	121	u32 config; /* 0x50 */
	122	u32 status; /* 0x54 */
8fa656aa	123	u8 res5[0x8]; /* 0x58 */
187af954	124	struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
8fa656aa	125	u8 res6[0x14]; /* 0x1E0 */
a3d1421d DB	126	u32 ecc_config; /* 0x1F4 */
	127	u32 ecc_control; /* 0x1F8 */
	128	u32 ecc_size_config; /* 0x1FC */
	129	u32 ecc1_result; /* 0x200 */
	130	u32 ecc2_result; /* 0x204 */
	131	u32 ecc3_result; /* 0x208 */
	132	u32 ecc4_result; /* 0x20C */
	133	u32 ecc5_result; /* 0x210 */
	134	u32 ecc6_result; /* 0x214 */
	135	u32 ecc7_result; /* 0x218 */
	136	u32 ecc8_result; /* 0x21C */
	137	u32 ecc9_result; /* 0x220 */
97a099ea	138	};
632e1d90 TR	139
	140	/* Used for board specific gpmc initialization */
	141	extern struct gpmc *gpmc_cfg;
	142
2c803210 DB	143	#else /* __ASSEMBLY__ */
	144	#define GPMC_CONFIG1 0x00
	145	#define GPMC_CONFIG2 0x04
	146	#define GPMC_CONFIG3 0x08
	147	#define GPMC_CONFIG4 0x0C
	148	#define GPMC_CONFIG5 0x10
	149	#define GPMC_CONFIG6 0x14
	150	#define GPMC_CONFIG7 0x18
	151	#endif /* __ASSEMBLY__ */
a3d1421d	152	#endif /* __KERNEL_STRICT_NAMES */
2c803210 DB	153
	154	/* GPMC Mapping */
	155	#define FLASH_BASE 0x10000000 /* NOR flash, */
	156	/* aligned to 256 Meg */
	157	#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
	158	/* aligned to 64 Meg */
	159	#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
	160	/* aligned to 256 Meg */
	161	#define DEBUG_BASE 0x08000000 /* debug board */
	162	#define NAND_BASE 0x30000000 /* NAND addr */
	163	/* (actual size small port) */
	164	#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
	165	#define ONENAND_MAP 0x20000000 /* OneNand addr */
	166	/* (actual size small port) */
	167	/* SMS */
a3d1421d	168	#ifndef __KERNEL_STRICT_NAMES
2c803210	169	#ifndef __ASSEMBLY__
97a099ea	170	struct sms {
a3d1421d DB	171	u8 res1[0x10];
	172	u32 sysconfig; /* 0x10 */
	173	u8 res2[0x34];
	174	u32 rg_att0; /* 0x48 */
	175	u8 res3[0x84];
	176	u32 class_arb0; /* 0xD0 */
97a099ea	177	};
2c803210	178	#endif /* __ASSEMBLY__ */
a3d1421d	179	#endif /* __KERNEL_STRICT_NAMES */
2c803210 DB	180
	181	#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
	182
	183	/* SDRC */
a3d1421d	184	#ifndef __KERNEL_STRICT_NAMES
2c803210	185	#ifndef __ASSEMBLY__
97a099ea	186	struct sdrc_cs {
a3d1421d DB	187	u32 mcfg; /* 0x80 \|\| 0xB0 */
	188	u32 mr; /* 0x84 \|\| 0xB4 */
	189	u8 res1[0x4];
	190	u32 emr2; /* 0x8C \|\| 0xBC */
	191	u8 res2[0x14];
	192	u32 rfr_ctrl; /* 0x84 \|\| 0xD4 */
	193	u32 manual; /* 0xA8 \|\| 0xD8 */
	194	u8 res3[0x4];
97a099ea	195	};
2c803210	196
97a099ea	197	struct sdrc_actim {
a3d1421d DB	198	u32 ctrla; /* 0x9C \|\| 0xC4 */
a3d1421d DB	199	u32 ctrlb; /* 0xA0 \|\| 0xC8 */
97a099ea	200	};
2c803210	201
97a099ea	202	struct sdrc {
a3d1421d DB	203	u8 res1[0x10];
	204	u32 sysconfig; /* 0x10 */
	205	u32 status; /* 0x14 */
	206	u8 res2[0x28];
	207	u32 cs_cfg; /* 0x40 */
	208	u32 sharing; /* 0x44 */
	209	u8 res3[0x18];
	210	u32 dlla_ctrl; /* 0x60 */
	211	u32 dlla_status; /* 0x64 */
	212	u32 dllb_ctrl; /* 0x68 */
	213	u32 dllb_status; /* 0x6C */
	214	u32 power; /* 0x70 */
	215	u8 res4[0xC];
	216	struct sdrc_cs cs[2]; /* 0x80 \|\| 0xB0 */
97a099ea	217	};
cae377b5	218
1a5038ca VH	219	/* EMIF4 */
1a5038ca VH	220	typedef struct emif4 {
40b95c89	221	unsigned int emif_mod_id_rev;
1a5038ca VH	222	unsigned int sdram_sts;
	223	unsigned int sdram_config;
	224	unsigned int res1;
	225	unsigned int sdram_refresh_ctrl;
	226	unsigned int sdram_refresh_ctrl_shdw;
	227	unsigned int sdram_time1;
	228	unsigned int sdram_time1_shdw;
	229	unsigned int sdram_time2;
	230	unsigned int sdram_time2_shdw;
	231	unsigned int sdram_time3;
	232	unsigned int sdram_time3_shdw;
	233	unsigned char res2[8];
	234	unsigned int sdram_pwr_mgmt;
	235	unsigned int sdram_pwr_mgmt_shdw;
	236	unsigned char res3[32];
	237	unsigned int sdram_iodft_tlgc;
	238	unsigned char res4[128];
	239	unsigned int ddr_phyctrl1;
	240	unsigned int ddr_phyctrl1_shdw;
	241	unsigned int ddr_phyctrl2;
	242	} emif4_t;
	243
2c803210	244	#endif /* __ASSEMBLY__ */
a3d1421d	245	#endif /* __KERNEL_STRICT_NAMES */
2c803210 DB	246
	247	#define DLLPHASE_90 (0x1 << 1)
	248	#define LOADDLL (0x1 << 2)
	249	#define ENADLL (0x1 << 3)
	250	#define DLL_DELAY_MASK 0xFF00
	251	#define DLL_NO_FILTER_MASK ((0x1 << 9) \| (0x1 << 8))
	252
	253	#define PAGEPOLICY_HIGH (0x1 << 0)
	254	#define SRFRONRESET (0x1 << 7)
d414aae5	255	#define PWDNEN (0x1 << 2)
2c803210 DB	256	#define WAKEUPPROC (0x1 << 26)
	257
	258	#define DDR_SDRAM (0x1 << 0)
	259	#define DEEPPD (0x1 << 3)
	260	#define B32NOT16 (0x1 << 4)
	261	#define BANKALLOCATION (0x2 << 6)
	262	#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
	263	#define ADDRMUXLEGACY (0x1 << 19)
	264	#define CASWIDTH_10BITS (0x5 << 20)
	265	#define RASWIDTH_13BITS (0x2 << 24)
	266	#define BURSTLENGTH4 (0x2 << 0)
	267	#define CASL3 (0x3 << 4)
	268	#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
	269	#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
	270	#define ARE_ARCV_1 (0x1 << 0)
	271	#define ARCV (0x4e2 << 8) /* Autorefresh count */
	272	#define OMAP34XX_SDRC_CS0 0x80000000
	273	#define OMAP34XX_SDRC_CS1 0xA0000000
	274	#define CMD_NOP 0x0
	275	#define CMD_PRECHARGE 0x1
	276	#define CMD_AUTOREFRESH 0x2
	277	#define CMD_ENTR_PWRDOWN 0x3
	278	#define CMD_EXIT_PWRDOWN 0x4
	279	#define CMD_ENTR_SRFRSH 0x5
	280	#define CMD_CKE_HIGH 0x6
	281	#define CMD_CKE_LOW 0x7
	282	#define SOFTRESET (0x1 << 1)
	283	#define SMART_IDLE (0x2 << 3)
	284	#define REF_ON_IDLE (0x1 << 6)
	285
7b646a6d SS	286	/* DMA */
	287	#ifndef __KERNEL_STRICT_NAMES
	288	#ifndef __ASSEMBLY__
	289	struct dma4_chan {
	290	u32 ccr;
	291	u32 clnk_ctrl;
	292	u32 cicr;
	293	u32 csr;
	294	u32 csdp;
	295	u32 cen;
	296	u32 cfn;
	297	u32 cssa;
	298	u32 cdsa;
	299	u32 csel;
	300	u32 csfl;
	301	u32 cdel;
	302	u32 cdfl;
	303	u32 csac;
	304	u32 cdac;
	305	u32 ccen;
	306	u32 ccfn;
	307	u32 color;
	308	};
	309
	310	struct dma4 {
	311	u32 revision;
	312	u8 res1[0x4];
	313	u32 irqstatus_l[0x4];
	314	u32 irqenable_l[0x4];
	315	u32 sysstatus;
	316	u32 ocp_sysconfig;
	317	u8 res2[0x34];
	318	u32 caps_0;
	319	u8 res3[0x4];
	320	u32 caps_2;
	321	u32 caps_3;
	322	u32 caps_4;
	323	u32 gcr;
	324	u8 res4[0x4];
	325	struct dma4_chan chan[32];
	326	};
	327
	328	#endif /__ASSEMBLY__ /
	329	#endif /* __KERNEL_STRICT_NAMES */
	330
2c803210 DB	331	/* timer regs offsets (32 bit regs) */
2c803210 DB	332
a3d1421d	333	#ifndef __KERNEL_STRICT_NAMES
2c803210	334	#ifndef __ASSEMBLY__
97a099ea	335	struct gptimer {
a3d1421d DB	336	u32 tidr; /* 0x00 r */
	337	u8 res[0xc];
	338	u32 tiocp_cfg; /* 0x10 rw */
	339	u32 tistat; /* 0x14 r */
	340	u32 tisr; /* 0x18 rw */
	341	u32 tier; /* 0x1c rw */
	342	u32 twer; /* 0x20 rw */
	343	u32 tclr; /* 0x24 rw */
	344	u32 tcrr; /* 0x28 rw */
	345	u32 tldr; /* 0x2c rw */
	346	u32 ttgr; /* 0x30 rw */
	347	u32 twpc; /* 0x34 r*/
	348	u32 tmar; /* 0x38 rw*/
	349	u32 tcar1; /* 0x3c r */
	350	u32 tcicr; /* 0x40 rw */
	351	u32 tcar2; /* 0x44 r */
97a099ea	352	};
2c803210	353	#endif /* __ASSEMBLY__ */
a3d1421d	354	#endif /* __KERNEL_STRICT_NAMES */
2c803210 DB	355
	356	/* enable sys_clk NO-prescale /1 */
	357	#define GPT_EN ((0x0 << 2) \| (0x1 << 1) \| (0x1 << 0))
	358
	359	/* Watchdog */
a3d1421d	360	#ifndef __KERNEL_STRICT_NAMES
2c803210	361	#ifndef __ASSEMBLY__
97a099ea	362	struct watchdog {
a3d1421d DB	363	u8 res1[0x34];
	364	u32 wwps; /* 0x34 r */
	365	u8 res2[0x10];
	366	u32 wspr; /* 0x48 rw */
97a099ea	367	};
2c803210	368	#endif /* __ASSEMBLY__ */
a3d1421d	369	#endif /* __KERNEL_STRICT_NAMES */
2c803210 DB	370
	371	#define WD_UNLOCK1 0xAAAA
	372	#define WD_UNLOCK2 0x5555
	373
	374	/* PRCM */
	375	#define PRCM_BASE 0x48004000
	376
a3d1421d	377	#ifndef __KERNEL_STRICT_NAMES
2c803210	378	#ifndef __ASSEMBLY__
97a099ea	379	struct prcm {
a3d1421d DB	380	u32 fclken_iva2; /* 0x00 */
	381	u32 clken_pll_iva2; /* 0x04 */
	382	u8 res1[0x1c];
	383	u32 idlest_pll_iva2; /* 0x24 */
	384	u8 res2[0x18];
	385	u32 clksel1_pll_iva2 ; /* 0x40 */
	386	u32 clksel2_pll_iva2; /* 0x44 */
	387	u8 res3[0x8bc];
	388	u32 clken_pll_mpu; /* 0x904 */
	389	u8 res4[0x1c];
	390	u32 idlest_pll_mpu; /* 0x924 */
	391	u8 res5[0x18];
	392	u32 clksel1_pll_mpu; /* 0x940 */
	393	u32 clksel2_pll_mpu; /* 0x944 */
	394	u8 res6[0xb8];
	395	u32 fclken1_core; /* 0xa00 */
7b89795f AH	396	u32 res_fclken2_core;
	397	u32 fclken3_core; /* 0xa08 */
	398	u8 res7[0x4];
a3d1421d DB	399	u32 iclken1_core; /* 0xa10 */
a3d1421d DB	400	u32 iclken2_core; /* 0xa14 */
7b89795f AH	401	u32 iclken3_core; /* 0xa18 */
7b89795f AH	402	u8 res8[0x24];
a3d1421d DB	403	u32 clksel_core; /* 0xa40 */
	404	u8 res9[0xbc];
	405	u32 fclken_gfx; /* 0xb00 */
	406	u8 res10[0xc];
	407	u32 iclken_gfx; /* 0xb10 */
	408	u8 res11[0x2c];
	409	u32 clksel_gfx; /* 0xb40 */
	410	u8 res12[0xbc];
	411	u32 fclken_wkup; /* 0xc00 */
	412	u8 res13[0xc];
	413	u32 iclken_wkup; /* 0xc10 */
	414	u8 res14[0xc];
	415	u32 idlest_wkup; /* 0xc20 */
	416	u8 res15[0x1c];
	417	u32 clksel_wkup; /* 0xc40 */
	418	u8 res16[0xbc];
	419	u32 clken_pll; /* 0xd00 */
7b89795f AH	420	u32 clken2_pll; /* 0xd04 */
7b89795f AH	421	u8 res17[0x18];
a3d1421d	422	u32 idlest_ckgen; /* 0xd20 */
7b89795f AH	423	u32 idlest2_ckgen; /* 0xd24 */
7b89795f AH	424	u8 res18[0x18];
a3d1421d DB	425	u32 clksel1_pll; /* 0xd40 */
	426	u32 clksel2_pll; /* 0xd44 */
	427	u32 clksel3_pll; /* 0xd48 */
7b89795f AH	428	u32 clksel4_pll; /* 0xd4c */
	429	u32 clksel5_pll; /* 0xd50 */
	430	u8 res19[0xac];
a3d1421d DB	431	u32 fclken_dss; /* 0xe00 */
	432	u8 res20[0xc];
	433	u32 iclken_dss; /* 0xe10 */
	434	u8 res21[0x2c];
	435	u32 clksel_dss; /* 0xe40 */
	436	u8 res22[0xbc];
	437	u32 fclken_cam; /* 0xf00 */
	438	u8 res23[0xc];
	439	u32 iclken_cam; /* 0xf10 */
	440	u8 res24[0x2c];
	441	u32 clksel_cam; /* 0xf40 */
	442	u8 res25[0xbc];
	443	u32 fclken_per; /* 0x1000 */
	444	u8 res26[0xc];
	445	u32 iclken_per; /* 0x1010 */
	446	u8 res27[0x2c];
	447	u32 clksel_per; /* 0x1040 */
	448	u8 res28[0xfc];
	449	u32 clksel1_emu; /* 0x1140 */
7b89795f AH	450	u8 res29[0x2bc];
	451	u32 fclken_usbhost; /* 0x1400 */
	452	u8 res30[0xc];
	453	u32 iclken_usbhost; /* 0x1410 */
97a099ea	454	};
2c803210 DB	455	#else /* __ASSEMBLY__ */
	456	#define CM_CLKSEL_CORE 0x48004a40
	457	#define CM_CLKSEL_GFX 0x48004b40
	458	#define CM_CLKSEL_WKUP 0x48004c40
	459	#define CM_CLKEN_PLL 0x48004d00
	460	#define CM_CLKSEL1_PLL 0x48004d40
	461	#define CM_CLKSEL1_EMU 0x48005140
	462	#endif /* __ASSEMBLY__ */
a3d1421d	463	#endif /* __KERNEL_STRICT_NAMES */
2c803210 DB	464
	465	#define PRM_BASE 0x48306000
	466
a3d1421d	467	#ifndef __KERNEL_STRICT_NAMES
2c803210	468	#ifndef __ASSEMBLY__
97a099ea	469	struct prm {
a3d1421d DB	470	u8 res1[0xd40];
	471	u32 clksel; /* 0xd40 */
	472	u8 res2[0x50c];
	473	u32 rstctrl; /* 0x1250 */
	474	u8 res3[0x1c];
	475	u32 clksrc_ctrl; /* 0x1270 */
97a099ea	476	};
2c803210	477	#endif /* __ASSEMBLY__ */
a3d1421d	478	#endif /* __KERNEL_STRICT_NAMES */
2c803210	479
d417d1db S	480	#define PRM_RSTCTRL 0x48307250
d417d1db S	481	#define PRM_RSTCTRL_RESET 0x04
70239507 LV	482	#define PRM_RSTST 0x48307258
70239507 LV	483	#define PRM_RSTST_WARM_RESET_MASK 0x7D2
2c803210 DB	484	#define SYSCLKDIV_1 (0x1 << 6)
	485	#define SYSCLKDIV_2 (0x1 << 7)
	486
	487	#define CLKSEL_GPT1 (0x1 << 0)
	488
	489	#define EN_GPT1 (0x1 << 0)
	490	#define EN_32KSYNC (0x1 << 2)
	491
	492	#define ST_WDT2 (0x1 << 5)
	493
	494	#define ST_MPU_CLK (0x1 << 0)
	495
	496	#define ST_CORE_CLK (0x1 << 0)
	497
	498	#define ST_PERIPH_CLK (0x1 << 1)
	499
	500	#define ST_IVA2_CLK (0x1 << 0)
	501
	502	#define RESETDONE (0x1 << 0)
	503
	504	#define TCLR_ST (0x1 << 0)
	505	#define TCLR_AR (0x1 << 1)
	506	#define TCLR_PRE (0x1 << 5)
	507
	508	/* SMX-APE */
	509	#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
	510	#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
	511	#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
	512	#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
	513
a3d1421d	514	#ifndef __KERNEL_STRICT_NAMES
2c803210	515	#ifndef __ASSEMBLY__
97a099ea	516	struct pm {
a3d1421d DB	517	u8 res1[0x48];
	518	u32 req_info_permission_0; /* 0x48 */
	519	u8 res2[0x4];
	520	u32 read_permission_0; /* 0x50 */
	521	u8 res3[0x4];
	522	u32 wirte_permission_0; /* 0x58 */
	523	u8 res4[0x4];
	524	u32 addr_match_1; /* 0x58 */
	525	u8 res5[0x4];
	526	u32 req_info_permission_1; /* 0x68 */
	527	u8 res6[0x14];
	528	u32 addr_match_2; /* 0x80 */
97a099ea	529	};
2c803210	530	#endif /__ASSEMBLY__ /
a3d1421d	531	#endif /* __KERNEL_STRICT_NAMES */
2c803210 DB	532
	533	/* Permission values for registers -Full fledged permissions to all */
	534	#define UNLOCK_1 0xFFFFFFFF
	535	#define UNLOCK_2 0x00000000
	536	#define UNLOCK_3 0x0000FFFF
	537
	538	#define NOT_EARLY 0
	539
	540	/* I2C base */
	541	#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
	542	#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
	543	#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
	544
9b167577 SS	545	/* MUSB base */
	546	#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
	547
25223a68 A	548	/* OMAP3 GPIO registers */
	549	#define OMAP_GPIO_REVISION 0x0000
	550	#define OMAP_GPIO_SYSCONFIG 0x0010
	551	#define OMAP_GPIO_SYSSTATUS 0x0014
	552	#define OMAP_GPIO_IRQSTATUS1 0x0018
	553	#define OMAP_GPIO_IRQSTATUS2 0x0028
	554	#define OMAP_GPIO_IRQENABLE2 0x002c
	555	#define OMAP_GPIO_IRQENABLE1 0x001c
	556	#define OMAP_GPIO_WAKE_EN 0x0020
	557	#define OMAP_GPIO_CTRL 0x0030
	558	#define OMAP_GPIO_OE 0x0034
	559	#define OMAP_GPIO_DATAIN 0x0038
	560	#define OMAP_GPIO_DATAOUT 0x003c
	561	#define OMAP_GPIO_LEVELDETECT0 0x0040
	562	#define OMAP_GPIO_LEVELDETECT1 0x0044
	563	#define OMAP_GPIO_RISINGDETECT 0x0048
	564	#define OMAP_GPIO_FALLINGDETECT 0x004c
	565	#define OMAP_GPIO_DEBOUNCE_EN 0x0050
	566	#define OMAP_GPIO_DEBOUNCE_VAL 0x0054
	567	#define OMAP_GPIO_CLEARIRQENABLE1 0x0060
	568	#define OMAP_GPIO_SETIRQENABLE1 0x0064
	569	#define OMAP_GPIO_CLEARWKUENA 0x0080
	570	#define OMAP_GPIO_SETWKUENA 0x0084
	571	#define OMAP_GPIO_CLEARDATAOUT 0x0090
	572	#define OMAP_GPIO_SETDATAOUT 0x0094
	573
2c803210	574	#endif /* _CPU_H */