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2c803210 DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _CPU_H | |
26 | #define _CPU_H | |
27 | ||
a3d1421d DB |
28 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
29 | #include <asm/types.h> | |
30 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ | |
31 | ||
2c803210 DB |
32 | /* Register offsets of common modules */ |
33 | /* Control */ | |
a3d1421d | 34 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 35 | #ifndef __ASSEMBLY__ |
97a099ea | 36 | struct ctrl { |
a3d1421d DB |
37 | u8 res1[0xC0]; |
38 | u16 gpmc_nadv_ale; /* 0xC0 */ | |
39 | u16 gpmc_noe; /* 0xC2 */ | |
40 | u16 gpmc_nwe; /* 0xC4 */ | |
41 | u8 res2[0x22A]; | |
42 | u32 status; /* 0x2F0 */ | |
43 | u32 gpstatus; /* 0x2F4 */ | |
44 | u8 res3[0x08]; | |
45 | u32 rpubkey_0; /* 0x300 */ | |
46 | u32 rpubkey_1; /* 0x304 */ | |
47 | u32 rpubkey_2; /* 0x308 */ | |
48 | u32 rpubkey_3; /* 0x30C */ | |
49 | u32 rpubkey_4; /* 0x310 */ | |
50 | u8 res4[0x04]; | |
51 | u32 randkey_0; /* 0x318 */ | |
52 | u32 randkey_1; /* 0x31C */ | |
53 | u32 randkey_2; /* 0x320 */ | |
54 | u32 randkey_3; /* 0x324 */ | |
55 | u8 res5[0x124]; | |
56 | u32 ctrl_omap_stat; /* 0x44C */ | |
97a099ea | 57 | }; |
2c803210 DB |
58 | #else /* __ASSEMBLY__ */ |
59 | #define CONTROL_STATUS 0x2F0 | |
60 | #endif /* __ASSEMBLY__ */ | |
a3d1421d | 61 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 | 62 | |
6530a8bf DB |
63 | /* cpu type */ |
64 | #define OMAP3503 0x5c00 | |
65 | #define OMAP3515 0x1c00 | |
66 | #define OMAP3525 0x4c00 | |
67 | #define OMAP3530 0x0c00 | |
68 | ||
a3d1421d | 69 | #ifndef __KERNEL_STRICT_NAMES |
e6a6a704 | 70 | #ifndef __ASSEMBLY__ |
97a099ea | 71 | struct ctrl_id { |
a3d1421d DB |
72 | u8 res1[0x4]; |
73 | u32 idcode; /* 0x04 */ | |
74 | u32 prod_id; /* 0x08 */ | |
75 | u8 res2[0x0C]; | |
76 | u32 die_id_0; /* 0x18 */ | |
77 | u32 die_id_1; /* 0x1C */ | |
78 | u32 die_id_2; /* 0x20 */ | |
79 | u32 die_id_3; /* 0x24 */ | |
97a099ea | 80 | }; |
e6a6a704 | 81 | #endif /* __ASSEMBLY__ */ |
a3d1421d | 82 | #endif /* __KERNEL_STRICT_NAMES */ |
e6a6a704 | 83 | |
2c803210 DB |
84 | /* device type */ |
85 | #define DEVICE_MASK (0x7 << 8) | |
86 | #define SYSBOOT_MASK 0x1F | |
87 | #define TST_DEVICE 0x0 | |
88 | #define EMU_DEVICE 0x1 | |
89 | #define HS_DEVICE 0x2 | |
90 | #define GP_DEVICE 0x3 | |
91 | ||
2c803210 DB |
92 | #define GPMC_BASE (OMAP34XX_GPMC_BASE) |
93 | #define GPMC_CONFIG_CS0 0x60 | |
cd3dcba1 | 94 | #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) |
2c803210 | 95 | |
a3d1421d | 96 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 97 | #ifndef __ASSEMBLY__ |
187af954 | 98 | struct gpmc_cs { |
a3d1421d DB |
99 | u32 config1; /* 0x00 */ |
100 | u32 config2; /* 0x04 */ | |
101 | u32 config3; /* 0x08 */ | |
102 | u32 config4; /* 0x0C */ | |
103 | u32 config5; /* 0x10 */ | |
104 | u32 config6; /* 0x14 */ | |
105 | u32 config7; /* 0x18 */ | |
106 | u32 nand_cmd; /* 0x1C */ | |
107 | u32 nand_adr; /* 0x20 */ | |
108 | u32 nand_dat; /* 0x24 */ | |
109 | u8 res[8]; /* blow up to 0x30 byte */ | |
187af954 ML |
110 | }; |
111 | ||
97a099ea | 112 | struct gpmc { |
a3d1421d DB |
113 | u8 res1[0x10]; |
114 | u32 sysconfig; /* 0x10 */ | |
115 | u8 res2[0x4]; | |
116 | u32 irqstatus; /* 0x18 */ | |
117 | u32 irqenable; /* 0x1C */ | |
118 | u8 res3[0x20]; | |
119 | u32 timeout_control; /* 0x40 */ | |
120 | u8 res4[0xC]; | |
121 | u32 config; /* 0x50 */ | |
122 | u32 status; /* 0x54 */ | |
8fa656aa | 123 | u8 res5[0x8]; /* 0x58 */ |
187af954 | 124 | struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ |
8fa656aa | 125 | u8 res6[0x14]; /* 0x1E0 */ |
a3d1421d DB |
126 | u32 ecc_config; /* 0x1F4 */ |
127 | u32 ecc_control; /* 0x1F8 */ | |
128 | u32 ecc_size_config; /* 0x1FC */ | |
129 | u32 ecc1_result; /* 0x200 */ | |
130 | u32 ecc2_result; /* 0x204 */ | |
131 | u32 ecc3_result; /* 0x208 */ | |
132 | u32 ecc4_result; /* 0x20C */ | |
133 | u32 ecc5_result; /* 0x210 */ | |
134 | u32 ecc6_result; /* 0x214 */ | |
135 | u32 ecc7_result; /* 0x218 */ | |
136 | u32 ecc8_result; /* 0x21C */ | |
137 | u32 ecc9_result; /* 0x220 */ | |
97a099ea | 138 | }; |
632e1d90 TR |
139 | |
140 | /* Used for board specific gpmc initialization */ | |
141 | extern struct gpmc *gpmc_cfg; | |
142 | ||
2c803210 DB |
143 | #else /* __ASSEMBLY__ */ |
144 | #define GPMC_CONFIG1 0x00 | |
145 | #define GPMC_CONFIG2 0x04 | |
146 | #define GPMC_CONFIG3 0x08 | |
147 | #define GPMC_CONFIG4 0x0C | |
148 | #define GPMC_CONFIG5 0x10 | |
149 | #define GPMC_CONFIG6 0x14 | |
150 | #define GPMC_CONFIG7 0x18 | |
151 | #endif /* __ASSEMBLY__ */ | |
a3d1421d | 152 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
153 | |
154 | /* GPMC Mapping */ | |
155 | #define FLASH_BASE 0x10000000 /* NOR flash, */ | |
156 | /* aligned to 256 Meg */ | |
157 | #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ | |
158 | /* aligned to 64 Meg */ | |
159 | #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ | |
160 | /* aligned to 256 Meg */ | |
161 | #define DEBUG_BASE 0x08000000 /* debug board */ | |
162 | #define NAND_BASE 0x30000000 /* NAND addr */ | |
163 | /* (actual size small port) */ | |
164 | #define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ | |
165 | #define ONENAND_MAP 0x20000000 /* OneNand addr */ | |
166 | /* (actual size small port) */ | |
167 | /* SMS */ | |
a3d1421d | 168 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 169 | #ifndef __ASSEMBLY__ |
97a099ea | 170 | struct sms { |
a3d1421d DB |
171 | u8 res1[0x10]; |
172 | u32 sysconfig; /* 0x10 */ | |
173 | u8 res2[0x34]; | |
174 | u32 rg_att0; /* 0x48 */ | |
175 | u8 res3[0x84]; | |
176 | u32 class_arb0; /* 0xD0 */ | |
97a099ea | 177 | }; |
2c803210 | 178 | #endif /* __ASSEMBLY__ */ |
a3d1421d | 179 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
180 | |
181 | #define BURSTCOMPLETE_GROUP7 (0x1 << 31) | |
182 | ||
183 | /* SDRC */ | |
a3d1421d | 184 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 185 | #ifndef __ASSEMBLY__ |
97a099ea | 186 | struct sdrc_cs { |
a3d1421d DB |
187 | u32 mcfg; /* 0x80 || 0xB0 */ |
188 | u32 mr; /* 0x84 || 0xB4 */ | |
189 | u8 res1[0x4]; | |
190 | u32 emr2; /* 0x8C || 0xBC */ | |
191 | u8 res2[0x14]; | |
192 | u32 rfr_ctrl; /* 0x84 || 0xD4 */ | |
193 | u32 manual; /* 0xA8 || 0xD8 */ | |
194 | u8 res3[0x4]; | |
97a099ea | 195 | }; |
2c803210 | 196 | |
97a099ea | 197 | struct sdrc_actim { |
a3d1421d DB |
198 | u32 ctrla; /* 0x9C || 0xC4 */ |
199 | u32 ctrlb; /* 0xA0 || 0xC8 */ | |
97a099ea | 200 | }; |
2c803210 | 201 | |
97a099ea | 202 | struct sdrc { |
a3d1421d DB |
203 | u8 res1[0x10]; |
204 | u32 sysconfig; /* 0x10 */ | |
205 | u32 status; /* 0x14 */ | |
206 | u8 res2[0x28]; | |
207 | u32 cs_cfg; /* 0x40 */ | |
208 | u32 sharing; /* 0x44 */ | |
209 | u8 res3[0x18]; | |
210 | u32 dlla_ctrl; /* 0x60 */ | |
211 | u32 dlla_status; /* 0x64 */ | |
212 | u32 dllb_ctrl; /* 0x68 */ | |
213 | u32 dllb_status; /* 0x6C */ | |
214 | u32 power; /* 0x70 */ | |
215 | u8 res4[0xC]; | |
216 | struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ | |
97a099ea | 217 | }; |
2c803210 | 218 | #endif /* __ASSEMBLY__ */ |
a3d1421d | 219 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
220 | |
221 | #define DLLPHASE_90 (0x1 << 1) | |
222 | #define LOADDLL (0x1 << 2) | |
223 | #define ENADLL (0x1 << 3) | |
224 | #define DLL_DELAY_MASK 0xFF00 | |
225 | #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) | |
226 | ||
227 | #define PAGEPOLICY_HIGH (0x1 << 0) | |
228 | #define SRFRONRESET (0x1 << 7) | |
d414aae5 | 229 | #define PWDNEN (0x1 << 2) |
2c803210 DB |
230 | #define WAKEUPPROC (0x1 << 26) |
231 | ||
232 | #define DDR_SDRAM (0x1 << 0) | |
233 | #define DEEPPD (0x1 << 3) | |
234 | #define B32NOT16 (0x1 << 4) | |
235 | #define BANKALLOCATION (0x2 << 6) | |
236 | #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ | |
237 | #define ADDRMUXLEGACY (0x1 << 19) | |
238 | #define CASWIDTH_10BITS (0x5 << 20) | |
239 | #define RASWIDTH_13BITS (0x2 << 24) | |
240 | #define BURSTLENGTH4 (0x2 << 0) | |
241 | #define CASL3 (0x3 << 4) | |
242 | #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) | |
243 | #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) | |
244 | #define ARE_ARCV_1 (0x1 << 0) | |
245 | #define ARCV (0x4e2 << 8) /* Autorefresh count */ | |
246 | #define OMAP34XX_SDRC_CS0 0x80000000 | |
247 | #define OMAP34XX_SDRC_CS1 0xA0000000 | |
248 | #define CMD_NOP 0x0 | |
249 | #define CMD_PRECHARGE 0x1 | |
250 | #define CMD_AUTOREFRESH 0x2 | |
251 | #define CMD_ENTR_PWRDOWN 0x3 | |
252 | #define CMD_EXIT_PWRDOWN 0x4 | |
253 | #define CMD_ENTR_SRFRSH 0x5 | |
254 | #define CMD_CKE_HIGH 0x6 | |
255 | #define CMD_CKE_LOW 0x7 | |
256 | #define SOFTRESET (0x1 << 1) | |
257 | #define SMART_IDLE (0x2 << 3) | |
258 | #define REF_ON_IDLE (0x1 << 6) | |
259 | ||
260 | /* timer regs offsets (32 bit regs) */ | |
261 | ||
a3d1421d | 262 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 263 | #ifndef __ASSEMBLY__ |
97a099ea | 264 | struct gptimer { |
a3d1421d DB |
265 | u32 tidr; /* 0x00 r */ |
266 | u8 res[0xc]; | |
267 | u32 tiocp_cfg; /* 0x10 rw */ | |
268 | u32 tistat; /* 0x14 r */ | |
269 | u32 tisr; /* 0x18 rw */ | |
270 | u32 tier; /* 0x1c rw */ | |
271 | u32 twer; /* 0x20 rw */ | |
272 | u32 tclr; /* 0x24 rw */ | |
273 | u32 tcrr; /* 0x28 rw */ | |
274 | u32 tldr; /* 0x2c rw */ | |
275 | u32 ttgr; /* 0x30 rw */ | |
276 | u32 twpc; /* 0x34 r*/ | |
277 | u32 tmar; /* 0x38 rw*/ | |
278 | u32 tcar1; /* 0x3c r */ | |
279 | u32 tcicr; /* 0x40 rw */ | |
280 | u32 tcar2; /* 0x44 r */ | |
97a099ea | 281 | }; |
2c803210 | 282 | #endif /* __ASSEMBLY__ */ |
a3d1421d | 283 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
284 | |
285 | /* enable sys_clk NO-prescale /1 */ | |
286 | #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) | |
287 | ||
288 | /* Watchdog */ | |
a3d1421d | 289 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 290 | #ifndef __ASSEMBLY__ |
97a099ea | 291 | struct watchdog { |
a3d1421d DB |
292 | u8 res1[0x34]; |
293 | u32 wwps; /* 0x34 r */ | |
294 | u8 res2[0x10]; | |
295 | u32 wspr; /* 0x48 rw */ | |
97a099ea | 296 | }; |
2c803210 | 297 | #endif /* __ASSEMBLY__ */ |
a3d1421d | 298 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
299 | |
300 | #define WD_UNLOCK1 0xAAAA | |
301 | #define WD_UNLOCK2 0x5555 | |
302 | ||
303 | /* PRCM */ | |
304 | #define PRCM_BASE 0x48004000 | |
305 | ||
a3d1421d | 306 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 307 | #ifndef __ASSEMBLY__ |
97a099ea | 308 | struct prcm { |
a3d1421d DB |
309 | u32 fclken_iva2; /* 0x00 */ |
310 | u32 clken_pll_iva2; /* 0x04 */ | |
311 | u8 res1[0x1c]; | |
312 | u32 idlest_pll_iva2; /* 0x24 */ | |
313 | u8 res2[0x18]; | |
314 | u32 clksel1_pll_iva2 ; /* 0x40 */ | |
315 | u32 clksel2_pll_iva2; /* 0x44 */ | |
316 | u8 res3[0x8bc]; | |
317 | u32 clken_pll_mpu; /* 0x904 */ | |
318 | u8 res4[0x1c]; | |
319 | u32 idlest_pll_mpu; /* 0x924 */ | |
320 | u8 res5[0x18]; | |
321 | u32 clksel1_pll_mpu; /* 0x940 */ | |
322 | u32 clksel2_pll_mpu; /* 0x944 */ | |
323 | u8 res6[0xb8]; | |
324 | u32 fclken1_core; /* 0xa00 */ | |
325 | u8 res7[0xc]; | |
326 | u32 iclken1_core; /* 0xa10 */ | |
327 | u32 iclken2_core; /* 0xa14 */ | |
328 | u8 res8[0x28]; | |
329 | u32 clksel_core; /* 0xa40 */ | |
330 | u8 res9[0xbc]; | |
331 | u32 fclken_gfx; /* 0xb00 */ | |
332 | u8 res10[0xc]; | |
333 | u32 iclken_gfx; /* 0xb10 */ | |
334 | u8 res11[0x2c]; | |
335 | u32 clksel_gfx; /* 0xb40 */ | |
336 | u8 res12[0xbc]; | |
337 | u32 fclken_wkup; /* 0xc00 */ | |
338 | u8 res13[0xc]; | |
339 | u32 iclken_wkup; /* 0xc10 */ | |
340 | u8 res14[0xc]; | |
341 | u32 idlest_wkup; /* 0xc20 */ | |
342 | u8 res15[0x1c]; | |
343 | u32 clksel_wkup; /* 0xc40 */ | |
344 | u8 res16[0xbc]; | |
345 | u32 clken_pll; /* 0xd00 */ | |
346 | u8 res17[0x1c]; | |
347 | u32 idlest_ckgen; /* 0xd20 */ | |
348 | u8 res18[0x1c]; | |
349 | u32 clksel1_pll; /* 0xd40 */ | |
350 | u32 clksel2_pll; /* 0xd44 */ | |
351 | u32 clksel3_pll; /* 0xd48 */ | |
352 | u8 res19[0xb4]; | |
353 | u32 fclken_dss; /* 0xe00 */ | |
354 | u8 res20[0xc]; | |
355 | u32 iclken_dss; /* 0xe10 */ | |
356 | u8 res21[0x2c]; | |
357 | u32 clksel_dss; /* 0xe40 */ | |
358 | u8 res22[0xbc]; | |
359 | u32 fclken_cam; /* 0xf00 */ | |
360 | u8 res23[0xc]; | |
361 | u32 iclken_cam; /* 0xf10 */ | |
362 | u8 res24[0x2c]; | |
363 | u32 clksel_cam; /* 0xf40 */ | |
364 | u8 res25[0xbc]; | |
365 | u32 fclken_per; /* 0x1000 */ | |
366 | u8 res26[0xc]; | |
367 | u32 iclken_per; /* 0x1010 */ | |
368 | u8 res27[0x2c]; | |
369 | u32 clksel_per; /* 0x1040 */ | |
370 | u8 res28[0xfc]; | |
371 | u32 clksel1_emu; /* 0x1140 */ | |
97a099ea | 372 | }; |
2c803210 DB |
373 | #else /* __ASSEMBLY__ */ |
374 | #define CM_CLKSEL_CORE 0x48004a40 | |
375 | #define CM_CLKSEL_GFX 0x48004b40 | |
376 | #define CM_CLKSEL_WKUP 0x48004c40 | |
377 | #define CM_CLKEN_PLL 0x48004d00 | |
378 | #define CM_CLKSEL1_PLL 0x48004d40 | |
379 | #define CM_CLKSEL1_EMU 0x48005140 | |
380 | #endif /* __ASSEMBLY__ */ | |
a3d1421d | 381 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
382 | |
383 | #define PRM_BASE 0x48306000 | |
384 | ||
a3d1421d | 385 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 386 | #ifndef __ASSEMBLY__ |
97a099ea | 387 | struct prm { |
a3d1421d DB |
388 | u8 res1[0xd40]; |
389 | u32 clksel; /* 0xd40 */ | |
390 | u8 res2[0x50c]; | |
391 | u32 rstctrl; /* 0x1250 */ | |
392 | u8 res3[0x1c]; | |
393 | u32 clksrc_ctrl; /* 0x1270 */ | |
97a099ea | 394 | }; |
2c803210 DB |
395 | #else /* __ASSEMBLY__ */ |
396 | #define PRM_RSTCTRL 0x48307250 | |
397 | #endif /* __ASSEMBLY__ */ | |
a3d1421d | 398 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
399 | |
400 | #define SYSCLKDIV_1 (0x1 << 6) | |
401 | #define SYSCLKDIV_2 (0x1 << 7) | |
402 | ||
403 | #define CLKSEL_GPT1 (0x1 << 0) | |
404 | ||
405 | #define EN_GPT1 (0x1 << 0) | |
406 | #define EN_32KSYNC (0x1 << 2) | |
407 | ||
408 | #define ST_WDT2 (0x1 << 5) | |
409 | ||
410 | #define ST_MPU_CLK (0x1 << 0) | |
411 | ||
412 | #define ST_CORE_CLK (0x1 << 0) | |
413 | ||
414 | #define ST_PERIPH_CLK (0x1 << 1) | |
415 | ||
416 | #define ST_IVA2_CLK (0x1 << 0) | |
417 | ||
418 | #define RESETDONE (0x1 << 0) | |
419 | ||
420 | #define TCLR_ST (0x1 << 0) | |
421 | #define TCLR_AR (0x1 << 1) | |
422 | #define TCLR_PRE (0x1 << 5) | |
423 | ||
424 | /* SMX-APE */ | |
425 | #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) | |
426 | #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) | |
427 | #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) | |
428 | #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) | |
429 | ||
a3d1421d | 430 | #ifndef __KERNEL_STRICT_NAMES |
2c803210 | 431 | #ifndef __ASSEMBLY__ |
97a099ea | 432 | struct pm { |
a3d1421d DB |
433 | u8 res1[0x48]; |
434 | u32 req_info_permission_0; /* 0x48 */ | |
435 | u8 res2[0x4]; | |
436 | u32 read_permission_0; /* 0x50 */ | |
437 | u8 res3[0x4]; | |
438 | u32 wirte_permission_0; /* 0x58 */ | |
439 | u8 res4[0x4]; | |
440 | u32 addr_match_1; /* 0x58 */ | |
441 | u8 res5[0x4]; | |
442 | u32 req_info_permission_1; /* 0x68 */ | |
443 | u8 res6[0x14]; | |
444 | u32 addr_match_2; /* 0x80 */ | |
97a099ea | 445 | }; |
2c803210 | 446 | #endif /*__ASSEMBLY__ */ |
a3d1421d | 447 | #endif /* __KERNEL_STRICT_NAMES */ |
2c803210 DB |
448 | |
449 | /* Permission values for registers -Full fledged permissions to all */ | |
450 | #define UNLOCK_1 0xFFFFFFFF | |
451 | #define UNLOCK_2 0x00000000 | |
452 | #define UNLOCK_3 0x0000FFFF | |
453 | ||
454 | #define NOT_EARLY 0 | |
455 | ||
456 | /* I2C base */ | |
457 | #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) | |
458 | #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) | |
459 | #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) | |
460 | ||
461 | #endif /* _CPU_H */ |