projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ad853c3 SS |
1 | /* |
| 2 | * (C) Copyright 2004-2009 | |
| 3 | * Texas Instruments Incorporated | |
| 4 | * Richard Woodruff <r-woodruff2@ti.com> | |
| 5 | * Aneesh V <aneesh@ti.com> | |
| 6 | * Balaji Krishnamoorthy <balajitk@ti.com> | |
| 7 | * | |
| 1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 2ad853c3 SS |
9 | */ |
| 10 | #ifndef _MUX_OMAP4_H_ | |
| 11 | #define _MUX_OMAP4_H_ | |
| 12 | ||
| 13 | #include <asm/types.h> | |
| 14 | ||
| 15 | struct pad_conf_entry { | |
| 16 | ||
| 17 | u16 offset; | |
| 18 | ||
| 19 | u16 val; | |
| 20 | ||
| 03f69dc6 | 21 | }; |
| 2ad853c3 SS |
22 | |
| 23 | #ifdef CONFIG_OFF_PADCONF | |
| 24 | #define OFF_PD (1 << 12) | |
| 25 | #define OFF_PU (3 << 12) | |
| 26 | #define OFF_OUT_PTD (0 << 10) | |
| 27 | #define OFF_OUT_PTU (2 << 10) | |
| 28 | #define OFF_IN (1 << 10) | |
| 29 | #define OFF_OUT (0 << 10) | |
| 30 | #define OFF_EN (1 << 9) | |
| 31 | #else | |
| 32 | #define OFF_PD (0 << 12) | |
| 33 | #define OFF_PU (0 << 12) | |
| 34 | #define OFF_OUT_PTD (0 << 10) | |
| 35 | #define OFF_OUT_PTU (0 << 10) | |
| 36 | #define OFF_IN (0 << 10) | |
| 37 | #define OFF_OUT (0 << 10) | |
| 38 | #define OFF_EN (0 << 9) | |
| 39 | #endif | |
| 40 | ||
| 41 | #define IEN (1 << 8) | |
| 42 | #define IDIS (0 << 8) | |
| 43 | #define PTU (3 << 3) | |
| 44 | #define PTD (1 << 3) | |
| 45 | #define EN (1 << 3) | |
| 46 | #define DIS (0 << 3) | |
| 47 | ||
| 48 | #define M0 0 | |
| 49 | #define M1 1 | |
| 50 | #define M2 2 | |
| 51 | #define M3 3 | |
| 52 | #define M4 4 | |
| 53 | #define M5 5 | |
| 54 | #define M6 6 | |
| 55 | #define M7 7 | |
| 56 | ||
| 57 | #define SAFE_MODE M7 | |
| 58 | ||
| 59 | #ifdef CONFIG_OFF_PADCONF | |
| 60 | #define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) | |
| 61 | #define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) | |
| 62 | #define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) | |
| 63 | #define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) | |
| 64 | #else | |
| 65 | #define OFF_IN_PD 0 | |
| 66 | #define OFF_IN_PU 0 | |
| 67 | #define OFF_OUT_PD 0 | |
| 68 | #define OFF_OUT_PU 0 | |
| 69 | #endif | |
| 70 | ||
| 71 | #define CORE_REVISION 0x0000 | |
| 72 | #define CORE_HWINFO 0x0004 | |
| 73 | #define CORE_SYSCONFIG 0x0010 | |
| 74 | #define GPMC_AD0 0x0040 | |
| 75 | #define GPMC_AD1 0x0042 | |
| 76 | #define GPMC_AD2 0x0044 | |
| 77 | #define GPMC_AD3 0x0046 | |
| 78 | #define GPMC_AD4 0x0048 | |
| 79 | #define GPMC_AD5 0x004A | |
| 80 | #define GPMC_AD6 0x004C | |
| 81 | #define GPMC_AD7 0x004E | |
| 82 | #define GPMC_AD8 0x0050 | |
| 83 | #define GPMC_AD9 0x0052 | |
| 84 | #define GPMC_AD10 0x0054 | |
| 85 | #define GPMC_AD11 0x0056 | |
| 86 | #define GPMC_AD12 0x0058 | |
| 87 | #define GPMC_AD13 0x005A | |
| 88 | #define GPMC_AD14 0x005C | |
| 89 | #define GPMC_AD15 0x005E | |
| 90 | #define GPMC_A16 0x0060 | |
| 91 | #define GPMC_A17 0x0062 | |
| 92 | #define GPMC_A18 0x0064 | |
| 93 | #define GPMC_A19 0x0066 | |
| 94 | #define GPMC_A20 0x0068 | |
| 95 | #define GPMC_A21 0x006A | |
| 96 | #define GPMC_A22 0x006C | |
| 97 | #define GPMC_A23 0x006E | |
| 98 | #define GPMC_A24 0x0070 | |
| 99 | #define GPMC_A25 0x0072 | |
| 100 | #define GPMC_NCS0 0x0074 | |
| 101 | #define GPMC_NCS1 0x0076 | |
| 102 | #define GPMC_NCS2 0x0078 | |
| 103 | #define GPMC_NCS3 0x007A | |
| 104 | #define GPMC_NWP 0x007C | |
| 105 | #define GPMC_CLK 0x007E | |
| 106 | #define GPMC_NADV_ALE 0x0080 | |
| 107 | #define GPMC_NOE 0x0082 | |
| 108 | #define GPMC_NWE 0x0084 | |
| 109 | #define GPMC_NBE0_CLE 0x0086 | |
| 110 | #define GPMC_NBE1 0x0088 | |
| 111 | #define GPMC_WAIT0 0x008A | |
| 112 | #define GPMC_WAIT1 0x008C | |
| 113 | #define C2C_DATA11 0x008E | |
| 114 | #define C2C_DATA12 0x0090 | |
| 115 | #define C2C_DATA13 0x0092 | |
| 116 | #define C2C_DATA14 0x0094 | |
| 117 | #define C2C_DATA15 0x0096 | |
| 118 | #define HDMI_HPD 0x0098 | |
| 119 | #define HDMI_CEC 0x009A | |
| 120 | #define HDMI_DDC_SCL 0x009C | |
| 121 | #define HDMI_DDC_SDA 0x009E | |
| 122 | #define CSI21_DX0 0x00A0 | |
| 123 | #define CSI21_DY0 0x00A2 | |
| 124 | #define CSI21_DX1 0x00A4 | |
| 125 | #define CSI21_DY1 0x00A6 | |
| 126 | #define CSI21_DX2 0x00A8 | |
| 127 | #define CSI21_DY2 0x00AA | |
| 128 | #define CSI21_DX3 0x00AC | |
| 129 | #define CSI21_DY3 0x00AE | |
| 130 | #define CSI21_DX4 0x00B0 | |
| 131 | #define CSI21_DY4 0x00B2 | |
| 132 | #define CSI22_DX0 0x00B4 | |
| 133 | #define CSI22_DY0 0x00B6 | |
| 134 | #define CSI22_DX1 0x00B8 | |
| 135 | #define CSI22_DY1 0x00BA | |
| 136 | #define CAM_SHUTTER 0x00BC | |
| 137 | #define CAM_STROBE 0x00BE | |
| 138 | #define CAM_GLOBALRESET 0x00C0 | |
| 139 | #define USBB1_ULPITLL_CLK 0x00C2 | |
| 140 | #define USBB1_ULPITLL_STP 0x00C4 | |
| 141 | #define USBB1_ULPITLL_DIR 0x00C6 | |
| 142 | #define USBB1_ULPITLL_NXT 0x00C8 | |
| 143 | #define USBB1_ULPITLL_DAT0 0x00CA | |
| 144 | #define USBB1_ULPITLL_DAT1 0x00CC | |
| 145 | #define USBB1_ULPITLL_DAT2 0x00CE | |
| 146 | #define USBB1_ULPITLL_DAT3 0x00D0 | |
| 147 | #define USBB1_ULPITLL_DAT4 0x00D2 | |
| 148 | #define USBB1_ULPITLL_DAT5 0x00D4 | |
| 149 | #define USBB1_ULPITLL_DAT6 0x00D6 | |
| 150 | #define USBB1_ULPITLL_DAT7 0x00D8 | |
| 151 | #define USBB1_HSIC_DATA 0x00DA | |
| 152 | #define USBB1_HSIC_STROBE 0x00DC | |
| 153 | #define USBC1_ICUSB_DP 0x00DE | |
| 154 | #define USBC1_ICUSB_DM 0x00E0 | |
| 155 | #define SDMMC1_CLK 0x00E2 | |
| 156 | #define SDMMC1_CMD 0x00E4 | |
| 157 | #define SDMMC1_DAT0 0x00E6 | |
| 158 | #define SDMMC1_DAT1 0x00E8 | |
| 159 | #define SDMMC1_DAT2 0x00EA | |
| 160 | #define SDMMC1_DAT3 0x00EC | |
| 161 | #define SDMMC1_DAT4 0x00EE | |
| 162 | #define SDMMC1_DAT5 0x00F0 | |
| 163 | #define SDMMC1_DAT6 0x00F2 | |
| 164 | #define SDMMC1_DAT7 0x00F4 | |
| 165 | #define ABE_MCBSP2_CLKX 0x00F6 | |
| 166 | #define ABE_MCBSP2_DR 0x00F8 | |
| 167 | #define ABE_MCBSP2_DX 0x00FA | |
| 168 | #define ABE_MCBSP2_FSX 0x00FC | |
| 169 | #define ABE_MCBSP1_CLKX 0x00FE | |
| 170 | #define ABE_MCBSP1_DR 0x0100 | |
| 171 | #define ABE_MCBSP1_DX 0x0102 | |
| 172 | #define ABE_MCBSP1_FSX 0x0104 | |
| 173 | #define ABE_PDM_UL_DATA 0x0106 | |
| 174 | #define ABE_PDM_DL_DATA 0x0108 | |
| 175 | #define ABE_PDM_FRAME 0x010A | |
| 176 | #define ABE_PDM_LB_CLK 0x010C | |
| 177 | #define ABE_CLKS 0x010E | |
| 178 | #define ABE_DMIC_CLK1 0x0110 | |
| 179 | #define ABE_DMIC_DIN1 0x0112 | |
| 180 | #define ABE_DMIC_DIN2 0x0114 | |
| 181 | #define ABE_DMIC_DIN3 0x0116 | |
| 182 | #define UART2_CTS 0x0118 | |
| 183 | #define UART2_RTS 0x011A | |
| 184 | #define UART2_RX 0x011C | |
| 185 | #define UART2_TX 0x011E | |
| 186 | #define HDQ_SIO 0x0120 | |
| 187 | #define I2C1_SCL 0x0122 | |
| 188 | #define I2C1_SDA 0x0124 | |
| 189 | #define I2C2_SCL 0x0126 | |
| 190 | #define I2C2_SDA 0x0128 | |
| 191 | #define I2C3_SCL 0x012A | |
| 192 | #define I2C3_SDA 0x012C | |
| 193 | #define I2C4_SCL 0x012E | |
| 194 | #define I2C4_SDA 0x0130 | |
| 195 | #define MCSPI1_CLK 0x0132 | |
| 196 | #define MCSPI1_SOMI 0x0134 | |
| 197 | #define MCSPI1_SIMO 0x0136 | |
| 198 | #define MCSPI1_CS0 0x0138 | |
| 199 | #define MCSPI1_CS1 0x013A | |
| 200 | #define MCSPI1_CS2 0x013C | |
| 201 | #define MCSPI1_CS3 0x013E | |
| 202 | #define UART3_CTS_RCTX 0x0140 | |
| 203 | #define UART3_RTS_SD 0x0142 | |
| 204 | #define UART3_RX_IRRX 0x0144 | |
| 205 | #define UART3_TX_IRTX 0x0146 | |
| 206 | #define SDMMC5_CLK 0x0148 | |
| 207 | #define SDMMC5_CMD 0x014A | |
| 208 | #define SDMMC5_DAT0 0x014C | |
| 209 | #define SDMMC5_DAT1 0x014E | |
| 210 | #define SDMMC5_DAT2 0x0150 | |
| 211 | #define SDMMC5_DAT3 0x0152 | |
| 212 | #define MCSPI4_CLK 0x0154 | |
| 213 | #define MCSPI4_SIMO 0x0156 | |
| 214 | #define MCSPI4_SOMI 0x0158 | |
| 215 | #define MCSPI4_CS0 0x015A | |
| 216 | #define UART4_RX 0x015C | |
| 217 | #define UART4_TX 0x015E | |
| 218 | #define USBB2_ULPITLL_CLK 0x0160 | |
| 219 | #define USBB2_ULPITLL_STP 0x0162 | |
| 220 | #define USBB2_ULPITLL_DIR 0x0164 | |
| 221 | #define USBB2_ULPITLL_NXT 0x0166 | |
| 222 | #define USBB2_ULPITLL_DAT0 0x0168 | |
| 223 | #define USBB2_ULPITLL_DAT1 0x016A | |
| 224 | #define USBB2_ULPITLL_DAT2 0x016C | |
| 225 | #define USBB2_ULPITLL_DAT3 0x016E | |
| 226 | #define USBB2_ULPITLL_DAT4 0x0170 | |
| 227 | #define USBB2_ULPITLL_DAT5 0x0172 | |
| 228 | #define USBB2_ULPITLL_DAT6 0x0174 | |
| 229 | #define USBB2_ULPITLL_DAT7 0x0176 | |
| 230 | #define USBB2_HSIC_DATA 0x0178 | |
| 231 | #define USBB2_HSIC_STROBE 0x017A | |
| 232 | #define UNIPRO_TX0 0x017C | |
| 233 | #define UNIPRO_TY0 0x017E | |
| 234 | #define UNIPRO_TX1 0x0180 | |
| 235 | #define UNIPRO_TY1 0x0182 | |
| 236 | #define UNIPRO_TX2 0x0184 | |
| 237 | #define UNIPRO_TY2 0x0186 | |
| 238 | #define UNIPRO_RX0 0x0188 | |
| 239 | #define UNIPRO_RY0 0x018A | |
| 240 | #define UNIPRO_RX1 0x018C | |
| 241 | #define UNIPRO_RY1 0x018E | |
| 242 | #define UNIPRO_RX2 0x0190 | |
| 243 | #define UNIPRO_RY2 0x0192 | |
| 244 | #define USBA0_OTG_CE 0x0194 | |
| 245 | #define USBA0_OTG_DP 0x0196 | |
| 246 | #define USBA0_OTG_DM 0x0198 | |
| 247 | #define FREF_CLK1_OUT 0x019A | |
| 248 | #define FREF_CLK2_OUT 0x019C | |
| 249 | #define SYS_NIRQ1 0x019E | |
| 250 | #define SYS_NIRQ2 0x01A0 | |
| 251 | #define SYS_BOOT0 0x01A2 | |
| 252 | #define SYS_BOOT1 0x01A4 | |
| 253 | #define SYS_BOOT2 0x01A6 | |
| 254 | #define SYS_BOOT3 0x01A8 | |
| 255 | #define SYS_BOOT4 0x01AA | |
| 256 | #define SYS_BOOT5 0x01AC | |
| 257 | #define DPM_EMU0 0x01AE | |
| 258 | #define DPM_EMU1 0x01B0 | |
| 259 | #define DPM_EMU2 0x01B2 | |
| 260 | #define DPM_EMU3 0x01B4 | |
| 261 | #define DPM_EMU4 0x01B6 | |
| 262 | #define DPM_EMU5 0x01B8 | |
| 263 | #define DPM_EMU6 0x01BA | |
| 264 | #define DPM_EMU7 0x01BC | |
| 265 | #define DPM_EMU8 0x01BE | |
| 266 | #define DPM_EMU9 0x01C0 | |
| 267 | #define DPM_EMU10 0x01C2 | |
| 268 | #define DPM_EMU11 0x01C4 | |
| 269 | #define DPM_EMU12 0x01C6 | |
| 270 | #define DPM_EMU13 0x01C8 | |
| 271 | #define DPM_EMU14 0x01CA | |
| 272 | #define DPM_EMU15 0x01CC | |
| 273 | #define DPM_EMU16 0x01CE | |
| 274 | #define DPM_EMU17 0x01D0 | |
| 275 | #define DPM_EMU18 0x01D2 | |
| 276 | #define DPM_EMU19 0x01D4 | |
| 277 | #define WAKEUPEVENT_0 0x01D8 | |
| 278 | #define WAKEUPEVENT_1 0x01DC | |
| 279 | #define WAKEUPEVENT_2 0x01E0 | |
| 280 | #define WAKEUPEVENT_3 0x01E4 | |
| 281 | #define WAKEUPEVENT_4 0x01E8 | |
| 282 | #define WAKEUPEVENT_5 0x01EC | |
| 283 | #define WAKEUPEVENT_6 0x01F0 | |
| 284 | ||
| 285 | #define WKUP_REVISION 0x0000 | |
| 286 | #define WKUP_HWINFO 0x0004 | |
| 287 | #define WKUP_SYSCONFIG 0x0010 | |
| 288 | #define PAD0_SIM_IO 0x0040 | |
| 289 | #define PAD1_SIM_CLK 0x0042 | |
| 290 | #define PAD0_SIM_RESET 0x0044 | |
| 291 | #define PAD1_SIM_CD 0x0046 | |
| 292 | #define PAD0_SIM_PWRCTRL 0x0048 | |
| 293 | #define PAD1_SR_SCL 0x004A | |
| 294 | #define PAD0_SR_SDA 0x004C | |
| 295 | #define PAD1_FREF_XTAL_IN 0x004E | |
| 296 | #define PAD0_FREF_SLICER_IN 0x0050 | |
| 297 | #define PAD1_FREF_CLK_IOREQ 0x0052 | |
| 298 | #define PAD0_FREF_CLK0_OUT 0x0054 | |
| 299 | #define PAD1_FREF_CLK3_REQ 0x0056 | |
| 300 | #define PAD0_FREF_CLK3_OUT 0x0058 | |
| 301 | #define PAD1_FREF_CLK4_REQ 0x005A | |
| 302 | #define PAD0_FREF_CLK4_OUT 0x005C | |
| 303 | #define PAD1_SYS_32K 0x005E | |
| 304 | #define PAD0_SYS_NRESPWRON 0x0060 | |
| 305 | #define PAD1_SYS_NRESWARM 0x0062 | |
| 306 | #define PAD0_SYS_PWR_REQ 0x0064 | |
| 307 | #define PAD1_SYS_PWRON_RESET 0x0066 | |
| 308 | #define PAD0_SYS_BOOT6 0x0068 | |
| 309 | #define PAD1_SYS_BOOT7 0x006A | |
| 310 | #define PAD0_JTAG_NTRST 0x006C | |
| 311 | #define PAD1_JTAG_TCK 0x006D | |
| 312 | #define PAD0_JTAG_RTCK 0x0070 | |
| 313 | #define PAD1_JTAG_TMS_TMSC 0x0072 | |
| 314 | #define PAD0_JTAG_TDI 0x0074 | |
| 315 | #define PAD1_JTAG_TDO 0x0076 | |
| 316 | #define PADCONF_WAKEUPEVENT_0 0x007C | |
| 317 | #define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 | |
| 318 | #define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 | |
| 319 | #define PADCONF_MODE 0x05A8 | |
| 320 | #define CONTROL_XTAL_OSCILLATOR 0x05AC | |
| 321 | #define CONTROL_CONTROL_I2C_2 0x0604 | |
| 322 | #define CONTROL_CONTROL_JTAG 0x0608 | |
| 323 | #define CONTROL_CONTROL_SYS 0x060C | |
| 324 | #define CONTROL_SPARE_RW 0x0614 | |
| 325 | #define CONTROL_SPARE_R 0x0618 | |
| 326 | #define CONTROL_SPARE_R_C0 0x061C | |
| 327 | ||
| d506719f | 328 | #define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A |
| 2ad853c3 | 329 | #endif /* _MUX_OMAP4_H_ */ |