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d34efc76 SS |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Authors: | |
6 | * Aneesh V <aneesh@ti.com> | |
7 | * | |
8 | * Derived from OMAP3 work by | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
11 | * | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
d34efc76 SS |
13 | */ |
14 | ||
15 | #ifndef _OMAP4_H_ | |
16 | #define _OMAP4_H_ | |
17 | ||
18 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
19 | #include <asm/types.h> | |
20 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ | |
21 | ||
22 | /* | |
23 | * L4 Peripherals - L4 Wakeup and L4 Core now | |
24 | */ | |
25 | #define OMAP44XX_L4_CORE_BASE 0x4A000000 | |
26 | #define OMAP44XX_L4_WKUP_BASE 0x4A300000 | |
27 | #define OMAP44XX_L4_PER_BASE 0x48000000 | |
28 | ||
7ca3f9c5 A |
29 | #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 |
30 | #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 | |
508a58fa S |
31 | #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START |
32 | #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END | |
7ca3f9c5 | 33 | |
ad577c8a A |
34 | /* CONTROL_ID_CODE */ |
35 | #define CONTROL_ID_CODE 0x4A002204 | |
36 | ||
508a58fa S |
37 | #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F |
38 | #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F | |
39 | #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F | |
40 | #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F | |
41 | #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F | |
9404758e A |
42 | #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F |
43 | #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F | |
8f6a027f | 44 | |
d34efc76 SS |
45 | /* UART */ |
46 | #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) | |
47 | #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) | |
48 | #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) | |
49 | ||
50 | /* General Purpose Timers */ | |
51 | #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) | |
52 | #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) | |
53 | #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) | |
54 | ||
55 | /* Watchdog Timer2 - MPU watchdog */ | |
56 | #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) | |
57 | ||
d34efc76 | 58 | /* GPMC */ |
27952014 | 59 | #define OMAP44XX_GPMC_BASE 0x50000000 |
d34efc76 SS |
60 | |
61 | /* | |
62 | * Hardware Register Details | |
63 | */ | |
64 | ||
65 | /* Watchdog Timer */ | |
66 | #define WD_UNLOCK1 0xAAAA | |
67 | #define WD_UNLOCK2 0x5555 | |
68 | ||
69 | /* GP Timer */ | |
70 | #define TCLR_ST (0x1 << 0) | |
71 | #define TCLR_AR (0x1 << 1) | |
72 | #define TCLR_PRE (0x1 << 5) | |
73 | ||
4ecfcfaa A |
74 | /* Control Module */ |
75 | #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) | |
76 | #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f | |
77 | #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 | |
fe7104b3 | 78 | #define CONTROL_EFUSE_2_OVERRIDE 0x99084000 |
4ecfcfaa A |
79 | |
80 | /* LPDDR2 IO regs */ | |
81 | #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C | |
82 | #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E | |
83 | #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C | |
84 | #define LPDDR2IO_GR10_WD_MASK (3 << 17) | |
e423a8f7 | 85 | #define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F |
4ecfcfaa A |
86 | |
87 | /* CONTROL_EFUSE_2 */ | |
88 | #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 | |
89 | ||
14fa2dd0 B |
90 | #define MMC1_PWRDNZ (1 << 26) |
91 | #define MMC1_PBIASLITE_PWRDNZ (1 << 22) | |
92 | #define MMC1_PBIASLITE_VMODE (1 << 21) | |
93 | ||
d34efc76 SS |
94 | #ifndef __ASSEMBLY__ |
95 | ||
96 | struct s32ktimer { | |
97 | unsigned char res[0x10]; | |
98 | unsigned int s32k_cr; /* 0x10 */ | |
99 | }; | |
100 | ||
c1fa3c37 S |
101 | #define DEVICE_TYPE_SHIFT (0x8) |
102 | #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) | |
103 | #define DEVICE_GP 0x3 | |
104 | ||
d34efc76 SS |
105 | #endif /* __ASSEMBLY__ */ |
106 | ||
107 | /* | |
108 | * Non-secure SRAM Addresses | |
109 | * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE | |
110 | * at 0x40304000(EMU base) so that our code works for both EMU and GP | |
111 | */ | |
112 | #define NON_SECURE_SRAM_START 0x40304000 | |
113 | #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ | |
edfcf85a | 114 | #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START |
d34efc76 SS |
115 | /* base address for indirect vectors (internal boot mode) */ |
116 | #define SRAM_ROM_VECT_BASE 0x4030D000 | |
4d0df9c1 AT |
117 | |
118 | /* ABB settings */ | |
119 | #define OMAP_ABB_SETTLING_TIME 50 | |
120 | #define OMAP_ABB_CLOCK_CYCLES 16 | |
121 | ||
122 | /* ABB tranxdone mask */ | |
123 | #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) | |
124 | ||
d34efc76 | 125 | #endif |