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eda6fbcc LV |
1 | /* |
2 | * (C) Copyright 2015 | |
3 | * Texas Instruments Incorporated | |
4 | * | |
5 | * Lokesh Vutla <lokeshvutla@ti.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef _DRA7_IODELAY_H_ | |
11 | #define _DRA7_IODELAY_H_ | |
12 | ||
13 | #include <common.h> | |
14 | #include <asm/arch/sys_proto.h> | |
15 | ||
16 | /* CONFIG_REG_0 */ | |
17 | #define CFG_REG_0_OFFSET 0xC | |
18 | #define CFG_REG_ROM_READ_SHIFT 1 | |
19 | #define CFG_REG_ROM_READ_MASK (1 << 1) | |
20 | #define CFG_REG_CALIB_STRT_SHIFT 0 | |
21 | #define CFG_REG_CALIB_STRT_MASK (1 << 0) | |
22 | #define CFG_REG_CALIB_STRT 1 | |
23 | #define CFG_REG_CALIB_END 0 | |
24 | #define CFG_REG_ROM_READ_START (1 << 1) | |
25 | #define CFG_REG_ROM_READ_END (0 << 1) | |
26 | ||
27 | /* CONFIG_REG_2 */ | |
28 | #define CFG_REG_2_OFFSET 0x14 | |
29 | #define CFG_REG_REFCLK_PERIOD_SHIFT 0 | |
30 | #define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) | |
31 | #define CFG_REG_REFCLK_PERIOD 0x2EF | |
32 | ||
33 | /* CONFIG_REG_8 */ | |
34 | #define CFG_REG_8_OFFSET 0x2C | |
35 | #define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA | |
36 | #define CFG_IODELAY_LOCK_KEY 0x0000AAAB | |
37 | ||
71bed185 LV |
38 | /* CONFIG_REG_3/4 */ |
39 | #define CFG_REG_3_OFFSET 0x18 | |
40 | #define CFG_REG_4_OFFSET 0x1C | |
41 | #define CFG_REG_DLY_CNT_SHIFT 16 | |
42 | #define CFG_REG_DLY_CNT_MASK (0xFFFF << 16) | |
43 | #define CFG_REG_REF_CNT_SHIFT 0 | |
44 | #define CFG_REG_REF_CNT_MASK (0xFFFF << 0) | |
45 | ||
eda6fbcc LV |
46 | /* CTRL_CORE_SMA_SW_0 */ |
47 | #define CTRL_ISOLATE_SHIFT 2 | |
48 | #define CTRL_ISOLATE_MASK (1 << 2) | |
49 | #define ISOLATE_IO 1 | |
50 | #define DEISOLATE_IO 0 | |
51 | ||
52 | /* PRM_IO_PMCTRL */ | |
53 | #define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 | |
54 | #define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) | |
55 | #define PMCTRL_ISOCLK_STATUS_SHIFT 1 | |
56 | #define PMCTRL_ISOCLK_STATUS_MASK (1 << 1) | |
57 | #define PMCTRL_ISOCLK_OVERRIDE_CTRL 1 | |
58 | #define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0 | |
59 | ||
60 | #define ERR_CALIBRATE_IODELAY 0x1 | |
61 | #define ERR_DEISOLATE_IO 0x2 | |
62 | #define ERR_ISOLATE_IO 0x4 | |
63 | #define ERR_UPDATE_DELAY 0x8 | |
71bed185 LV |
64 | #define ERR_CPDE 0x3 |
65 | #define ERR_FPDE 0x5 | |
66 | ||
67 | /* CFG_XXX */ | |
68 | #define CFG_X_SIGNATURE_SHIFT 12 | |
69 | #define CFG_X_SIGNATURE_MASK (0x3F << 12) | |
70 | #define CFG_X_LOCK_SHIFT 10 | |
71 | #define CFG_X_LOCK_MASK (0x1 << 10) | |
72 | #define CFG_X_COARSE_DLY_SHIFT 5 | |
73 | #define CFG_X_COARSE_DLY_MASK (0x1F << 5) | |
74 | #define CFG_X_FINE_DLY_SHIFT 0 | |
75 | #define CFG_X_FINE_DLY_MASK (0x1F << 0) | |
76 | #define CFG_X_SIGNATURE 0x29 | |
77 | #define CFG_X_LOCK 1 | |
78 | ||
79 | void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, | |
80 | struct iodelay_cfg_entry const *iodelay, | |
81 | int niodelays); | |
eda6fbcc | 82 | |
eda6fbcc | 83 | #endif |